SPRUIE9D
May 2017 – May 2024
DRA74P
,
DRA75P
,
DRA76P
,
DRA77P
1
Read This First
Support Resources
About This Manual
Information About Cautions and Warnings
Register, Field, and Bit Calls
Coding Rules
Flow Chart Rules
Glossary
Export Control Notice
DRA75xP, DRA74xP, DRA77xP, DRA76xP MIPI® Disclaimer
Trademarks
1
Introduction
1.1
DRA75xP, DRA74xP, DRA77xP, DRA76xP Overview
1.2
DRA75xP, DRA74xP, DRA77xP, DRA76xP Environment
1.3
DRA75xP, DRA74xP, DRA77xP, DRA76xP Description
1.3.1
MPU Subsystem
1.3.2
DSP Subsystems
1.3.3
EVE Subsystems
1.3.4
Imaging Subsystem
1.3.5
Camera Interface Subsystem
1.3.6
IPU Subsystems
1.3.7
IVA-HD Subsystem
1.3.8
Display Subsystem
1.3.9
Video Processing Subsystem
1.3.10
Video Capture
1.3.11
3D GPU Subsystem
1.3.12
BB2D Subsystem
1.3.13
On-Chip Debug Support
1.3.14
Power, Reset, and Clock Management
1.3.15
On-Chip Memory
1.3.16
Memory Management
1.3.17
External Memory Interfaces
1.3.18
System and Connectivity Peripherals
1.3.18.1
System Peripherals
1.3.18.2
Media Connectivity Peripherals
1.3.18.3
Car Connectivity Peripherals
1.3.18.4
Audio Connectivity Peripherals
1.3.18.5
Serial Control Peripherals
1.3.18.6
Radio Accelerators
1.4
DRA75xP, DRA74xP, DRA77xP, DRA76xP Family
1.5
DRA75xP, DRA74xP, DRA77xP, DRA76xP Device Identification
1.6
DRA75xP, DRA74xP, DRA77xP, DRA76xP Package Characteristics Overview
2
Memory Mapping
2.1
Introduction
2.2
L3_MAIN Memory Map
2.2.1
L3_INSTR Memory Map
2.3
L4 Memory Map
2.3.1
L4_CFG Memory Map
2.3.2
L4_WKUP Memory Map
2.4
L4_PER Memory Map
2.4.1
L4_PER1 Memory Space Mapping
2.4.2
L4_PER2 Memory Map
2.4.3
L4_PER3 Memory Map
2.5
MPU Memory Map
2.6
IPU Memory Map
2.7
DSP Memory Map
2.8
EVE Memory Map
2.9
TILER View Memory Map
3
Power, Reset, and Clock Management
3.1
Device Power Management Introduction
3.1.1
Device Power-Management Architecture Building Blocks
3.1.1.1
Clock Management
3.1.1.1.1
Module Interface and Functional Clocks
3.1.1.1.2
65
3.1.1.1.3
Module-Level Clock Management
3.1.1.1.4
Clock Domain
3.1.1.1.5
Clock Domain-Level Clock Management
3.1.1.1.6
Clock Domain HW_AUTO Mode Sequences
3.1.1.1.7
Clock Domain Sleep/Wake-up
3.1.1.1.8
Clock Domain Dependency
3.1.1.1.8.1
Static Dependency
3.1.1.1.8.2
Dynamic Dependency
3.1.1.1.8.3
Wake-Up Dependency
3.1.1.2
Power Management
3.1.1.2.1
Power Domain
3.1.1.2.2
Module Logic and Memory Context
3.1.1.2.3
Power Domain Management
3.1.1.3
Voltage Management
3.1.1.3.1
Voltage Domain
3.1.1.3.2
Voltage Domain Management
3.1.1.3.3
AVS Overview
3.1.1.3.3.1
AVS Class 0 (SmartReflex™) Voltage Control
3.1.2
Power-Management Techniques
3.1.2.1
Standby Leakage Management
3.1.2.2
Dynamic Voltage and Frequency Scaling
3.1.2.3
Dynamic Power Switching
3.1.2.4
Adaptive Voltage Scaling
3.1.2.5
Adaptive Body Bias
3.1.2.6
SR3-APG (Automatic Power Gating)
3.1.2.7
Combining Power-Management Techniques
3.1.2.7.1
DPS Versus SLM
3.2
PRCM Subsystem Overview
3.2.1
Introduction
3.2.2
Power-Management Framework Features
3.3
PRCM Subsystem Environment
3.3.1
External Clock Signals
3.3.2
External Boot Signals
3.3.3
External Reset Signals
3.3.4
External Voltage Inputs
3.4
PRCM Subsystem Integration
3.4.1
Device Power-Management Layout
3.4.2
Power-Management Scheme, Reset, and Interrupt Requests
3.4.2.1
Power Domain
3.4.2.2
Resets
3.4.2.3
PRCM Interrupt Requests
3.4.2.4
107
3.5
Reset Management Functional Description
3.5.1
Overview
3.5.1.1
PRCM Reset Management Functional Description
3.5.1.1.1
Power-On Reset
3.5.1.1.2
Warm Reset
3.5.1.2
PRM Reset Management Functional Description
3.5.2
General Characteristics of Reset Signals
3.5.2.1
Scope
3.5.2.2
Occurrence
3.5.2.3
Source Type
3.5.2.4
Retention Type
3.5.3
Reset Sources
3.5.3.1
Global Reset Sources
3.5.3.2
Local Reset Sources
3.5.4
Reset Logging
3.5.5
Reset Domains
3.5.6
Reset Sequences
3.5.6.1
MPU Subsystem Power-On Reset Sequence
3.5.6.2
MPU Subsystem Warm Reset Sequence
3.5.6.3
MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION State
3.5.6.4
IVA Subsystem Power-On Reset Sequence
3.5.6.5
IVA Subsystem Software Warm Reset Sequence
3.5.6.6
DSP1 Subsystem Power-On Reset Sequence
3.5.6.7
DSP1 Subsystem Software Warm Reset Sequence
3.5.6.8
DSP2 Subsystem Power-On Reset Sequence
3.5.6.9
DSP2 Subsystem Software Warm Reset Sequence
3.5.6.10
IPU1 Subsystem Power-On Reset Sequence
3.5.6.11
IPU1 Subsystem Software Warm Reset Sequence
3.5.6.12
IPU2 Subsystem Power-On Reset Sequence
3.5.6.13
IPU2 Subsystem Software Warm Reset Sequence
3.5.6.14
EVE1 Subsystem Power-On Reset Sequence
3.5.6.15
EVE1 Subsystem Software Warm Reset Sequence
3.5.6.16
EVE2 Subsystem Power-On Reset Sequence
3.5.6.17
EVE2 Subsystem Software Warm Reset Sequence
3.5.6.18
Global Warm Reset Sequence
3.6
Clock Management Functional Description
3.6.1
Overview
3.6.2
External Clock Inputs
3.6.2.1
FUNC_32K_CLK Clock
3.6.2.2
High-Frequency System Clock Input
3.6.2.3
External Reference Clock Input
3.6.3
Internal Clock Sources and Generators
3.6.3.1
PRM Clock Source
3.6.3.2
CM Clock Source
3.6.3.2.1
CM_CORE_AON Clock Generator
3.6.3.2.2
CM_CORE_AON_CLKOUTMUX Overview
3.6.3.2.3
CM_CORE_AON_TIMER Overview
3.6.3.2.4
CM_CORE_AON_MCASP Overview
3.6.3.3
Generic DPLL Overview
3.6.3.3.1
Generic APLL Overview
3.6.3.3.2
DPLLs Output Clocks Parameters
3.6.3.3.3
Enable Control, Status, and Low-Power Operation Mode
3.6.3.3.4
DPLL Power Modes
3.6.3.3.5
DPLL Recalibration
3.6.3.3.6
DPLL Output Power Down
3.6.3.4
DPLL_PER Description
3.6.3.4.1
DPLL_PER Overview
3.6.3.4.2
DPLL_PER Synthesized Clock Parameters
3.6.3.4.3
DPLL_PER Power Modes
3.6.3.4.4
DPLL_PER Recalibration
3.6.3.5
DPLL_CORE Description
3.6.3.5.1
DPLL_CORE Overview
3.6.3.5.2
DPLL_CORE Synthesized Clock Parameters
3.6.3.5.3
DPLL_CORE Power Modes
3.6.3.5.4
DPLL_CORE Recalibration
3.6.3.6
DPLL_ABE Description
3.6.3.6.1
DPLL_ABE Overview
3.6.3.6.2
DPLL_ABE Synthesized Clock Parameters
3.6.3.6.3
DPLL_ABE Power Modes
3.6.3.6.4
DPLL_ABE Recalibration
3.6.3.6.5
Fractional M-factor
3.6.3.7
DPLL_MPU Description
3.6.3.7.1
DPLL_MPU Overview
3.6.3.7.2
DPLL_MPU Tactical Clocking Adjustment
3.6.3.7.3
DPLL_MPU Synthesized Clock Parameters
3.6.3.7.4
DPLL_MPU Power Modes
3.6.3.7.5
DPLL_MPU Recalibration
3.6.3.8
DPLL_IVA Description
3.6.3.8.1
DPLL_IVA Overview
3.6.3.8.2
DPLL_IVA Synthesized Clock Parameters
3.6.3.8.3
DPLL_IVA Power Modes
3.6.3.8.4
DPLL_IVA Recalibration
3.6.3.9
DPLL_USB Description
3.6.3.9.1
DPLL_USB Overview
3.6.3.9.2
DPLL_USB Synthesized Clock Parameters
3.6.3.9.3
DPLL_USB Power Modes
3.6.3.9.4
DPLL_USB Recalibration
3.6.3.10
DPLL_EVE Description
3.6.3.10.1
DPLL_EVE Overview
3.6.3.10.2
DPLL_EVE Synthesized Clock Parameters
3.6.3.10.3
DPLL_EVE Power Modes
3.6.3.10.4
DPLL_EVE Recalibration
3.6.3.11
DPLL_DSP Description
3.6.3.11.1
DPLL_DSP Overview
3.6.3.11.2
DPLL_DSP Synthesized Clock Parameters
3.6.3.11.3
DPLL_DSP Power Modes
3.6.3.11.4
DPLL_DSP Recalibration
3.6.3.12
DPLL_GMAC Description
3.6.3.12.1
DPLL_GMAC Overview
3.6.3.12.2
DPLL_GMAC Synthesized Clock Parameters
3.6.3.12.3
DPLL_GMAC Power Modes
3.6.3.12.4
DPLL_GMAC Recalibration
3.6.3.13
DPLL_GPU Description
3.6.3.13.1
DPLL_GPU Overview
3.6.3.13.2
DPLL_GPU Synthesized Clock Parameters
3.6.3.13.3
DPLL_GPU Power Modes
3.6.3.13.4
DPLL_GPU Recalibration
3.6.3.14
DPLL_DDR Description
3.6.3.14.1
DPLL_DDR Overview
3.6.3.14.2
DPLL_DDR Synthesized Clock Parameters
3.6.3.14.3
DPLL_DDR Power Modes
3.6.3.14.4
DPLL_DDR Recalibration
3.6.3.15
DPLL_PCIE_REF Description
3.6.3.15.1
DPLL_PCIE_REF Overview
3.6.3.15.2
DPLL_PCIE_REF Synthesized Clock Parameters
3.6.3.15.3
DPLL_PCIE_REF Power Modes
3.6.3.16
APLL_PCIE Description
3.6.3.16.1
APLL_PCIE Overview
3.6.3.16.2
APLL_PCIE Synthesized Clock Parameters
3.6.3.16.3
APLL_PCIE Power Modes
3.6.4
Clock Domains
3.6.4.1
CD_WKUPAON Clock Domain
3.6.4.1.1
Overview
3.6.4.1.2
Clock Domain Modes
3.6.4.1.3
Clock Domain Dependency
3.6.4.1.3.1
Wake-Up Dependency
3.6.4.1.4
Clock Domain Module Attributes
3.6.4.2
CD_DSP1 Clock Domain
3.6.4.2.1
Overview
3.6.4.2.2
Clock Domain Modes
3.6.4.2.3
Clock Domain Dependency
3.6.4.2.3.1
Static Dependency
3.6.4.2.3.2
Dynamic Dependency
3.6.4.2.4
Clock Domain Module Attributes
3.6.4.3
CD_DSP2 Clock Domain
3.6.4.3.1
Overview
3.6.4.3.2
Clock Domain Modes
3.6.4.3.3
Clock Domain Dependency
3.6.4.3.3.1
Static Dependency
3.6.4.3.3.2
Dynamic Dependency
3.6.4.3.4
Clock Domain Module Attributes
3.6.4.4
CD_CUSTEFUSE Clock Domain
3.6.4.4.1
Overview
3.6.4.4.2
Clock Domain Modes
3.6.4.4.3
Clock Domain Dependency
3.6.4.4.4
Clock Domain Module Attributes
3.6.4.5
CD_MPU Clock Domain
3.6.4.5.1
Overview
3.6.4.5.2
Clock Domain Modes
3.6.4.5.3
Clock Domain Dependency
3.6.4.5.3.1
Static Dependency
3.6.4.5.3.2
Dynamic Dependency
3.6.4.5.4
Clock Domain Module Attributes
3.6.4.6
CD_L4PER1 Clock Domain
3.6.4.6.1
Overview
3.6.4.6.2
Clock Domain Modes
3.6.4.6.3
Clock Domain Dependency
3.6.4.6.3.1
Dynamic Dependency
3.6.4.6.3.2
Wake-Up Dependency
3.6.4.6.4
Clock Domain Module Attributes
3.6.4.7
CD_L4PER2 Clock Domain
3.6.4.7.1
Overview
3.6.4.7.2
Clock Domain Modes
3.6.4.7.3
Clock Domain Dependency
3.6.4.7.3.1
Dynamic Dependency
3.6.4.7.3.2
Wake-Up Dependency
3.6.4.7.4
Clock Domain Module Attributes
3.6.4.8
CD_L4PER3 Clock Domain
3.6.4.8.1
Overview
3.6.4.8.2
Clock Domain Modes
3.6.4.8.3
Clock Domain Dependency
3.6.4.8.3.1
Dynamic Dependency
3.6.4.8.3.2
Wake-Up Dependency
3.6.4.8.4
Clock Domain Module Attributes
3.6.4.9
CD_L4SEC Clock Domain
3.6.4.9.1
Overview
3.6.4.9.2
Clock Domain Modes
3.6.4.9.3
Clock Domain Dependency
3.6.4.9.3.1
Static Dependency
3.6.4.9.3.2
Dynamic Dependency
3.6.4.9.4
Clock Domain Module Attributes
3.6.4.9.5
289
3.6.4.10
CD_L3INIT Clock Domain
3.6.4.10.1
Overview
3.6.4.10.2
Clock Domain Modes
3.6.4.10.3
Clock Domain Dependency
3.6.4.10.3.1
Static Dependency
3.6.4.10.3.2
Dynamic Dependency
3.6.4.10.3.3
Wake-Up Dependency
3.6.4.10.4
Clock Domain Module Attributes
3.6.4.11
CD_IVA Clock Domain
3.6.4.11.1
Overview
3.6.4.11.2
Clock Domain Modes
3.6.4.11.3
Clock Domain Dependency
3.6.4.11.3.1
Static Dependency
3.6.4.11.3.2
Dynamic Dependency
3.6.4.11.4
Clock Domain Module Attributes
3.6.4.12
CD_GPU Description
3.6.4.12.1
Overview
3.6.4.12.2
Clock Domain Modes
3.6.4.12.3
Clock Domain Dependency
3.6.4.12.3.1
Static Dependency
3.6.4.12.3.2
Dynamic Dependency
3.6.4.12.4
Clock Domain Module Attributes
3.6.4.13
CD_EMU Clock Domain
3.6.4.13.1
Overview
3.6.4.13.2
Clock Domain Modes
3.6.4.13.3
Clock Domain Dependency
3.6.4.13.3.1
Dynamic Dependency
3.6.4.13.4
Clock Domain Module Attributes
3.6.4.14
CD_DSS Clock Domain
3.6.4.14.1
Overview
3.6.4.14.2
Clock Domain Modes
3.6.4.14.3
Clock Domain Dependency
3.6.4.14.3.1
Static Dependency
3.6.4.14.3.2
Dynamic Dependency
3.6.4.14.3.3
Wake-Up Dependency
3.6.4.14.4
Clock Domain Module Attributes
3.6.4.15
CD_L4_CFG Clock Domain
3.6.4.15.1
Overview
3.6.4.15.2
Clock Domain Modes
3.6.4.15.3
Clock Domain Dependency
3.6.4.15.3.1
Dynamic Dependency
3.6.4.15.4
Clock Domain Module Attributes
3.6.4.16
CD_L3_INSTR Clock Domain
3.6.4.16.1
Overview
3.6.4.16.2
Clock Domain Modes
3.6.4.16.3
Clock Domain Dependency
3.6.4.16.4
Clock Domain Module Attributes
3.6.4.17
CD_L3_MAIN1 Clock Domain
3.6.4.17.1
Overview
3.6.4.17.2
Clock Domain Modes
3.6.4.17.3
Clock Domain Dependency
3.6.4.17.3.1
Dynamic Dependency
3.6.4.17.4
Clock Domain Module Attributes
3.6.4.18
CD_EMIF Clock Domain
3.6.4.18.1
Overview
3.6.4.18.2
Clock Domain Modes
3.6.4.18.3
Clock Domain Dependency
3.6.4.18.4
Clock Domain Module Attributes
3.6.4.19
CD_IPU Clock Domain
3.6.4.19.1
Overview
3.6.4.19.2
Clock Domain Modes
3.6.4.19.3
Clock Domain Dependency
3.6.4.19.3.1
Static Dependency
3.6.4.19.3.2
Dynamic Dependency
3.6.4.19.4
Clock Domain Module Attributes
3.6.4.20
CD_IPU1 Clock Domain
3.6.4.20.1
Overview
3.6.4.20.2
Clock Domain Modes
3.6.4.20.3
Clock Domain Dependency
3.6.4.20.3.1
Static Dependency
3.6.4.20.3.2
Dynamic Dependency
3.6.4.20.4
Clock Domain Module Attributes
3.6.4.21
CD_IPU2 Clock Domain
3.6.4.21.1
Overview
3.6.4.21.2
Clock Domain Modes
3.6.4.21.3
Clock Domain Dependency
3.6.4.21.3.1
Static Dependency
3.6.4.21.3.2
Dynamic Dependency
3.6.4.21.4
Clock Domain Module Attributes
3.6.4.22
CD_DMA Clock Domain
3.6.4.22.1
Overview
3.6.4.22.2
Clock Domain Modes
3.6.4.22.3
Clock Domain Dependency
3.6.4.22.3.1
Static Dependency
3.6.4.22.3.2
Dynamic Dependency
3.6.4.22.4
Clock Domain Module Attributes
3.6.4.23
CD_ATL Clock Domain
3.6.4.23.1
Overview
3.6.4.23.2
Clock Domain Modes
3.6.4.23.3
Clock Domain Module Attributes
3.6.4.24
CD_CAM Clock Domain
3.6.4.24.1
Overview
3.6.4.24.2
Clock Domain Modes
3.6.4.24.3
Clock Domain Dependency
3.6.4.24.3.1
Static Dependency
3.6.4.24.3.2
Dynamic Dependency
3.6.4.24.4
Clock Domain Module Attributes
3.6.4.24.5
387
3.6.4.25
CD_GMAC Clock Domain
3.6.4.25.1
Overview
3.6.4.25.2
Clock Domain Modes
3.6.4.25.3
Clock Domain Dependency
3.6.4.25.3.1
Static Dependency
3.6.4.25.3.2
Dynamic Dependency
3.6.4.25.4
Clock Domain Module Attributes
3.6.4.26
CD_VPE Clock Domain
3.6.4.26.1
CD_VPE Overview
3.6.4.26.2
Clock Domain Modes
3.6.4.26.3
Clock Domain Dependency
3.6.4.26.3.1
Wake-Up Dependency
3.6.4.26.4
Clock Domain Module Attributes
3.6.4.27
CD_EVE1 Clock Domain
3.6.4.27.1
CD_EVE1 Overview
3.6.4.27.2
Clock Domain Modes
3.6.4.27.3
Clock Domain Dependency
3.6.4.27.3.1
Wake-Up Dependency
3.6.4.27.4
Clock Domain Module Attributes
3.6.4.28
CD_EVE2 Clock Domain
3.6.4.28.1
CD_EVE2 Overview
3.6.4.28.2
Clock Domain Modes
3.6.4.28.3
Clock Domain Dependency
3.6.4.28.3.1
Wake-Up Dependency
3.6.4.28.4
Clock Domain Module Attributes
3.6.4.29
CD_EVE3 Clock Domain
3.6.4.29.1
CD_EVE3 Overview
3.6.4.29.2
415
3.6.4.29.3
Clock Domain Modes
3.6.4.29.4
Clock Domain Dependency
3.6.4.29.4.1
Wake-Up Dependency
3.6.4.29.5
Clock Domain Module Attributes
3.6.4.30
CD_RTC Clock Domain
3.6.4.30.1
CD_RTC Overview
3.6.4.30.2
Clock Domain Modes
3.6.4.30.3
Clock Domain Dependency
3.6.4.30.3.1
Wake-Up Dependency
3.6.4.30.4
Clock Domain Module Attributes
3.6.4.31
CD_PCIE Clock Domain
3.6.4.31.1
CD_PCIE Overview
3.6.4.31.2
Clock Domain Modes
3.6.4.31.3
Clock Domain Dependency
3.6.4.31.3.1
Wake-Up Dependency
3.6.4.31.4
Clock Domain Module Attributes
3.7
Power Management Functional Description
3.7.1
PD_WKUPAON Description
3.7.1.1
Power Domain Modes
3.7.1.1.1
Logic and Memory Area Power Modes
3.7.2
PD_DSP1 Description
3.7.2.1
Power Domain Modes
3.7.2.1.1
Logic and Memory Area Power Modes
3.7.2.1.2
Logic and Memory Area Power Modes Control and Status
3.7.3
PD_DSP2 Description
3.7.3.1
Power Domain Modes
3.7.3.1.1
Logic and Memory Area Power Modes
3.7.3.1.2
Logic and Memory Area Power Modes Control and Status
3.7.4
PD_CUSTEFUSE Description
3.7.4.1
Power Domain Modes
3.7.4.1.1
Logic and Memory Area Power Modes
3.7.4.1.2
Logic and Memory Area Power Modes Control and Status
3.7.5
PD_MPU Description
3.7.5.1
Power Domain Modes
3.7.5.1.1
Logic and Memory Area Power Modes
3.7.5.1.2
Logic and Memory Area Power Modes Control and Status
3.7.5.1.3
Power State Override
3.7.6
PD_IPU Description
3.7.6.1
Power Domain Modes
3.7.6.1.1
Logic and Memory Area Power Modes
3.7.6.1.2
Logic and Memory Area Power Modes Control and Status
3.7.7
PD_L3INIT Description
3.7.7.1
Power Domain Modes
3.7.7.1.1
Logic and Memory Area Power Modes
3.7.7.1.2
Logic and Memory Area Power Modes Control and Status
3.7.8
PD_L4PER Description
3.7.8.1
Power Domain Modes
3.7.8.1.1
Logic and Memory Area Power Modes
3.7.8.1.2
Logic and Memory Area Power Modes Control and Status
3.7.9
PD_IVA Description
3.7.9.1
Power Domain Modes
3.7.9.1.1
Logic and Memory Area Power Modes
3.7.9.1.2
Logic and Memory Area Power Modes Control and Status
3.7.10
PD_GPU Description
3.7.10.1
Power Domain Modes
3.7.10.1.1
Logic and Memory Area Power Modes
3.7.10.1.2
Logic and Memory Area Power Modes Control and Status
3.7.11
PD_EMU Description
3.7.11.1
Power Domain Modes
3.7.11.1.1
Logic and Memory Area Power Modes
3.7.11.1.2
Logic and Memory Area Power Modes Control and Status
3.7.12
PD_DSS Description
3.7.12.1
Power Domain Modes
3.7.12.1.1
Logic and Memory Area Power Modes
3.7.12.1.2
Logic and Memory Area Power Mode Control and Status
3.7.13
PD_CORE Description
3.7.13.1
Power Domain Modes
3.7.13.1.1
Logic and Memory Area Power Modes
3.7.13.1.2
Logic and Memory Area Power Mode Control and Status
3.7.14
PD_CAM (Physical PD_COREAON) Description
3.7.14.1
Power Domain Modes
3.7.14.1.1
Logic and Memory Area Power Modes
3.7.14.1.2
Logic and Memory Area Power Mode Control and Status
3.7.15
PD_MPUAON Description
3.7.15.1
Power Domain Modes
3.7.16
PD_MMAON Description
3.7.16.1
Power Domain Modes
3.7.17
PD_COREAON Description
3.7.17.1
Power Domain Modes
3.7.18
PD_VPE Description
3.7.18.1
Power Domain Modes
3.7.18.1.1
Logic and Memory Area Power Modes
3.7.18.1.2
Logic and Memory Area Power Modes Control and Status
3.7.19
PD_EVE1 Description
3.7.19.1
Power Domain Modes
3.7.19.1.1
Logic and Memory Area Power Modes
3.7.19.1.2
Logic and Memory Area Power Modes Control and Status
3.7.20
PD_EVE2 Description
3.7.20.1
Power Domain Modes
3.7.20.1.1
Logic and Memory Area Power Modes
3.7.20.1.2
Logic and Memory Area Power Modes Control and Status
3.7.21
PD_EVE3 Description
3.7.21.1
Power Domain Modes
3.7.21.1.1
Logic and Memory Area Power Modes
3.7.21.1.2
Logic and Memory Area Power Modes Control and Status
3.7.22
PD_RTC Description
3.7.22.1
Power Domain Modes
3.7.22.1.1
Logic and Memory Area Power Modes
3.8
Voltage-Management Functional Description
3.8.1
Overview
3.8.2
Voltage-Control Architecture
3.8.3
Internal LDOs Control
3.8.3.1
VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
3.8.3.1.1
Adaptive Voltage Scaling
3.8.3.1.1.1
SmartReflex in the Device
3.8.3.2
Memory LDOs
3.8.3.3
ABB LDOs Control
3.8.3.4
ABB LDO Programming Sequence
3.8.3.4.1
ABB LDO Enable Sequence
3.8.3.4.2
ABB LDO Disable Sequence (Entering in Bypass Mode)
3.8.3.5
BANDGAPs Control
3.8.4
DVFS
3.9
Device Low-Power States
3.9.1
Device Wake-Up Source Summary
3.9.2
Wakeup Upon Global Warm Reset
3.9.3
Global Warm Reset During a Device Wake-Up Sequence
3.9.4
I/O Management
3.9.4.1
Isolation / Wakeup Sequence
3.9.4.1.1
Software-Controlled I/O Isolation
3.10
PRCM Module Programming Guide
3.10.1
DPLLs Low-Level Programming Models
3.10.1.1
Global Initialization
3.10.1.1.1
Surrounding Module Global Initialization
3.10.1.1.2
DPLL Global Initialization
3.10.1.1.2.1
Main Sequence – DPLL Global Initialization
3.10.1.1.2.2
Subsequence – Recalibration Parameter Configuration
3.10.1.1.2.3
Subsequence – Synthesized Clock Parameter Configuration
3.10.1.1.2.4
Subsequence – Output Clock Parameter Configuration
3.10.1.2
DPLL Output Frequency Change
3.10.2
Clock Management Low-Level Programming Models
3.10.2.1
Global Initialization
3.10.2.1.1
Surrounding Module Global Initialization
3.10.2.1.2
Clock Management Global Initialization
3.10.2.1.2.1
Main Sequence – Clock Domain Global Initialization
3.10.2.1.2.2
Subsequence – Slave Module Clock-Management Parameters Configuration
3.10.2.2
Clock Domain Sleep Transition and Troubleshooting
3.10.2.3
Enable/Disable Software-Programmable Static Dependency
3.10.3
Power Management Low-Level Programming Models
3.10.3.1
Global Initialization
3.10.3.1.1
Surrounding Module Global Initialization
3.10.3.1.2
Power Management Global Initialization
3.10.3.1.2.1
Main Sequence – Power Domain Global Initialization and Setting
3.10.3.2
Forced Memory Area State Change With Power Domain ON
3.10.3.3
Forced Power Domain Low-Power State Transition
3.11
560
3.12
PRCM Software Configuration for OPP_PLUS
3.13
PRCM Register Manual
3.13.1
PRCM Instance Summary
3.13.2
CM_CORE_AON__CKGEN Registers
3.13.2.1
CM_CORE_AON__CKGEN Register Summary
3.13.2.2
CM_CORE_AON__CKGEN Register Description
3.13.3
CM_CORE_AON__DSP1 Registers
3.13.3.1
CM_CORE_AON__DSP1 Register Summary
3.13.3.2
CM_CORE_AON__DSP1 Register Description
3.13.4
CM_CORE_AON__DSP2 Registers
3.13.4.1
CM_CORE_AON__DSP2 Register Summary
3.13.4.2
CM_CORE_AON__DSP2 Register Description
3.13.5
CM_CORE_AON__EVE1 Registers
3.13.5.1
CM_CORE_AON__EVE1 Register Summary
3.13.5.2
CM_CORE_AON__EVE1 Register Description
3.13.6
CM_CORE_AON__EVE2 Registers
3.13.6.1
CM_CORE_AON__EVE2 Register Summary
3.13.6.2
CM_CORE_AON__EVE2 Register Description
3.13.7
CORE_AON__EVE3 Registers
3.13.7.1
CM_CORE_AON__EVE3 Register Summary
3.13.7.2
CM_CORE_AON__EVE3 Register Description
3.13.8
CM_CORE_AON__INSTR Registers
3.13.8.1
CM_CORE_AON__INSTR Register Summary
3.13.8.2
CM_CORE_AON__INSTR Register Description
3.13.9
CM_CORE_AON__IPU Registers
3.13.9.1
CM_CORE_AON__IPU Register Summary
3.13.9.2
CM_CORE_AON__IPU Register Description
3.13.10
CM_CORE_AON__MPU Registers
3.13.10.1
CM_CORE_AON__MPU Register Summary
3.13.10.2
CM_CORE_AON__MPU Register Description
3.13.11
CM_CORE_AON__OCP_SOCKET Registers
3.13.11.1
CM_CORE_AON__OCP_SOCKET Register Summary
3.13.11.2
CM_CORE_AON__OCP_SOCKET Register Description
3.13.12
CM_CORE_AON__RESTORE Registers
3.13.12.1
CM_CORE_AON__RESTORE Register Summary
3.13.12.2
CM_CORE_AON__RESTORE Register Description
3.13.13
CM_CORE_AON__RTC Registers
3.13.13.1
CM_CORE_AON__RTC Register Summary
3.13.13.2
CM_CORE_AON__RTC Register Description
3.13.14
CM_CORE_AON__VPE Registers
3.13.14.1
CM_CORE_AON__VPE Register Summary
3.13.14.2
CM_CORE_AON__VPE Register Description
3.13.15
CM_CORE__CAM Registers
3.13.15.1
CM_CORE__CAM Register Summary
3.13.15.2
CM_CORE__CAM Register Description
3.13.16
CM_CORE__CKGEN Registers
3.13.16.1
CM_CORE__CKGEN Register Summary
3.13.16.2
CM_CORE__CKGEN Register Description
3.13.17
CM_CORE__COREAON Registers
3.13.17.1
CM_CORE__COREAON Register Summary
3.13.17.2
CM_CORE__COREAON Register Description
3.13.18
CM_CORE__CORE Registers
3.13.18.1
CM_CORE__CORE Register Summary
3.13.18.2
CM_CORE__CORE Register Description
3.13.19
CM_CORE__CUSTEFUSE Registers
3.13.19.1
CM_CORE__CUSTEFUSE Register Summary
3.13.19.2
CM_CORE__CUSTEFUSE Register Description
3.13.20
CM_CORE__DSS Registers
3.13.20.1
CM_CORE__DSS Register Summary
3.13.20.2
CM_CORE__DSS Register Description
3.13.21
CM_CORE__GPU Registers
3.13.21.1
CM_CORE__GPU Register Summary
3.13.21.2
CM_CORE__GPU Register Description
3.13.22
CM_CORE__IVA Registers
3.13.22.1
CM_CORE__IVA Register Summary
3.13.22.2
CM_CORE__IVA Register Description
3.13.23
CM_CORE__L3INIT Registers
3.13.23.1
CM_CORE__L3INIT Register Summary
3.13.23.2
CM_CORE__L3INIT Register Description
3.13.24
CM_CORE__L4PER Registers
3.13.24.1
CM_CORE__L4PER Register Summary
3.13.24.2
CM_CORE__L4PER Register Description
3.13.25
CM_CORE__OCP_SOCKET Registers
3.13.25.1
CM_CORE__OCP_SOCKET Register Summary
3.13.25.2
CM_CORE__OCP_SOCKET Register Description
3.13.26
CM_CORE__RESTORE Registers
3.13.26.1
CM_CORE__RESTORE Register Summary
3.13.26.2
CM_CORE__RESTORE Register Description
3.13.27
CAM_PRM Registers
3.13.27.1
CAM_PRM Register Summary
3.13.27.2
CAM_PRM Register Description
3.13.28
CKGEN_PRM Registers
3.13.28.1
CKGEN_PRM Register Summary
3.13.28.2
CKGEN_PRM Register Description
3.13.29
CORE_PRM Registers
3.13.29.1
CORE_PRM Register Summary
3.13.29.2
CORE_PRM Register Description
3.13.30
CUSTEFUSE_PRM Registers
3.13.30.1
CUSTEFUSE_PRM Register Summary
3.13.30.2
CUSTEFUSE_PRM Register Description
3.13.31
DEVICE_PRM Registers
3.13.31.1
DEVICE_PRM Register Summary
3.13.31.2
DEVICE_PRM Register Description
3.13.32
DSP1_PRM Registers
3.13.32.1
DSP1_PRM Register Summary
3.13.32.2
DSP1_PRM Register Description
3.13.33
DSP2_PRM Registers
3.13.33.1
DSP2_PRM Register Summary
3.13.33.2
DSP2_PRM Register Description
3.13.34
DSS_PRM Registers
3.13.34.1
DSS_PRM Register Summary
3.13.34.2
DSS_PRM Register Description
3.13.35
EMU_CM Registers
3.13.35.1
EMU_CM Register Summary
3.13.35.2
EMU_CM Register Description
3.13.36
EMU_PRM Registers
3.13.36.1
EMU_PRM Register Summary
3.13.36.2
EMU_PRM Register Description
3.13.37
EVE1_PRM Registers
3.13.37.1
EVE1_PRM Register Summary
3.13.37.2
EVE1_PRM Register Description
3.13.38
EVE2_PRM Registers
3.13.38.1
EVE2_PRM Register Summary
3.13.38.2
EVE2_PRM Register Description
3.13.39
EVE3_PRM Registers
3.13.39.1
EVE3_PRM Register Summary
3.13.39.2
EVE3_PRM Register Description
3.13.40
GPU_PRM Registers
3.13.40.1
GPU_PRM Register Summary
3.13.40.2
GPU_PRM Register Description
3.13.41
INSTR_PRM Registers
3.13.41.1
INSTR_PRM Register Summary
3.13.41.2
INSTR_PRM Register Description
3.13.42
IPU_PRM Registers
3.13.42.1
IPU_PRM Register Summary
3.13.42.2
IPU_PRM Register Description
3.13.43
IVA_PRM Registers
3.13.43.1
IVA_PRM Register Summary
3.13.43.2
IVA_PRM Register Description
3.13.44
L3INIT_PRM Registers
3.13.44.1
L3INIT_PRM Register Summary
3.13.44.2
L3INIT_PRM Register Description
3.13.45
L4PER_PRM Registers
3.13.45.1
L4PER_PRM Register Summary
3.13.45.2
L4PER_PRM Register Description
3.13.46
MPU_PRM Registers
3.13.46.1
MPU_PRM Register Summary
3.13.46.2
MPU_PRM Register Description
3.13.47
OCP_SOCKET_PRM Registers
3.13.47.1
OCP_SOCKET_PRM Register Summary
3.13.47.2
OCP_SOCKET_PRM Register Description
3.13.48
RTC_PRM Registers
3.13.48.1
RTC_PRM Register Summary
3.13.48.2
RTC_PRM Register Description
3.13.49
VPE_PRM Registers
3.13.49.1
VPE_PRM Register Summary
3.13.49.2
VPE_PRM Register Description
3.13.50
WKUPAON_CM Registers
3.13.50.1
WKUPAON_CM Register Summary
3.13.50.2
WKUPAON_CM Register Description
3.13.51
WKUPAON_PRM Registers
3.13.51.1
WKUPAON_PRM Register Summary
3.13.51.2
WKUPAON_PRM Register Description
4
Dual Cortex-A15 MPU Subsystem
4.1
Dual Cortex-A15 MPU Subsystem Overview
4.1.1
Introduction
4.1.2
Features
4.2
Dual Cortex-A15 MPU Subsystem Integration
4.2.1
Clock Distribution
4.2.2
Reset Distribution
4.3
Dual Cortex-A15 MPU Subsystem Functional Description
4.3.1
MPU Subsystem Block Diagram
4.3.2
Cortex-A15 MPCore (MPU_CLUSTER)
4.3.2.1
MPU L2 Cache Memory System
4.3.2.1.1
MPU L2 Cache Architecture
4.3.2.1.2
MPU L2 Cache Controller
4.3.2.1.3
727
4.3.3
MPU_AXI2OCP
4.3.4
Memory Adapter
4.3.4.1
MPU_MA Overview
4.3.4.2
AXI Input Interface
4.3.4.3
Interleaving
4.3.4.3.1
High-Order Fixed Interleaving Model
4.3.4.3.2
Lower 2-GiB Programmable Interleaving Model
4.3.4.3.3
Local Interconnect and Synchronization Agent (LISA) Section Manager
4.3.4.3.4
MA_LSM Registers
4.3.4.3.5
Posted and Nonposted Writes
4.3.4.3.6
Errors
4.3.4.4
Statistics Collector Probe Ports
4.3.4.5
MPU_MA Firewall
4.3.4.6
MPU_MA Power and Reset Management
4.3.4.7
MPU_MA Watchpoint
4.3.4.7.1
Watchpoint Types
4.3.4.7.2
Transaction Filtering Options
4.3.4.7.3
Transaction Match Effects
4.3.4.7.4
Trigger Generation
4.3.4.7.5
Programming Options Summary
4.3.5
Realtime Counter (Master Counter)
4.3.5.1
Counter Operation
4.3.5.2
Frequency Change Procedure
4.3.6
MPU Watchdog Timer
4.3.7
MPU Subsystem Power Management
4.3.7.1
Power Domains
4.3.7.2
Power States of MPU_Cx
4.3.7.3
Power States of MPU Subsystem
4.3.7.4
MPU_WUGEN
4.3.7.5
Power Transition Sequence
4.3.7.6
SR3-APG Technology Fail-Safe Mode
4.3.8
MPU Subsystem AMBA Interface Configuration
4.4
Dual Cortex-A15 MPU Subsystem Register Manual
4.4.1
Dual Cortex-A15 MPU Subsystem Instance Summary
4.4.2
MPU_CS_STM Registers
4.4.3
MPU_INTC Registers
4.4.4
MPU_PRCM_OCP_SOCKET Registers
4.4.4.1
MPU_PRCM_OCP_SOCKET Register Summary
4.4.4.2
MPU_PRCM_OCP_SOCKET Register Description
4.4.5
MPU_PRCM_DEVICE Registers
4.4.5.1
MPU_PRCM_DEVICE Register Summary
4.4.5.2
MPU_PRCM_DEVICE Register Description
4.4.6
MPU_PRCM_PRM_C0 Registers
4.4.6.1
MPU_PRCM_PRM_C0 Register Summary
4.4.6.2
MPU_PRCM_PRM_C0 Register Description
4.4.7
MPU_PRCM_CM_C0 Registers
4.4.7.1
MPU_PRCM_CM_C0 Register Summary
4.4.7.2
MPU_PRCM_CM_C0 Register Description
4.4.8
MPU_PRCM_PRM_C1 Registers
4.4.8.1
MPU_PRCM_PRM_C1 Register Summary
4.4.8.2
MPU_PRCM_PRM_C1 Register Description
4.4.9
MPU_PRCM_CM_C1 Registers
4.4.9.1
MPU_PRCM_CM_C1 Register Summary
4.4.9.2
MPU_PRCM_CM_C1 Register Description
4.4.10
MPU_WUGEN Registers
4.4.10.1
MPU_WUGEN Register Summary
4.4.10.2
MPU_WUGEN Register Description
4.4.11
MPU_WD_TIMER Registers
4.4.11.1
MPU_WD_TIMER Register Summary
4.4.11.2
MPU_WD_TIMER Register Description
4.4.12
MPU_AXI2OCP_MISC Registers
4.4.12.1
MPU_AXI2OCP_MISC Register Summary
4.4.12.2
MPU_AXI2OCP_MISC Register Description
4.4.13
MPU_MA_LSM Registers
4.4.13.1
MPU_MA_LSM Register Summary
4.4.13.2
MPU_MA_LSM Register Description
4.4.14
MPU_MA_WP Registers
4.4.14.1
MPU_MA_WP Register Summary
4.4.14.2
MPU_MA_WP Register Description
5
DSP Subsystems
5.1
DSP Subsystems Overview
5.1.1
DSP Subsystems Key Features
5.2
DSP Subsystem Integration
5.3
DSP Subsystems Functional Description
5.3.1
DSP Subsystems Block Diagram
5.3.2
DSP Subsystem Components
5.3.2.1
C66x DSP Subsystem Introduction
5.3.2.2
DSP TMS320C66x CorePac
5.3.2.2.1
DSP TMS320C66x CorePac CPU
5.3.2.2.2
DSP TMS320C66x CorePac Internal Memory Controllers and Memories
5.3.2.2.2.1
Level 1 Memories
5.3.2.2.2.2
Level 2 Memory
5.3.2.2.3
DSP C66x CorePac Internal Peripherals
5.3.2.2.3.1
DSP C66x CorePac Interrupt Controller (DSP INTC)
5.3.2.2.3.2
DSP C66x CorePac Power-Down Controller (DSP PDC)
5.3.2.2.3.3
DSP C66x CorePac Bandwidth Manager (BWM)
5.3.2.2.3.4
DSP C66x CorePac Memory Protection Hardware
5.3.2.2.3.5
DSP C66x CorePac Internal DMA (IDMA) Controller
5.3.2.2.3.6
DSP C66x CorePac External Memory Controller
5.3.2.2.3.7
DSP C66x CorePac Extended Memory Controller
5.3.2.2.3.7.1
XMC MDMA Accesses at DSP System Level
5.3.2.2.3.7.1.1
DSP System MPAX Logic
5.3.2.2.3.7.1.2
MDMA Non-Post Override Control
5.3.2.2.3.8
L1P Memory Error Detection Logic
5.3.2.2.3.9
L2 Memory Error Detection and Correction Logic
5.3.2.3
DSP Debug and Trace Support
5.3.2.3.1
DSP Advanced Event Triggering (AET)
5.3.2.3.2
DSP Trace Support
5.3.2.3.3
826
5.3.3
DSP System Control Logic
5.3.3.1
DSP System Clocks
5.3.3.2
DSP Hardware Resets
5.3.3.3
DSP Software Resets
5.3.3.4
DSP Power Management
5.3.3.4.1
DSP System Powerdown Protocols
5.3.3.4.2
DSP Software and Hardware Power Down Sequence Overview
5.3.3.4.3
DSP IDLE Wakeup
5.3.3.4.4
DSP SYSTEM IRQWAKEEN registers
5.3.3.4.5
DSP Automatic Power Transition
5.3.4
DSP Interrupt Requests
5.3.4.1
DSP Input Interrupts
5.3.4.1.1
DSP Non-maskable Interrupt Input
5.3.4.2
DSP Event and Interrupt Generation Outputs
5.3.4.2.1
DSP MDMA and DSP EDMA Mflag Event Outputs
5.3.4.2.2
DSP Aggregated Error Interrupt Output
5.3.4.2.3
Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs
5.3.5
DSP DMA Requests
5.3.5.1
DSP EDMA Wakeup Interrupt
5.3.6
DSP Intergated Memory Management Units
5.3.6.1
DSP MMUs Overview
5.3.6.2
Routing MDMA Traffic through DSP MMU0
5.3.6.3
Routing EDMA Traffic thorugh DSP MMU1
5.3.7
DSP Integrated EDMA Subsystem
5.3.7.1
DSP EDMA Overview
5.3.7.2
DSP System and Device Level Settings of DSP EDMA
5.3.8
DSP L2 interconnect Network
5.3.8.1
DSP Public Firewall Settings
5.3.8.2
DSP NoC Flag Mux and Error Log Registers
5.3.8.3
DSP NoC Arbitration
5.3.9
DSP Boot Configuration
5.3.10
DSP Internal and External Memory Views
5.3.10.1
C66x CPU View of the Address Space
5.3.10.2
DSP_EDMA View of the Address Space
5.3.10.3
L3_MAIN View of the DSP Address Space
5.4
DSP Subsystem Register Manual
5.4.1
DSP Subsystem Instance Summary
5.4.2
DSP_ICFG Registers
5.4.2.1
DSP_ICFG Register Summary
5.4.2.2
DSP_ICFG Register Description
5.4.3
DSP_SYSTEM Registers
5.4.3.1
DSP_SYSTEM Register Summary
5.4.3.2
DSP_SYSTEM Register Description
5.4.4
DSP_FW_L2_NOC_CFG Registers
5.4.4.1
DSP_FW_L2_NOC_CFG Register Summary
5.4.4.2
DSP_FW_L2_NOC_CFG Register Description
6
IVA Subsystem
7
Dual Cortex-M4 IPU Subsystem
7.1
Dual Cortex-M4 IPU Subsystem Overview
7.1.1
Introduction
7.1.2
Features
7.2
Dual Cortex-M4 IPU Subsystem Integration
7.2.1
Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
7.2.1.1
Clock Distribution
7.2.1.2
Reset Distribution
7.3
Dual Cortex-M4 IPU Subsystem Functional Description
7.3.1
IPUx Subsystem Block Diagram
7.3.2
Power Management
7.3.2.1
Local Power Management
7.3.2.2
Power Domains
7.3.2.3
887
7.3.2.4
Voltage Domain
7.3.2.5
Power States and Modes
7.3.2.6
Wake-Up Generator (IPUx_WUGEN)
7.3.2.6.1
IPUx_WUGEN Main Features
7.3.3
IPUx_UNICACHE
7.3.4
IPUx_UNICACHE_MMU
7.3.5
IPUx_UNICACHE_SCTM
7.3.5.1
Counter Functions
7.3.5.1.1
Input Events
7.3.5.1.2
Counters
7.3.5.1.2.1
Counting Modes
7.3.5.1.2.2
Counter Overflow
7.3.5.1.2.3
Counters and Processor State
7.3.5.1.2.4
Chaining Counters
7.3.5.1.2.5
Enabling and Disabling Counters
7.3.5.1.2.6
Resetting Counters
7.3.5.2
Timer Functions
7.3.5.2.1
Periodic Intervals
7.3.5.2.2
Event Generation
7.3.6
IPUx_MMU
7.3.6.1
IPUx_MMU Behavior on Page-Fault in IPUx Subsystem
7.3.7
Interprocessor Communication (IPC)
7.3.7.1
Use of WFE and SEV
7.3.7.2
Use of Interrupt for IPC
7.3.7.3
Use of the Bit-Band Feature for Semaphore Operations
7.3.7.4
Private Memory Space
7.3.8
IPU Boot Options
7.4
Dual Cortex-M4 IPU Subsystem Register Manual
7.4.1
IPUx Subsystem Instance Summary
7.4.2
IPUx_UNICACHE_CFG Registers
7.4.2.1
IPUx_UNICACHE_CFG Register Summary
7.4.2.2
IPUx_UNICACHE_CFG Register Description
7.4.3
IPUx_UNICACHE_SCTM Registers
7.4.3.1
IPUx_UNICACHE_SCTM Register Summary
7.4.3.2
IPUx_UNICACHE_SCTM Register Description
7.4.4
IPUx_UNICACHE_MMU (AMMU) Registers
7.4.4.1
IPUx_UNICACHE_MMU (AMMU) Register Summary
7.4.4.2
IPUx_UNICACHE_MMU (AMMU) Register Description
7.4.5
IPUx_MMU Registers
7.4.6
IPUx_Cx_INTC Registers
7.4.7
IPUx_WUGEN Registers
7.4.7.1
IPUx_WUGEN Register Summary
7.4.7.2
IPUx_WUGEN Register Description
7.4.8
IPUx_Cx_RW_TABLE Registers
7.4.8.1
IPUx_Cx_RW_TABLE Register Summary
7.4.8.2
IPUx_Cx_RW_TABLE Register Description
8
Embedded Vision Engine
8.1
Embedded Vision Engine (EVE) Subsystem
8.1.1
EVE Overview
8.1.1.1
EVE Memories
8.1.2
EVE Integration
8.1.2.1
Multi-EVE Recommended Connections
8.1.3
EVE Functional Description
8.1.3.1
EVE Connection ID (ConnID) Mapping
8.1.3.2
EVE Processors Overview
8.1.3.2.1
Scalar Core (ARP32)
8.1.3.2.2
VCOP
8.1.3.2.3
Scalar-Vector Interaction
8.1.3.3
Internal Memory Overview
8.1.3.3.1
Program Cache/Memory
8.1.3.3.2
ARP32 Data Memory (DMEM)
8.1.3.3.3
WBUF
8.1.3.3.4
Image Buffers–IBUFLA, IBUFLB, IBUFHA, and IBUFHB
8.1.3.3.5
Memory Switch Error Registers
8.1.3.3.6
Memory Error Detection
8.1.3.3.6.1
Captured Address – EDADDR and EDADDR_BO
8.1.3.3.6.2
Modes of Operation
8.1.3.3.6.3
Parity Error Testability
8.1.3.3.6.4
Parity Error Recovery
8.1.3.3.7
VCOP System Error Halt Conditions
8.1.3.4
Program Cache Architecture
8.1.3.4.1
Basic Operation
8.1.3.4.2
Line Buffer
8.1.3.4.3
Software Direct Preload
8.1.3.4.4
User Coherence Operation
8.1.3.4.4.1
Global Invalidate
8.1.3.4.4.2
Range-Based Invalidate
8.1.3.4.4.3
Single-Address Invalidate – For Breakpoint Operation
8.1.3.4.5
Demand-Based Prefetch
8.1.3.4.6
Debug Support
8.1.3.4.6.1
Read/Write Accessibility through OCP Debug Target Port
8.1.3.4.6.2
Breakpoint Support
8.1.3.4.6.3
Cache Profiling
8.1.3.4.7
Error Detection
8.1.3.5
EDMA
8.1.3.5.1
DMA Channel Events
8.1.3.5.2
DMA Parameter Set
8.1.3.5.3
Channel Controller
8.1.3.5.4
EVE-Level Bus Width and Throughput
8.1.3.5.4.1
Concurrent Transfer Requirements
8.1.3.6
General-Purpose Inputs/Outputs
8.1.3.7
CME Signaling
8.1.3.8
Multi-EVE and VIP Usage Models
8.1.3.8.1
Data Partitioning
8.1.3.8.2
Task Partitioning
8.1.3.8.3
983
8.1.3.9
Memory Management Unit
8.1.3.10
Interrupt Control
8.1.3.10.1
EVE Interrupt Sources – Memory Switch and Parity Error Interrupts
8.1.3.10.2
ARP32 INTC
8.1.3.10.3
Output Interrupt Reduction
8.1.3.10.4
End of Interrupt Mapping
8.1.3.11
Interprocessor Communication
8.1.3.11.1
Mailbox Configuration
8.1.3.11.1.1
Mailbox 0 – EVE to DSP1, DSP2 and MPU
8.1.3.11.1.2
Mailbox 1 – EVE to Other Hosts
8.1.3.11.1.3
Mailbox 2 – EVE to EVE in a 2x EVE System
8.1.3.12
Powerdown
8.1.3.12.1
Extended Duration Sleep
8.1.3.12.1.1
Sequence Overview
8.1.3.12.1.2
Idle Protocol Overview
8.1.3.12.1.3
Mstandby Protocol Overview
8.1.3.12.1.4
IDLE Wakeup
8.1.3.13
Hardware-Assisted Software Self-Test – MISRs
8.1.3.13.1
Mapping of MISRs to Different Width Buses
8.1.3.13.2
Detection of Valid Address and Data Cycles
8.1.3.13.3
Creating a Unique Signature – Software Self-Test Implications
8.1.3.13.4
Multipass Tests Using WBUF MISR
8.1.3.14
Error Recovery – ARP32 and OCP Disconnect
8.1.3.14.1
ARP32 Disconnect
8.1.3.14.2
OCP Initiator Disconnect
8.1.3.15
Lock and Unlock Feature
8.1.3.16
EVE Memory Map
8.1.3.16.1
VCOP and Local EDMA: IBUF Memory Map Aliasing
8.1.3.16.2
ARP32 Write Model – Avoiding Race Conditions
8.1.3.17
Debug Support
8.1.3.17.1
ARP32 Debug Support
8.1.3.17.2
SCTM
8.1.3.17.2.1
SCTM Configuration
8.1.3.17.2.2
SCTM Resources Reserved for BIOS
8.1.3.17.2.3
SCTM Event Mapping
8.1.3.17.2.4
SCTM Halt and Idle Modes
8.1.3.17.3
SMSET
8.1.3.17.3.1
SMSET Configuration
8.1.3.17.3.2
SMSET Event Mapping
8.1.3.18
EVE L2_FNOC Interconnect
8.1.3.18.1
EVE L2_FNOC Flag Mux and Error Log Registers
8.1.4
EVE Programming Model
8.1.4.1
Boot
8.1.4.2
Task Change and Program Cache Prefetch
8.1.4.2.1
Simple or Unoptimized Branch to New Task
8.1.4.2.2
Prefetch, Wait, then Branch to New Task
8.1.4.2.3
Hidden Prefetch
8.1.4.3
Interrupts
8.1.4.4
Safety Considerations
8.1.4.4.1
Memory Error Detection
8.1.4.4.2
MMU
8.1.4.4.3
Firewall
8.1.4.4.4
Interconnect
8.1.4.4.5
Application Stability/Sequencing
8.1.4.4.6
Interrupt Servicing
8.1.5
EVE Subsystem Register Manual
8.1.5.1
EVE Instance Summary
8.1.5.2
EVE Register Summary and Description
8.1.5.2.1
EVE Register Summary
8.1.5.2.2
EVE Register Description
8.1.5.3
EVE L2_FNOC Register Summary and Description
8.1.5.3.1
EVE L2_FNOC Register Summary
8.1.5.3.2
EVE L2_FNOC Register Description
8.1.6
Subsystem Counter Timer Module
8.1.6.1
Introduction
8.1.6.1.1
Overview
8.1.6.1.2
Top-Level Requirements
8.1.6.1.3
Configuration
8.1.6.1.4
Block Diagram
8.1.6.2
Functional Description
8.1.6.2.1
Configuration Interface
8.1.6.2.2
Counter Function
8.1.6.2.2.1
Input Events
8.1.6.2.2.2
Counters
8.1.6.2.2.3
Counting Mode
8.1.6.2.2.4
Counter Overflow
8.1.6.2.2.5
Counters and Processor State
8.1.6.2.2.6
Chaining Counters
8.1.6.2.2.6.1
Reading Chained Counters
8.1.6.2.2.7
Enabling and Disabling Counters
8.1.6.2.2.8
Resetting Counters
8.1.6.2.3
Timer Function
8.1.6.2.3.1
Periodic Intervals
8.1.6.2.3.2
Event Generation
8.1.6.2.3.3
Watchdog Timer Function
8.1.6.2.4
System Trace Integration
8.1.6.2.4.1
Overview
8.1.6.2.4.2
STM Configuration
8.1.6.2.4.2.1
Periodic Counter State Export
8.1.6.2.4.2.2
Application Control of Counter State Export
8.1.6.2.4.2.3
Application Control of the Counter Configuration Export
8.1.6.3
Use Case Examples
8.1.6.3.1
Counter Enable
8.1.6.3.1.1
Enabling a Single Counter
8.1.6.3.1.2
Reading a Single Counter
8.1.6.3.1.3
Enabling a Group of Counters Simultaneously
8.1.6.3.1.4
Reading a Group of Counters Simultaneously
8.1.6.3.1.5
Configuring a Chained Counter
8.1.6.3.2
Timer Enable
8.1.6.3.3
Periodic STM Export Enable
8.1.6.3.4
Disabling the SCTM
8.1.6.4
SCTM Register Manual
8.1.6.4.1
SCTM Instance Summary
8.1.6.4.2
SCTM Registers
8.1.6.4.2.1
SCTM Register Summary
8.1.6.4.2.2
SCTM Register Description
8.1.7
Software Message and System Event Trace
8.1.7.1
Introduction
8.1.7.1.1
Overview
8.1.7.1.2
Configuration
8.1.7.1.3
Block Diagram
8.1.7.2
Functional Description
8.1.7.2.1
Connectivity
8.1.7.2.2
SMSET Event Mapping
8.1.7.2.3
Software Messages
8.1.7.2.4
SMSET Master Port
8.1.7.2.4.1
OCP Disconnect
8.1.7.2.5
SMSET Debug Features
8.1.7.2.6
Component Ownership
8.1.7.2.6.1
Ownership State
8.1.7.2.6.1.1
Available State
8.1.7.2.6.1.2
Claimed State
8.1.7.2.6.1.3
Enabled State
8.1.7.2.6.2
Ownership Commands
8.1.7.2.6.3
Claim Reset
8.1.7.3
Use Case Examples
8.1.7.3.1
Procedure to Enable System Event Capture
8.1.7.3.2
Procedure to Start and Stop System Event Capture from External Trigger Detection
8.1.7.3.3
Procedure to Disable System Event Capture
8.1.7.4
SMSET Register Manual
8.1.7.4.1
SMSET Instance Summary
8.1.7.4.2
SMSET Register Summary
8.1.7.4.3
SMSET Register Description
8.2
ARP32 CPU and Instruction Set
8.2.1
Overview
8.2.2
Features
8.2.3
Block Diagram
8.2.4
Architecture
8.2.4.1
Interface Description
8.2.4.1.1
Data Memory Interface
8.2.4.1.2
Instruction Memory Interface
8.2.4.2
Pipeline
8.2.4.2.1
Overview
8.2.4.2.2
Pipeline Operation
8.2.4.2.2.1
ARP32 CPU Pipeline Operation
8.2.4.2.2.2
1129
8.2.4.2.3
Pipeline Interlocks
8.2.4.3
Data Format
8.2.4.4
Endian Support
8.2.4.5
Architectural Register File
8.2.4.6
CPU Control Registers
8.2.4.6.1
Control Status Register (CSR)
8.2.4.6.2
Interrupt Enable Register (IER)
8.2.4.6.3
Interrupt Flag Register (IFR)
8.2.4.6.4
Interrupt Set Register (ISR)
8.2.4.6.5
Interrupt Clear Register (ICR)
8.2.4.6.6
Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
8.2.4.6.7
Interrupt Return Pointer Register (IRP)
8.2.4.6.8
Stack Pointer Register (SP)
8.2.4.6.9
Global Data Pointer Register (GDP)
8.2.4.6.10
Link Register (LR)
8.2.4.6.11
Loop 0 Start Address Register (LSA0)
8.2.4.6.12
Loop 0 End Address Register (LEA0)
8.2.4.6.13
Loop 0 Iteration Count Register (LCNT0)
8.2.4.6.14
Loop 1 Start Address Register (LSA1)
8.2.4.6.15
Loop 1 End Address Register (LEA1)
8.2.4.6.16
Loop 1 Iteration Count Register (LCNT1)
8.2.4.6.17
Loop 0 Iteration Count Reload Value Register (LCNT0RLD)
8.2.4.6.18
Shadow Control Status Register (SCSR)
8.2.4.6.19
NMI Shadow Control Status Register (NMISCSR)
8.2.4.6.20
CPU Identification Register (CPUID)
8.2.4.6.21
Decode Program Counter Register (DPC)
8.2.4.6.22
Time Stamp Counter Registers (TSCL and TSCH)
8.2.4.6.22.1
Initialization
8.2.4.6.22.2
Enabling Counting
8.2.4.6.22.3
Disabling Counting
8.2.4.6.22.4
Reading the Counter
8.2.4.7
CPU Shadow Registers
8.2.4.8
Functional Units
8.2.4.9
Instruction Fetch
8.2.4.10
Alignment of 32-bit Instructions
8.2.4.11
Instruction Execution in Branch Delay Slot
8.2.4.12
Address Space
8.2.4.13
Program Counter Convention
8.2.4.14
Stack Pointer Convention
8.2.4.15
Global Data Pointer Convention
8.2.4.16
Conditional Execution
8.2.4.17
Hardware Loop Acceleration
8.2.4.17.1
Overview
8.2.4.17.2
Loop Registers
8.2.4.17.3
Loop Setup Instructions
8.2.4.17.4
Loop Operation
8.2.4.17.5
Call and Branch within Loop Context
8.2.4.17.6
Dynamic Changes to Loop Iteration Count
8.2.4.17.7
Interrupt Processing During HLA
8.2.4.17.8
HLA Usage in Interrupt Context
8.2.4.17.9
HLA Usage Restrictions
8.2.4.17.10
HLA Mapping Examples
8.2.4.17.10.1
Loops With Single Level of Nesting
8.2.4.17.10.1.1
C memset-like Loop, Single Level, Minimum Instructions
8.2.4.17.10.1.2
1184
8.2.4.17.10.1.3
C memcpy-like Loop, Single Level, Minimum Instructions
8.2.4.17.10.1.4
1186
8.2.4.17.10.2
Loops With Two Levels of Nesting
8.2.4.17.10.2.1
Two-level Nesting, Both Loops Ending at Same Instruction
8.2.4.17.10.2.2
1189
8.2.4.17.10.2.3
Two-level Nesting, Different Ending Instructions for Two Levels
8.2.4.17.10.2.4
1191
8.2.4.18
Interrupts
8.2.4.18.1
Overview
8.2.4.18.2
Interrupt Processing
8.2.4.18.3
Interrupt Acknowledgment
8.2.4.18.4
Interrupt Priorities
8.2.4.18.5
Interrupt Service Table (IST)
8.2.4.18.6
Interrupt Flags
8.2.4.18.6.1
Setting Interrupt Flag
8.2.4.18.6.2
Setting Interrupt Flag
8.2.4.18.6.3
1201
8.2.4.18.7
Interrupt Behavior
8.2.4.18.7.1
Reset Interrupt
8.2.4.18.7.2
Non-maskable Interrupt (NMI)
8.2.4.18.7.3
SWI Interrupt
8.2.4.18.7.4
Maskable Interrupts
8.2.4.18.7.5
UNDEF Interrupt
8.2.4.18.8
Interrupt Context Save and Restore
8.2.4.18.9
Nested Interrupts
8.2.4.18.9.1
Non-nested Interrupt Model
8.2.4.18.9.2
Nested Interrupt Model
8.2.4.18.10
Non-nested Interrupt Latency
8.2.4.18.10.1
Best Case Interrupt Latency
8.2.4.18.10.2
Worst Case Interrupt Latency
8.2.A Instruction Set
8.2.A.1 Instruction Operation and Execution Notations
8.2.A.2 Instruction Syntax and Opcode Notations
8.2.A.3 Instruction Scheduling Restrictions
8.2.A.3.1 Restrictions Applicable to a Branch Delay Slot
8.2.A.3.2 Restrictions on Loops Using Hardware Loop Assist (HLA)
8.2.A.3.3 Restrictions on Other Types of Control Flow Instructions
8.2.A.3.4 Restrictions for Write Data Bypass to Control Register Reads
8.2.A.3.5 Restrictions for Write Data Bypass to Shadow Register Reads
8.2.A.3.6 Restrictions for Link Register Update
8.2.A.4 Instruction Set Encoding
8.2.A.5 Instruction Descriptions
ABS
ADD
ADD
ADD
ADD
ADD
AND
AND
B(cc)
B(cc)
B(cc)
BIRP
BKPT
BNRP
CALL
CALL
CLR
CLR
CMP
CMP
CMP
CMPU
CMPU
CMPU
DIV
DIVU
EXT
EXT
EXTU
EXTU
IDLE
LDB(U)
LDB(U)
LDB(U)
LDB(U)
LDB(U)
LDB(U)
LDB(U)
LDB(U)
LDH(U)
LDH(U)
LDH(U)
LDH(U)
LDH(U)
LDH(U)
LDH(U)
LDH(U)
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDW
LDRF
LMBD
MAX
MAXU
MIN
MINU
MOD
MODU
MPY
MPYU
MV
MVC
MVC
MVC
MVCH
MVK
MVKH
MVKLS
MVKS
MVS
MVS
NEG
NOP
NOT
OR
OR
RET
REV
ROT
ROTC
SADD
SATN
SET
SET
SHL
SHL
SHRA
SHRA
SHRU
SHRU
SLA
SSUB
STB
STB
STB
STB
STB
STB
STB
STB
STH
STH
STH
STH
STH
STH
STH
STH
STW
STW
STW
STW
STW
STW
STW
STW
STHI
STRF
SUB
SUB
SUB
SUB
SUB
SWI
XOR
XOR
8.2.B Clock, Reset, and Dynamic Power Management
8.2.B.1 Introduction
8.2.B.2 CPU Reset Modes
8.2.B.3 Dynamic Power Management
8.2.C Notes on Programming Model
8.2.C.1 Booting
8.2.C.2 Enabling and Disabling Interrupts
8.2.C.2.1 Globally Enabling or Disabling Maskable Interrupts
8.2.C.2.2 Enabling or Disabling Individual Interrupts
8.2.C.3 Stack Usage in Interrupt Service Routine
8.2.C.4 General Restrictions
8.3
VCOP CPU and Instruction Set
8.3.1
Module Overview
8.3.2
Features
8.3.3
Block Diagram
8.3.4
System Interfaces
8.3.4.1
Interrupts
8.3.4.2
Configuration Bus Slave Port
8.3.4.3
Performance Counter Interface
8.3.4.4
Data Memory Map
8.3.5
Functional Description
8.3.5.1
Scalar-Vector Architecture
8.3.5.1.1
Scalar Core
8.3.5.1.2
Scalar-Vector Interaction
8.3.5.2
Vector Core Overview
8.3.5.2.1
Nested for Loop Model
8.3.5.2.1.1
Nested Loop Model Skeleton
8.3.5.2.1.2
1385
8.3.5.2.2
Instruction Organization
8.3.5.3
Vector Control
8.3.5.3.1
Repeat End Count
8.3.5.3.2
Parameter Pointer
8.3.5.3.3
Switch Buffers
8.3.5.4
Vector-Scalar Synchronization
8.3.5.4.1
Wait for Vector Core Done
8.3.5.4.2
Wait for Vector Core Ready
8.3.5.5
Vector Computation
8.3.5.5.1
Vector Loop
8.3.5.5.1.1
Retention of State Between VLOOPs
8.3.5.5.2
Vector Register Initialization
8.3.5.5.3
Address Generator (agen)
8.3.5.5.4
Vector Load
8.3.5.5.5
Vector Arithmetic/Logic Operations
8.3.5.5.6
Vector Store
8.3.5.5.7
Table Lookup Operation
8.3.5.5.8
Histogram Operation
8.3.5.5.9
Circular Buffer Addressing Support
8.3.5.5.10
Load/Store Address Alignment Constraints
8.3.5.6
Load/Store Buffer and Scheduling
8.3.5.6.1
3-Tap Horizontal Filtering, Byte Type
8.3.5.6.2
1408
8.3.5.6.3
Horizontal Filtering, Short Type
8.3.5.6.4
1410
8.3.5.7
VCOP Per-Loop Overhead
8.3.5.8
VCOP Error Handling
8.3.5.9
Vector Operation Details
8.3.5.9.1
VABS
8.3.5.9.2
VABSDIF
8.3.5.9.3
VADD
8.3.5.9.4
VADDH
8.3.5.9.5
VADDSUB
8.3.5.9.6
VADD3
8.3.5.9.7
VADIF3
8.3.5.9.8
VAND
8.3.5.9.9
VANDN
8.3.5.9.10
VAND3
8.3.5.9.11
VBINLOG
8.3.5.9.12
VBITC
8.3.5.9.13
VBITDI
8.3.5.9.14
VBITI
8.3.5.9.15
VBITPK
8.3.5.9.16
VBITR
8.3.5.9.17
VBITTR
8.3.5.9.18
VBITUNPK
8.3.5.9.19
VCMOV
8.3.5.9.20
VCMPEQ
8.3.5.9.21
VCMPGE
8.3.5.9.22
VCMPGT
8.3.5.9.23
VDINTRLV
8.3.5.9.24
VDINTRLV2
8.3.5.9.25
VEXITNZ
8.3.5.9.26
VINTRLV
8.3.5.9.27
VINTRLV2
8.3.5.9.28
VINTRLV4
8.3.5.9.29
VLMBD
8.3.5.9.30
VMADD
8.3.5.9.31
VMAX
8.3.5.9.32
VMAXSETF
8.3.5.9.33
VMIN
8.3.5.9.34
VMINSETF
8.3.5.9.35
VMPY
8.3.5.9.36
VMSUB
8.3.5.9.37
VNOP
8.3.5.9.38
VNOT
8.3.5.9.39
VOR
8.3.5.9.40
VOR3
8.3.5.9.41
VRND
8.3.5.9.42
VSAD
8.3.5.9.43
VSEL
8.3.5.9.44
VSHF
8.3.5.9.45
VSHFOR
8.3.5.9.46
VSHF16
8.3.5.9.47
VSIGN
8.3.5.9.48
VSORT2
8.3.5.9.49
VSUB
8.3.5.9.50
VSWAP
8.3.5.9.51
VXOR
8.3.6
Debug Support
8.3.7
VCOP Register Manual
8.3.7.1
VCOP Instance Summary
8.3.7.2
VCOP Registers
8.3.7.2.1
VCOP Registers Mapping Summary
8.3.7.2.2
VCOP Register Description
9
Imaging Subsystem
9.1
ISS Overview
9.1.1
ISS Integration
9.1.1.1
ISS PRCM Interface Integration
9.1.1.1.1
ISS Clock Domains
9.1.2
ISS Functional Description
9.1.2.1
ISS Interrupts
9.1.2.1.1
ISS Interrupt Merger
9.1.2.1.2
ISS Submodule Interrupts
9.1.2.1.2.1
ISS ISP Interrupts
9.1.2.1.2.2
ISS CAL_B Interrupts
9.1.2.1.2.3
ISS SIMCOP Interrupts
9.1.2.2
ISS Interconnect
9.1.2.3
ISS Video Mux
9.1.2.4
ISS Clocks
9.1.2.5
ISS Reset
9.1.2.6
ISS Power Management
9.1.2.6.1
ISS Power-Management Infrastructure Overview
9.1.2.6.2
ISS STANDBY Mechanism
9.1.2.6.3
ISS IDLE Mechanism
9.1.2.7
ISS CAL Usage Considerations
9.1.2.7.1
CAL Usage as Memory to Memory Pixel DMA
9.1.2.7.2
CAL Usage with GLBCE
9.1.3
ISS Register Manual
9.1.3.1
ISS Instance Summary
9.1.3.2
ISS Registers
9.1.3.2.1
ISS TOP Register Summary
9.1.3.2.2
ISS TOP Register Description
9.2
ISS Camera Adapter Layer (CAL)
9.2.1
ISS CAL Features
9.2.2
ISS CAL Integration
9.2.2.1
CAL Main Integration Attributes
9.2.2.2
CAL Integration - Video Port
9.2.2.3
CAL Integration - BYS Ports
9.2.3
ISS CAL Functional Description
9.2.3.1
CAL Block Diagram
9.2.3.2
CAL Hardware and Software Reset
9.2.3.3
CAL Clock Configuration
9.2.3.4
CAL Power Management
9.2.3.5
CAL Interrupt Events
9.2.3.6
CAL Data Stream
9.2.3.7
CAL Pixel Extraction
9.2.3.8
CAL DPCM Decoding and Encoding
9.2.3.8.1
CAL Partial DPCM Decompression
9.2.3.9
CAL Pixel Packing
9.2.3.10
CAL Write DMA
9.2.3.10.1
CAL Write DMA Overview
9.2.3.10.2
CAL Write DMA Data Cropping
9.2.3.10.3
CAL Write DMA Buffer Management
9.2.3.10.4
CAL Write DMA OCP Address Generation
9.2.3.10.4.1
Write DMA Buffer Base Address
9.2.3.10.4.2
Write DMA Line Start Address
9.2.3.10.4.3
Write DMA Data Address
9.2.3.10.5
CAL Write DMA OCP Transaction Generation
9.2.3.10.6
CAL Write DMA Real Time Traffic
9.2.3.11
CAL Read DMA
9.2.3.11.1
CAL Read DMA Overview
9.2.3.11.2
CAL Read DMA Data Provided to Processing Pipeline
9.2.3.11.3
CAL Read DMA Skipping Modes
9.2.3.11.4
CAL Read DMA YUV420 Support
9.2.3.11.5
CAL Read DMA OCP Request Generation
9.2.3.12
CAL Video Port
9.2.3.12.1
CAL Video Port Overview
9.2.3.12.2
CAL Video Port Pixel Clock Generation
9.2.3.12.3
CAL Video Port Video Timing Generator
9.2.3.13
CAL BYS Ports
9.2.3.13.1
CAL BYS Ports Overview
9.2.3.13.2
CAL BYS Output Port
9.2.3.13.3
BYS Input Port
9.2.3.14
CAL Registers Shadowing
9.2.4
ISS CAL Register Manual
9.2.4.1
CAL Instance Summary
9.2.4.2
CAL Registers
9.2.4.2.1
CAL Register Summary
9.2.4.2.2
CAL Register Description
9.3
ISS Image Signal Processor (ISP)
9.3.1
ISS ISP Overview
9.3.1.1
ISS ISP Features
9.3.1.2
ISS ISP Block Diagram
9.3.2
ISS ISP Integration
9.3.2.1
ISS ISP PRCM Interface
9.3.2.1.1
ISS ISP Clocks
9.3.2.1.2
ISS ISP Reset
9.3.2.2
ISS ISP Interrupt Tree
9.3.2.3
ISS ISP IPIPEIF Integration
9.3.2.3.1
ISS ISP IPIPEIF Interrupts
9.3.2.4
ISS ISP IPIPE Integration
9.3.2.4.1
ISS ISP IPIPE Interrupts
9.3.2.5
ISS ISP RSZ Integration
9.3.2.5.1
ISS ISP RSZ PRCM Interface
9.3.2.5.1.1
ISS ISP RSZ Reset
9.3.2.5.2
ISS ISP RSZ Interrupts
9.3.2.6
ISS ISP H3A Integration
9.3.2.6.1
ISS ISP H3A Interrupts
9.3.2.7
ISS ISP ISIF Integration
9.3.2.7.1
ISS ISP ISIF Interrupts
9.3.2.8
ISS ISP BL Integration
9.3.3
ISS ISP Functional Description
9.3.3.1
ISS ISP VP Functional Description
9.3.3.1.1
ISS ISP VP Overview
9.3.3.1.2
ISS ISP VP Data Formats
9.3.3.1.3
ISS ISP VP Top-Level Communication With CAL_B
9.3.3.1.4
ISS ISP VP Pixel Clock Inversion
9.3.3.2
ISS ISP GLBCE Functional Description
9.3.3.2.1
ISS ISP GLBCE Overview
9.3.3.2.2
ISS ISP GLBCE Interface
9.3.3.2.3
ISS ISP GLBCE Core
9.3.3.2.3.1
ISS ISP GLBCE Core Key Parameters
9.3.3.2.3.2
ISS ISP GLBCE Iridix Strength Calculation
9.3.3.2.3.3
ISS ISP GLBCE Iridix Configuration Registers
9.3.3.2.3.3.1
ISS ISP GLBCE Iridix Frame Width
9.3.3.2.3.3.2
ISS ISP GLBCE Iridix Frame Height
9.3.3.2.3.3.3
ISS ISP GLBCE Iridix Control
9.3.3.2.3.3.4
ISS ISP GLBCE Iridix Control
9.3.3.2.3.3.5
ISS ISP GLBCE Iridix Strength
9.3.3.2.3.3.6
ISS ISP GLBCE Iridix Variance
9.3.3.2.3.3.7
ISS ISP GLBCE Iridix Dither
9.3.3.2.3.3.8
ISS ISP GLBCE Iridix Amplification Limit
9.3.3.2.3.3.9
ISS ISP GLBCE Iridix Slope Min and Max
9.3.3.2.3.3.10
ISS ISP GLBCE Iridix Black Level
9.3.3.2.3.3.11
ISS ISP GLBCE Iridix White Level
9.3.3.2.3.3.12
ISS ISP GLBCE Iridix Asymmetry Function Look-up-table
9.3.3.2.3.3.13
ISS ISP GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
9.3.3.2.3.3.14
ISS ISP GLBCE Iridix Tile Position and Size
9.3.3.2.3.3.15
ISS ISP GLBCE Iridix WDR Look-up-table
9.3.3.2.4
ISS ISP GLBCE Embedded Memory
9.3.3.2.5
ISS ISP GLBCE Programming Model
9.3.3.2.5.1
ISS ISP GLBCE Restriction
9.3.3.2.5.1.1
ISS ISP GLBCE Recovery from Reset
9.3.3.2.5.1.2
General description of GLBCE processing
9.3.3.2.5.1.3
Continuous Frame Processing
9.3.3.2.5.1.4
Single Image Processing
9.3.3.3
ISS ISP NSF3V Functional Description
9.3.3.3.1
ISS ISP NSF3V Overview
9.3.3.3.2
ISS ISP NSF3V Register Shadowing
9.3.3.3.3
ISS ISP NSF3V Programming Model
9.3.3.3.3.1
ISS ISP NSF3V Initialization
9.3.3.4
ISS ISP IPIPEIF Functional Description
9.3.3.4.1
ISS ISP IPIPEIF Overview
9.3.3.4.2
ISS ISP IPIPEIF Top-Level Block Diagram
9.3.3.4.3
ISS ISP IPIPEIF Input Interface
9.3.3.4.3.1
ISS ISP IPIPEIF Input From VP
9.3.3.4.3.2
ISS ISP IPIPEIF Input From BL
9.3.3.4.3.2.1
ISS ISP IPIPEIF Double-Buffer Input Function When Reading From BL
9.3.3.4.4
ISS ISP IPIPEIF Data Path Selection
9.3.3.4.4.1
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0
9.3.3.4.4.2
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 1
9.3.3.4.4.3
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 2
9.3.3.4.4.4
ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 3
9.3.3.4.4.5
ISS ISP IPIPEIF INPSRC1 = 1 and INPSRC2 = 0
9.3.3.4.4.6
ISS ISP IPIPEIF INPSRC1 = 2 and INPSRC2 = 0
9.3.3.4.4.7
ISS ISP IPIPEIF INPSRC1 = 3 and INPSRC2 = 0
9.3.3.4.5
ISS ISP IPIPEIF Timing Generation
9.3.3.4.5.1
ISS ISP IPIPEIF Fractional Clock Divider
9.3.3.4.6
ISS ISP IPIPEIF Decompression (DPCM) Subblock: Unpack and Decompression Function
9.3.3.4.7
ISS ISP IPIPEIF Dark-Frame Subtraction Functionality
9.3.3.4.7.1
ISS ISP IPIPEIF Defect Pixel Correction
9.3.3.4.7.2
ISS ISP IPIPEIF DFS Subtraction Direction
9.3.3.4.8
ISS ISP IPIPEIF Wide Dynamic Range WDR Merging Functionality
9.3.3.4.8.1
ISS ISP IPIPEIF merging general description
9.3.3.4.9
ISS ISP IPIPEIF (1, 2, 1) Averaging Filter for IPIPE Data Path
9.3.3.4.10
ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for IPIPE Data Path
9.3.3.4.11
ISS ISP IPIPEIF RAW Data Gain for IPIPE Data Path
9.3.3.4.12
ISS ISP IPIPEIF (1, 2 ,1) Averaging Filter for H3A Data Path
9.3.3.4.13
ISS ISP IPIPEIF Horizontal Pixel Decimator (Downsizer) for H3A Data Path
9.3.3.4.14
ISS ISP IPIPEIF YUV4:2:2 8-bit Packed Data Input Coming From ISIF Module
9.3.3.4.15
ISS ISP IPIPEIF YUV4:2:0 Data Input for Memory-to-Memory Resize Operations
9.3.3.4.16
ISS ISP IPIPEIF Module Events and Status Checking
9.3.3.5
ISS ISP IPIPE Functional Description
9.3.3.5.1
ISS ISP IPIPE Overview
9.3.3.5.2
ISS ISP IPIPE Top-Level Block Diagram
9.3.3.5.3
ISS ISP IPIPE Input Interface
9.3.3.5.4
ISS ISP IPIPE Defect Pixel Correction
9.3.3.5.4.1
ISS ISP IPIPE LUT Defect Pixel Correction (LUT DPC)
9.3.3.5.5
ISS ISP IPIPE DPC Interface
9.3.3.5.6
ISS ISP IPIPE White Balance
9.3.3.5.7
ISS ISP IPIPE YUV422to444
9.3.3.5.8
ISS ISP IPIPE RGB2RGB Blending Module
9.3.3.5.9
ISS ISP IPIPE Gamma Correction Module
9.3.3.5.10
ISS ISP IPIPE Second RGB2RGB Conversion Matrix
9.3.3.5.11
ISS ISP IPIPE RGB2YCbCr Conversion Matrix
9.3.3.5.12
ISS ISP IPIPE 4:2:2 Conversion Module
9.3.3.5.13
ISS ISP IPIPE 2D Edge-Enhancer
9.3.3.5.14
ISS ISP IPIPE Histogram
9.3.3.5.15
ISS ISP IPIPE Boxcar
9.3.3.6
ISS ISP RSZ Functional Description
9.3.3.6.1
ISS ISP RSZ Overview
9.3.3.6.2
ISS ISP RSZ Top-Level Block Diagram
9.3.3.6.3
ISS ISP RSZ Interfaces
9.3.3.6.3.1
ISS ISP RSZ VBUSP Interface
9.3.3.6.3.2
ISS ISP RSZ Video Port Interfaces
9.3.3.6.3.3
ISS ISP RSZ MTC Interfaces
9.3.3.6.3.4
ISS ISP RSZ CNF Interface
9.3.3.6.4
ISS ISP RSZ ICM Handshake Signals
9.3.3.6.5
ISS ISP RSZ Integration
9.3.3.6.6
ISS ISP RSZ Functional Description
9.3.3.6.6.1
ISS ISP RSZ Operating Modes
9.3.3.6.6.1.1
ISS ISP RSZ Operating Modes and Maximum Input Clock
9.3.3.6.6.2
ISS ISP RSZ Input Data Cropper
9.3.3.6.6.3
ISS ISP RSZ Averager
9.3.3.6.6.3.1
ISS ISP RSZ Use Cases
9.3.3.6.6.3.2
ISS ISP RSZ Memory Use
9.3.3.6.6.3.3
ISS ISP RSZ Border Conditions
9.3.3.6.6.4
ISS ISP RSZ Interpolation
9.3.3.6.6.4.1
ISS ISP RSZ Liner Interpolation Input Data
9.3.3.6.6.4.1.1
ISS ISP RSZ Cubic Convolution Mode
9.3.3.6.6.4.1.2
ISS ISP RSZ Phase Settings
9.3.3.6.6.5
ISS ISP RSZ Data Saturator
9.3.3.6.6.6
ISS ISP RSZ Color Converter
9.3.3.6.6.7
ISS ISP RSZ Output Interface
9.3.3.6.6.7.1
ISS ISP RSZ Circular Buffer
9.3.3.7
ISS ISP CNF Functional Description
9.3.3.7.1
ISS ISP CNF Overview
9.3.3.7.2
ISS ISP CNF Top Level Block Diagram
9.3.3.7.3
ISS ISP CNF Noise Filter Algorithm
9.3.3.7.4
ISS ISP CNF Chroma Downsampling and Upsampling
9.3.3.7.5
ISS ISP CNF Vertical and Horizontal Blanking
9.3.3.7.6
ISS ISP CNF configuring ranges/restrictions
9.3.3.8
ISS ISP H3A Functional Description
9.3.3.8.1
ISS ISP H3A Overview
9.3.3.8.2
ISS ISP H3A Top-Level Block Diagram
9.3.3.8.3
ISS ISP H3A Line Framing Logic
9.3.3.8.4
ISS ISP H3A Optional Preprocessing
9.3.3.8.5
ISS ISP H3A Autofocus Engine
9.3.3.8.5.1
ISS ISP H3A Paxel Extraction
9.3.3.8.5.2
ISS ISP H3A Horizontal FV Calculator
9.3.3.8.5.3
ISS ISP H3A HFV Accumulator
9.3.3.8.5.4
ISS ISP H3A VFV Calculator
9.3.3.8.5.5
ISS ISP H3A VFV Accumulator
9.3.3.8.6
ISS ISP H3A AE/AWB Engine
9.3.3.8.6.1
ISS ISP H3A Subsampler
9.3.3.8.6.2
ISS ISP H3A Additional Black Row of AE/AWB Windows
9.3.3.8.6.3
ISS ISP H3A Saturation Check
9.3.3.8.6.4
ISS ISP H3A AE/AWB Accumulators
9.3.3.8.7
ISS ISP H3A DMA Interface
9.3.3.8.8
ISS ISP H3A Events and Status Checking
9.3.3.9
ISS ISP ISIF Functional Description
9.3.3.9.1
ISS ISP ISIF Overview
9.3.3.9.2
ISS ISP ISIF Top-Level Block Diagram
9.3.3.9.3
ISS ISP ISIF Input Interface
9.3.3.9.4
ISS ISP ISIF Interface
9.3.3.9.5
ISS ISP ISIF Sensor Linearization
9.3.3.9.6
ISS ISP ISIF Input Data Formatter
9.3.3.9.6.1
1714
9.3.3.9.6.2
ISS ISP ISIF Formatter Area Settings
9.3.3.9.6.3
ISS ISP ISIF Formatter Programming
9.3.3.9.6.4
ISS ISP ISIF Combine the Divided Input Lines
9.3.3.9.7
ISS ISP ISIF Color Space Converter
9.3.3.9.8
ISS ISP ISIF Black Clamp
9.3.3.9.8.1
ISS ISP ISIF Clamp Value for Horizontal Direction
9.3.3.9.8.2
ISS ISP ISIF Clamp Value for Vertical Direction
9.3.3.9.9
ISS ISP ISIF Vertical Line Defect Correction (VDFC)
9.3.3.9.9.1
ISS ISP ISIF Vertical Line Defect Table Update Procedure
9.3.3.9.10
ISS ISP ISIF Lens Shading Correction Module (2D-LSC)
9.3.3.9.10.1
ISS ISP ISIF 2D-LSC Active Region Settings
9.3.3.9.10.1.1
ISS ISP ISIF 2D-LSC Gain and Offset Tables
9.3.3.9.10.1.2
ISS ISP ISIF 2D-LSC Gain and Offset Table Upsampling
9.3.3.9.10.1.3
ISS ISP ISIF Application of Gain and Offset to Image Pixels
9.3.3.9.10.1.4
ISS ISP ISIF Enabling and Disabling the 2D-LSC Module
9.3.3.9.10.1.5
ISS ISP ISIF 2D-LSC Events and Status Checking
9.3.3.9.10.1.6
ISS ISP ISIF Supported On-the-Fly 2D-LSC Configurations
9.3.3.9.10.1.7
ISS ISP ISIF Bandwidth Requirements on BL Read Port
9.3.3.9.11
ISS ISP ISIF White Balance
9.3.3.9.12
ISS ISP ISIF Low-Pass Filter
9.3.3.9.13
ISS ISP ISIF A-Law Compression
9.3.3.9.14
ISS ISP ISIF Culling
9.3.3.9.15
ISS ISP ISIF 12-to-8-Bit DPCM Compression Block
9.3.3.9.16
ISP ISIF Storage Formatter
9.3.3.9.17
ISS ISP ISIF Circular Buffer
9.3.3.9.18
ISS ISP ISIF YCbCr Signal Processing
9.3.3.9.19
ISS ISP ISIF Expected Bandwidth on BL Ports
9.3.3.9.19.1
ISS ISP ISIF Write Port
9.3.3.9.19.2
ISS ISP ISIF Read Port
9.3.3.9.20
ISS ISP ISIF Events and Status Checking
9.3.3.9.20.1
ISS ISP ISIF VDINT0, VDINT1, and VDINT2 Interrupts
9.3.3.9.20.2
ISS ISP ISIF 2DLSCINT Interrupt
9.3.3.9.20.3
ISS ISP ISIF Status Checking
9.3.3.10
ISS ISP BL Functional Description
9.3.3.10.1
ISS ISP BL Overview
9.3.3.10.2
ISS ISP BL Functional Description
9.3.3.10.3
ISS ISP BL Address Alignment
9.3.3.10.4
ISS ISP BL Out-of-Order Responses
9.3.3.10.5
ISS ISP BL Stalling
9.3.3.10.5.1
ISS ISP BL Stalling Write Requests
9.3.3.10.5.2
ISS ISP BL Stalling Read Requests
9.3.3.10.6
ISS ISP BL Dynamic and Static MFlag Generation
9.3.3.10.7
ISS ISP BL VBUSM2OCP Last Beat Command Delay
9.3.3.10.8
ISS ISP BL Peak Memory Bandwidth Reduction
9.3.3.11
ISS ISP Memory Mapping
9.3.4
ISS ISP Register Manual
9.3.4.1
ISS ISP Instance Summary
9.3.4.2
ISS ISP6P5_SYS1 Registers
9.3.4.2.1
ISS ISP6P5_SYS1 Register Summary
9.3.4.2.2
ISS ISP6P5_SYS1 Register Description
9.3.4.3
ISS ISP6P5_SYS2 Registers
9.3.4.3.1
ISS ISP6P5_SYS2 Register Summary
9.3.4.3.2
ISS ISP6P5_SYS2 Register Description
9.3.4.4
ISS ISP6P5_RESIZER Registers
9.3.4.4.1
ISS ISP6P5_RESIZER Register Summary
9.3.4.4.2
ISS ISP6P5_RESIZER Register Description
9.3.4.5
ISS ISP6P5_IPIPE Registers
9.3.4.5.1
ISS ISP6P5_IPIPE Register Summary
9.3.4.5.2
ISS ISP6P5_IPIPE Register Description
9.3.4.6
ISS ISP6P5_ISIF Registers
9.3.4.6.1
ISS ISP6P5_ISIF Register Summary
9.3.4.6.2
ISS ISP6P5_ISIF Register Description
9.3.4.7
ISS ISP6P5_IPIPEIF Registers
9.3.4.7.1
ISS ISP6P5_IPIPEIF Register Summary
9.3.4.7.2
ISS ISP6P5_IPIPEIF Register Description
9.3.4.8
ISS ISP6P5_H3A Registers
9.3.4.8.1
ISS ISP6P5_H3A Register Summary
9.3.4.8.2
ISS ISP6P5_H3A Register Description
9.3.4.9
ISS ISP6P5_SYS3 Registers
9.3.4.9.1
ISS ISP6P5_SYS3 Register Summary
9.3.4.9.2
ISS ISP6P5_SYS3 Register Description
9.3.4.10
ISS ISP6P5 CNF1 and NSF3V Registers
9.3.4.10.1
ISS ISP6P5 CNF1 and NSF3V Register Summary
9.3.4.10.2
ISS ISP6P5 CNF1 and NSF3V Register Description
9.3.4.11
ISS ISP6P5_GLBCE Registers
9.3.4.11.1
ISS ISP6P5_GLBCE Register Summary
9.3.4.11.2
ISS ISP6P5_GLBCE Register Description
9.4
ISS Still Image Coprocessor (SIMCOP)
9.4.1
ISS SIMCOP Overview
9.4.1.1
ISS SIMCOP Integration
9.4.1.2
ISS SIMCOP Functional Description
9.4.1.2.1
ISS SIMCOP Local Power and Clock Management
9.4.1.2.1.1
ISS SIMCOP Local Clock Management
9.4.1.2.1.2
Local Clock Autogating
9.4.1.2.1.3
ISS SIMCOP Power Management
9.4.1.2.2
ISS SIMCOP Reset
9.4.1.2.3
ISS SIMCOP Interrupt Merger
9.4.1.2.4
ISS SIMCOP Modules Description
9.4.1.3
ISS SIMCOP Programming Models
9.4.1.3.1
Global Initialization
9.4.1.3.1.1
Surrounding Modules Global Initialization
9.4.1.3.1.2
ISS SIMCOP Module Global Initialization
9.4.1.3.2
ISS SIMCOP Operational Modes Configuration
9.4.1.3.2.1
Interrupts
9.4.1.4
ISS SIMCOP Registers Manual
9.4.1.4.1
SIMCOP Instance Summary
9.4.1.4.2
SIMCOP Registers
9.4.1.4.2.1
SIMCOP Register Summary
9.4.1.4.2.2
SIMCOP Register Description
9.4.2
ISS SIMCOP Hardware Sequencer and Buffers Module
9.4.2.1
ISS SIMCOP Hardware Sequencer and Buffers Overview
9.4.2.2
ISS SIMCOP Hardware Sequencer and Buffer Integration
9.4.2.3
ISS SIMCOP Hardware Sequencer and Buffers Functional Description
9.4.2.3.1
ISS SIMCOP Hardware Sequencer and Buffers Software Reset
9.4.2.3.2
ISS SIMCOP Hardware Sequencer and Buffers Power Management
9.4.2.3.3
ISS SIMCOP Hardware Sequencer and Buffer Interrupt Requests
9.4.2.3.3.1
Static Crossbar
9.4.2.3.3.2
Image Buffers
9.4.2.3.4
ISS SIMCOP Hardware Sequencer
9.4.2.3.4.1
Automatic Operation
9.4.2.3.4.2
Hardware Sequencer Override
9.4.2.4
ISS SIMCOP Hardware Sequencer and Buffers Basic Programming Model
9.4.2.4.1
ISS SIMCOP Hardware Sequencer and Buffers Application Programming Principle
9.4.2.4.2
External CPU Use for Data Processing
9.4.2.5
ISS SIMCOP Hardware Sequencer and Buffer Registers Manual
9.4.2.5.1
Hardware Sequencer Instance Summary
9.4.2.5.2
Hardware Sequencer Registers
9.4.2.5.2.1
Hardware Sequencer Register Summary
9.4.2.5.2.2
Hardware Sequencer Register Description
9.4.3
ISS SIMCOP DMA Module
9.4.3.1
ISS SIMCOP DMA Overview
9.4.3.2
ISS SIMCOP DMA Integration
9.4.3.3
ISS SIMCOP DMA Functional Description
9.4.3.3.1
ISS SIMCOP DMA Block Diagram
9.4.3.3.2
ISS SIMCOP DMA Power Management
9.4.3.3.3
ISS SIMCOP DMA Interrupt Requests
9.4.3.3.4
ISS SIMCOP DMA Logical Channels
9.4.3.3.4.1
Logical Channel States
9.4.3.3.4.2
Logical Channel Chaining, Trigger, and Hardware Synchronization
9.4.3.3.4.3
Logical Channel Data Transfer
9.4.3.3.5
Transaction Generation
9.4.3.3.5.1
Incrementing Bursts for Regular Transfers
9.4.3.4
ISS SIMCOP DMA Basic Programming Model
9.4.3.4.1
Initialization of Surrounding Modules
9.4.3.4.2
ISS SIMCOP DMA Channel Configuration and Hardware Synchronization
9.4.3.4.3
Software Synchronization
9.4.3.5
ISS SIMCOP DMA Register Manual
9.4.3.5.1
ISS SIMCOP DMA Instance Summary
9.4.3.5.2
ISS SIMCOP DMA Registers
9.4.3.5.2.1
ISS SIMCOP DMA Register Summary
9.4.3.5.2.2
ISS SIMCOP DMA Register Description
9.4.4
ISS SIMCOP VTNF Module
9.4.4.1
ISS SIMCOP VTNF Overview
9.4.4.2
ISS SIMCOP VTNF Environment
9.4.4.2.1
ISS SIMCOP VTNF Protocols and Data Formats
9.4.4.3
ISS SIMCOP VTNF Integration
9.4.4.4
ISS SIMCOP VTNF Functional Description
9.4.4.4.1
ISS SIMCOP VTNF Block Diagram
9.4.4.4.2
ISS SIMCOP VTNF Clocks Management
9.4.4.4.3
ISS SIMCOP VTNF Interrupt Requests
9.4.4.4.4
ISS SIMCOP VTNF Configuration
9.4.4.4.4.1
ISS SIMCOP VTNF Initialization
9.4.4.4.4.2
ISS SIMCOP VTNF Programming Ranges and Restrictions
9.4.4.4.4.3
ISS SIMCOP VTNF Resets
9.4.4.4.4.4
ISS SIMCOP VTNF Programming Parameters Tuning
9.4.4.5
ISS SIMCOP VTNF Register Manual
9.4.4.5.1
ISS SIMCOP VTNF Instance Summary
9.4.4.5.2
ISS SIMCOP VTNF registers
9.4.4.5.2.1
ISS SIMCOP VTNF Register Summary
9.4.4.5.2.2
ISS SIMCOP VTNF Register Description
9.4.5
ISS SIMCOP LDC Module
9.4.5.1
ISS SIMCOP LDC Overview
9.4.5.2
ISS SIMCOP LDC Integration
9.4.5.3
ISS SIMCOP LDC Functional Description
9.4.5.3.1
ISS SIMCOP LDC Block Diagram
9.4.5.3.2
ISS SIMCOP LDC Interrupt Requests
9.4.5.3.3
ISS SIMCOP LDC Input/Output Format Data
9.4.5.3.3.1
ISS SIMCOP LDC YCbCr Format
9.4.5.3.3.2
ISS SIMCOP LDC Bayer Format
9.4.5.3.4
ISS SIMCOP Lens Distortion Back-Mapping
9.4.5.3.5
ISS SIMCOP LCD Bayer Chromatic Aberration Correction Implementation
9.4.5.3.6
ISS SIMCOP LDC Affine Transform
9.4.5.3.7
ISS SIMCOP LDC Perspective Transformation
9.4.5.3.8
ISS SIMCOP LDC Pixel Interpolation
9.4.5.3.9
ISS SIMCOP LDC Buffer Management
9.4.5.3.10
ISS SIMCOP LDC Input Circular Buffer
9.4.5.3.11
ISS SIMCOP LDC and Hardware Sequencer
9.4.5.3.11.1
ISS SIMCOP LDC and Hardware Sequencer and Buffers Overview
9.4.5.3.11.2
ISS SIMCOP LDC and Hardware Sequencer and Buffer Integration
9.4.5.3.11.3
ISS SIMCOP LDC and Hardware Sequencer and Buffers Functional Description
9.4.5.3.11.3.1
ISS SIMCOP Hardware Sequencer Buffer Description
9.4.5.3.11.3.1.1
ISS SIMCOP LDC Static Crossbar
9.4.5.3.11.3.1.2
ISS SIMCOP LDC Private Input Memory
9.4.5.3.11.3.2
ISS SIMCOP Hardware Sequencer
9.4.5.3.11.3.2.1
Hardware Sequencer Override
9.4.5.4
ISS SIMCOP LDC Basic Programming Model
9.4.5.4.1
ISS SIMCOP LDC Initialization of Surrounding Modules
9.4.5.4.2
ISS SIMCOP LDC Geometric Distortion Mode
9.4.5.4.3
ISS SIMCOP LDC Bayer Chromatic Aberration Mode
9.4.5.4.4
ISS SIMCOP LDC Programming Affine Transformation
9.4.5.4.5
ISS SIMCOP LDC Programming Perspective Transformation
9.4.5.5
ISS SIMCOP LDC Register Manual
9.4.5.5.1
ISS SIMCOP LDC Instance Summary
9.4.5.5.2
ISS SIMCOP LDC Registers
9.4.5.5.2.1
ISS SIMCOP LDC Register Summary
9.4.5.5.2.2
ISS SIMCOP LDC Register Description
10
Camera Interface Subsystem
10.1
CAMSS Overview
10.1.1
CAMSS Block Diagram
10.1.2
1914
10.1.3
CAMSS Features
10.2
CAMSS Environment
10.2.1
CAMSS Interfaces Signal Descriptions
10.3
CAMSS Integration
10.3.1
CAMSS Main Integration Attributes
10.3.2
CAL Integration - Video Port
10.3.3
CAL Integration - PPI Interface
10.4
CAMSS Functional Description
10.4.1
CAMSS Hardware and Software Reset
10.4.2
CAMSS Clock Configuration
10.4.3
CAMSS Power Management
10.4.4
CAMSS Interrupt Events
10.4.5
CSI2 PHY Functional Description
10.4.5.1
CSI2 PHY Overview
10.4.5.2
CSI2 PHY Configuration
10.4.5.3
CSI2 PHY Link Initialization Sequence
10.4.5.4
CSI2 PHY Error Signals
10.4.6
CAL Functional Description
10.4.6.1
CAL Block Diagram
10.4.6.2
CSI2 Low Level Protocol
10.4.6.2.1
CSI2 Physical Layer
10.4.6.2.2
CSI2 Multi-lane Layer and Lane Merger
10.4.6.2.3
CSI2 Protocol Layer
10.4.6.2.3.1
CSI2 Short Packet
10.4.6.2.3.2
CSI2 Long Packet
10.4.6.2.3.3
CSI2 ECC and Checksum Generation
10.4.6.2.3.3.1
CSI2 ECC
10.4.6.2.3.3.2
CSI2 Checksum
10.4.6.2.3.4
CSI2 Alignment Constraints
10.4.6.2.3.5
CSI2 Data Identifier
10.4.6.2.3.6
CSI2 Virtual Channel ID
10.4.6.2.3.7
CSI2 Synchronization Codes
10.4.6.2.3.8
CSI2 Generic Short Packet Codes
10.4.6.2.3.9
CSI2 Frame Structure and Data
10.4.6.2.3.10
CSI2 Virtual Channel and Context
10.4.6.2.4
CSI2 TAG Generation FSM
10.4.6.3
CAL Data Stream Merger
10.4.6.4
CAL Pixel Extraction
10.4.6.5
CAL DPCM Decoding and Encoding
10.4.6.6
CAL Stream Interleaving
10.4.6.7
CAL Pixel Packing
10.4.6.8
CAL Write DMA
10.4.6.8.1
CAL Write DMA Overview
10.4.6.8.2
CAL Write DMA Data Cropping
10.4.6.8.3
CAL Write DMA YUV422 to YUV422BP Conversion
10.4.6.8.4
CAL Write DMA Buffer Management
10.4.6.8.5
CAL Write DMA OCP Address Generation
10.4.6.8.5.1
Write DMA Buffer Base Address
10.4.6.8.5.2
Write DMA Line Start Address
10.4.6.8.5.3
Write DMA Data Address
10.4.6.8.6
CAL Write DMA OCP Transaction Generation
10.4.6.8.7
CAL Write DMA Real Time Traffic
10.4.6.9
CAL Video Port
10.4.6.9.1
CAL Video Port Overview
10.4.6.9.2
CAL Video Port Pixel Clock Generation
10.4.6.9.3
CAL Video Port Video Timing Generator
10.4.6.10
CAL Registers Shadowing
10.5
CAMSS Register Manual
10.5.1
CAMSS Instance Summary
10.5.2
CAL Registers
10.5.2.1
CAL Register Summary
10.5.2.2
CAL Register Description
10.5.3
CSI2 PHY Registers
10.5.3.1
CSI2 PHY Register Summary
10.5.3.2
CSI2 PHY Register Description
11
Video Input Port
11.1
VIP Overview
11.2
VIP Environment
11.3
VIP Integration
11.4
VIP Functional Description
11.4.1
VIP Block Diagram
11.4.2
VIP Software Reset
11.4.3
VIP Power and Clocks Management
11.4.3.1
VIP Clocks
11.4.3.2
VIP Idle Mode
11.4.3.3
VIP StandBy Mode
11.4.4
VIP Slice
11.4.4.1
VIP Slice Processing Path Overview
11.4.4.2
VIP Slice Processing Path Multiplexers
11.4.4.2.1
VIP_CSC Multiplexers
11.4.4.2.2
VIP_SC Multiplexer
11.4.4.2.3
Output to VPDMA Multiplexers
11.4.4.3
VIP Slice Processing Path Examples
11.4.4.3.1
Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB
11.4.4.3.2
Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB
11.4.4.3.3
Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420
11.4.4.3.4
Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422
11.4.4.3.5
Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420
11.4.4.3.6
Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444
11.4.4.3.7
Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444
11.4.4.3.8
Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420
11.4.4.3.9
Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420
11.4.5
VIP Parser
11.4.5.1
Features
11.4.5.2
Repacker
11.4.5.3
Analog Video
11.4.5.4
Digitized Video
11.4.5.5
Frame Buffers
11.4.5.6
Input Data Interface
11.4.5.6.1
8b Interface Mode
11.4.5.6.2
16b Interface Mode
11.4.5.6.3
24b Interface Mode
11.4.5.6.4
Signal Relationships
11.4.5.6.5
General 5 Pin Interfaces
11.4.5.6.6
Signal Subsets—4 Pin VSYNC, ACTVID, and FID
11.4.5.6.7
Signal Subsets—4 Pin VSYNC, HSYNC, and FID
11.4.5.6.8
Vertical Sync
11.4.5.6.9
Field ID Determination Using Dedicated Signal
11.4.5.6.10
Field ID Determination Using VSYNC Skew
11.4.5.6.11
Rationale for FID Determination By VSYNC Skew
11.4.5.6.12
ACTVID Framing
11.4.5.6.13
Ancillary Data Storage in Descrete Sync Mode
11.4.5.7
BT.656 Style Embedded Sync
11.4.5.7.1
Data Input
11.4.5.7.2
Sync Words
11.4.5.7.3
Error Correction
11.4.5.7.4
Embedded Sync Ancillary Data
11.4.5.7.5
Embedded Sync RGB 24-bit Data
11.4.5.8
Source Multiplexing
11.4.5.8.1
Multiplexing Scenarios
11.4.5.8.2
2-Way Multiplexing
11.4.5.8.3
4-Way Multiplexing
11.4.5.8.4
Line Multiplexing
11.4.5.8.5
Super Frame Concept in Line Multiplexing
11.4.5.8.6
8-bit Data Interface in Line Multiplexing
11.4.5.8.7
16-bit Data Interface in Line Multiplexing
11.4.5.8.8
Split Lines in Line Multiplex Mode
11.4.5.8.9
Meta Data
11.4.5.8.10
TI Line Mux Mode, Split Lines, and Channel ID Remapping
11.4.5.9
Channel ID Extraction for 2x/4x Multiplexed Source
11.4.5.9.1
Channel ID Extraction Overview
11.4.5.9.2
Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing
11.4.5.9.3
Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing
11.4.5.10
Embedded Sync Mux Modes and Data Bus Widths
11.4.5.11
Ancillary and Active Video Cropping
11.4.5.12
Interrupts
11.4.5.13
VDET Interrupt
11.4.5.14
Source Video Size
11.4.5.15
Clipping
11.4.5.16
Current and Last FID Value
11.4.5.17
Disable Handling
11.4.5.18
Picture Size Interrupt
11.4.5.19
Discrete Sync Signals
11.4.5.19.1
VBLNK and HBLNK
11.4.5.19.2
BLNK and ACTVID (1)
11.4.5.19.3
VBLNK and ACTVID(2)
11.4.5.19.4
VBLNK and HSYNC
11.4.5.19.5
VSYNC and HBLNK
11.4.5.19.6
VSYNC and ACTIVID(1)
11.4.5.19.7
VSYNC and ACTIVID(2)
11.4.5.19.8
VSYNC and HSYNC
11.4.5.19.9
Line and Pixel Capture Examples
11.4.5.20
VIP Overflow Detection and Recovery
11.4.6
VIP Color Space Converter (CSC)
11.4.6.1
CSC Features
11.4.6.2
CSC Functional Description
11.4.6.2.1
HDTV Application
11.4.6.2.1.1
HDTV Application with Video Data Range
11.4.6.2.1.2
HDTV Application with Graphics Data Range
11.4.6.2.1.3
Quantized Coefficients for Color Space Converter in HDTV
11.4.6.2.2
SDTV Application
11.4.6.2.2.1
SDTV Application with Video Data Range
11.4.6.2.2.2
SDTV Application with Graphics Data Range
11.4.6.2.2.3
Quantized Coefficients for Color Space Converter in SDTV
11.4.6.3
CSC Bypass Mode
11.4.7
VIP Scaler (SC)
11.4.7.1
SC Features
11.4.7.2
SC Functional Description
11.4.7.2.1
Trimmer
11.4.7.2.2
2084
11.4.7.2.3
Peaking
11.4.7.2.4
Vertical Scaler
11.4.7.2.4.1
Running Average Filter
11.4.7.2.4.2
Vertical Scaler Configuration Parameters
11.4.7.2.5
Horizontal Scaler
11.4.7.2.5.1
Half Decimation Filter
11.4.7.2.5.2
Polyphase Filter
11.4.7.2.5.3
Nonlinear Horizontal Scaling
11.4.7.2.5.4
Horizontal Scaler Configuration Registers
11.4.7.2.6
Basic Configurations
11.4.7.2.7
Coefficient Memory
11.4.7.2.7.1
Overview
11.4.7.2.7.2
Physical Coefficient SRAM Layout
11.4.7.2.7.3
Scaler Coefficients Packing on 128-bit VPI Control I/F
11.4.7.2.7.4
VPI Control I/F Memory Map for Scaler Coefficients
11.4.7.2.7.5
VPI Control Interface
11.4.7.2.7.6
Coefficient Table Selection Guide
11.4.7.3
SC Code
11.4.7.3.1
Generate Coefficient Memory Image
11.4.7.3.2
Scaler Configuration Calculation
11.4.7.3.3
Typical Configuration Values
11.4.7.4
SC Coefficient Data Files
11.4.7.4.1
HS Polyphase Filter Coefficients
11.4.7.4.1.1
ppfcoef_scale_eq_1_32_phases_flip.dat
11.4.7.4.1.2
ppfcoef_scale_eq_8div16_32_phases_flip.dat
11.4.7.4.1.3
ppfcoef_scale_eq_9div16_32_phases_flip.dat
11.4.7.4.1.4
ppfcoef_scale_eq_10div16_32_phases_flip.dat
11.4.7.4.1.5
ppfcoef_scale_eq_11div16_32_phases_flip.dat
11.4.7.4.1.6
ppfcoef_scale_eq_12div16_32_phases_flip.dat
11.4.7.4.1.7
ppfcoef_scale_eq_13div16_32_phases_flip.dat
11.4.7.4.1.8
ppfcoef_scale_eq_14div16_32_phases_flip.dat
11.4.7.4.1.9
ppfcoef_scale_eq_15div16_32_phases_flip.dat
11.4.7.4.2
VS Polyphase Filter Coefficients
11.4.7.4.2.1
ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
11.4.7.4.2.2
ppfcoef_scale_eq_3_32_phases_flip.dat
11.4.7.4.2.3
ppfcoef_scale_eq_4_32_phases_flip.dat
11.4.7.4.2.4
ppfcoef_scale_eq_5_32_phases_flip.dat
11.4.7.4.2.5
ppfcoef_scale_eq_6_32_phases_flip.dat
11.4.7.4.2.6
ppfcoef_scale_eq_7_32_phases_flip.dat
11.4.7.4.2.6.1
ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.2
ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.3
ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.4
ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.5
ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.6
ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.7
ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
11.4.7.4.2.6.8
ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
11.4.7.4.3
VS (Bilinear Filter Coefficients)
11.4.7.4.3.1
ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
11.4.8
VIP Video Port Direct Memory Access (VPDMA)
11.4.8.1
VPDMA Introduction
11.4.8.2
VPDMA Basic Definitions
11.4.8.2.1
Client
11.4.8.2.2
Channel
11.4.8.2.3
List
11.4.8.2.4
Data Formats Supported
11.4.8.3
2141
11.4.8.4
VPDMA Client Buffering and Functionality
11.4.8.5
VPDMA Channels Assignment
11.4.8.6
VPDMA MFLAG Mechanism
11.4.8.7
VPDMA Interrupts
11.4.8.8
VPDMA Descriptors
11.4.8.8.1
Data Transfer Descriptors
11.4.8.8.1.1
Data Packet Descriptor Word 0 (Data)
11.4.8.8.1.1.1
Data Type
11.4.8.8.1.1.2
Notify
11.4.8.8.1.1.3
Field
11.4.8.8.1.1.4
Even Line Skip
11.4.8.8.1.1.5
Odd Line Skip
11.4.8.8.1.1.6
Line Stride
11.4.8.8.1.2
Data Packet Descriptor Word 1
11.4.8.8.1.2.1
Line Length
11.4.8.8.1.2.2
Transfer Height
11.4.8.8.1.3
Data Packet Descriptor Word 2
11.4.8.8.1.3.1
Start Address
11.4.8.8.1.4
Data Packet Descriptor Word 3
11.4.8.8.1.4.1
Packet Type
11.4.8.8.1.4.2
Mode
11.4.8.8.1.4.3
Direction
11.4.8.8.1.4.4
Channel
11.4.8.8.1.4.5
Priority
11.4.8.8.1.4.6
Next Channel
11.4.8.8.1.5
Data Packet Descriptor Word 4
11.4.8.8.1.5.1
Inbound data
11.4.8.8.1.5.1.1
Frame Width
11.4.8.8.1.5.1.2
Frame Height
11.4.8.8.1.5.2
Outbound data
11.4.8.8.1.5.2.1
Descriptor Write Address
11.4.8.8.1.5.2.2
Write Descriptor
11.4.8.8.1.5.2.3
Drop Data
11.4.8.8.1.6
Data Packet Descriptor Word 5
11.4.8.8.1.6.1
Outbound data
11.4.8.8.1.6.1.1
Max Width
11.4.8.8.1.6.1.2
Max Height
11.4.8.8.2
Configuration Descriptor
11.4.8.8.2.1
Configuration Descriptor Header Word0
11.4.8.8.2.2
Configuration Descriptor Header Word1
11.4.8.8.2.2.1
Number of Data Words
11.4.8.8.2.3
Configuration Descriptor Header Word2
11.4.8.8.2.3.1
Payload Location
11.4.8.8.2.4
Configuration Descriptor Header Word3
11.4.8.8.2.4.1
Packet Type
11.4.8.8.2.4.2
Direct
11.4.8.8.2.4.3
Class
11.4.8.8.2.4.3.1
Address Data Block Format
11.4.8.8.2.4.4
Destination
11.4.8.8.2.4.5
Descriptor Length
11.4.8.8.3
Control Descriptor
11.4.8.8.3.1
Generic Control Descriptor Format
11.4.8.8.3.2
Control Descriptor Header Description
11.4.8.8.3.2.1
Packet Type
11.4.8.8.3.2.2
Source
11.4.8.8.3.2.3
Control
11.4.8.8.3.3
Control Descriptor Types
11.4.8.8.3.3.1
Sync on Client
11.4.8.8.3.3.2
Sync on List
11.4.8.8.3.3.3
Sync on External Event
11.4.8.8.3.3.4
Sync on Channel
11.4.8.8.3.3.5
Sync on LM Timer
11.4.8.8.3.3.6
Change Client Interrupt
11.4.8.8.3.3.7
Send Interrupt
11.4.8.8.3.3.8
Reload List
11.4.8.8.3.3.9
Abort Channel
11.4.8.9
VPDMA Configuration
11.4.8.9.1
Regular List
11.4.8.9.2
Video Input Ports
11.4.8.9.2.1
Multiplexed Data Streams
11.4.8.9.2.2
Single YUV Color Separate
11.4.8.9.2.3
Dual YUV Interleaved
11.4.8.10
VPDMA Data Formats
11.4.8.10.1
YUV Data Formats
11.4.8.10.1.1
Y 4:4:4 (Data Type 0)
11.4.8.10.1.2
Y 4:2:2 (Data Type 1)
11.4.8.10.1.3
Y 4:2:0 (Data Type 2)
11.4.8.10.1.4
C 4:4:4 (Data Type 4)
11.4.8.10.1.5
C 4:2:2 (Data Type 5)
11.4.8.10.1.6
C 4:2:0 (Data Type 6)
11.4.8.10.1.7
YC 4:2:2 (Data Type 7)
11.4.8.10.1.8
YC 4:4:4 (Data Type 8)
11.4.8.10.1.9
CY 4:2:2 (Data Type 23)
11.4.8.10.2
RGB Data Formats
11.4.8.10.2.1
RGB16-565 (Data Type 0)
11.4.8.10.2.2
ARGB-1555 (Data Type 1)
11.4.8.10.2.3
ARGB-4444 (Data Type 2)
11.4.8.10.2.4
RGBA-5551 (Data Type 3)
11.4.8.10.2.5
RGBA-4444 (Data Type 4)
11.4.8.10.2.6
ARGB24-6666 (Data Type 5)
11.4.8.10.2.7
RGB24-888 (Data Type 6)
11.4.8.10.2.8
ARGB32-8888 (Data Type 7)
11.4.8.10.2.9
RGBA24-6666 (Data Type 8)
11.4.8.10.2.10
RGBA32-8888 (Data Type 9)
11.4.8.10.3
Miscellaneous Data Type
11.5
VIP Register Manual
11.5.1
VIP Instance Summary
11.5.2
VIP Top Level Registers
11.5.2.1
VIP Top Level Register Summary
11.5.2.2
VIP Top Level Register Description
11.5.3
VIP Parser Registers
11.5.3.1
VIP Parser Register Summary
11.5.3.2
VIP Parser Register Description
11.5.4
VIP CSC Registers
11.5.4.1
VIP CSC Register Summary
11.5.4.2
VIP CSC Register Description
11.5.5
VIP SC registers
11.5.5.1
VIP SC Register Summary
11.5.5.2
VIP SC Register Description
11.5.6
VIP VPDMA Registers
11.5.6.1
VIP VPDMA Register Summary
11.5.6.2
VIP VPDMA Register Description
12
Video Processing Engine
12.1
VPE Overview
12.2
VPE Integration
12.3
VPE Functional Description
12.3.1
VPE Block Diagram
12.3.2
VPE VC1 Range Mapping/Range Reduction
12.3.3
VPE Deinterlacer (DEI)
12.3.3.1
Functional Description
12.3.3.2
Bypass Mode
12.3.3.3
2263
12.3.3.3.1
VPDMA Interface
12.3.3.3.2
MDT
12.3.3.3.3
EDI
12.3.3.3.4
FMD
12.3.3.3.5
MUX
12.3.3.3.6
LINE BUFFER
12.3.4
VPE Scaler (SC)
12.3.4.1
SC Features
12.3.4.2
SC Functional Description
12.3.4.2.1
Trimmer
12.3.4.2.2
2274
12.3.4.2.3
Peaking
12.3.4.2.4
Vertical Scaler
12.3.4.2.4.1
Running Average Filter
12.3.4.2.4.2
Vertical Scaler Configuration Parameters
12.3.4.2.5
Horizontal Scaler
12.3.4.2.5.1
Half Decimation Filter
12.3.4.2.5.2
Polyphase Filter
12.3.4.2.5.3
Nonlinear Horizontal Scaling
12.3.4.2.5.4
Horizontal Scaler Configuration Registers
12.3.4.2.6
Basic Configurations
12.3.4.2.7
Coefficient Memory
12.3.4.2.7.1
Overview
12.3.4.2.7.2
Physical Coefficient SRAM Layout
12.3.4.2.7.3
Scaler Coefficients Packing on 128-bit VPI Control I/F
12.3.4.2.7.4
VPI Control I/F Memory Map for Scaler Coefficients
12.3.4.2.7.5
VPI Control Interface
12.3.4.2.7.6
Coefficient Table Selection Guide
12.3.4.3
SC Code
12.3.4.3.1
Generate Coefficient Memory Image
12.3.4.3.2
Scaler Configuration Calculation
12.3.4.3.3
Typical Configuration Values
12.3.4.4
SC Coefficient Data Files
12.3.4.4.1
HS Polyphase Filter Coefficients
12.3.4.4.1.1
ppfcoef_scale_eq_1_32_phases_flip.dat
12.3.4.4.1.2
ppfcoef_scale_eq_8div16_32_phases_flip.dat
12.3.4.4.1.3
ppfcoef_scale_eq_9div16_32_phases_flip.dat
12.3.4.4.1.4
ppfcoef_scale_eq_10div16_32_phases_flip.dat
12.3.4.4.1.5
ppfcoef_scale_eq_11div16_32_phases_flip.dat
12.3.4.4.1.6
ppfcoef_scale_eq_12div16_32_phases_flip.dat
12.3.4.4.1.7
ppfcoef_scale_eq_13div16_32_phases_flip.dat
12.3.4.4.1.8
ppfcoef_scale_eq_14div16_32_phases_flip.dat
12.3.4.4.1.9
ppfcoef_scale_eq_15div16_32_phases_flip.dat
12.3.4.4.2
VS Polyphase Filter Coefficients
12.3.4.4.2.1
ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
12.3.4.4.2.2
ppfcoef_scale_eq_3_32_phases_flip.dat
12.3.4.4.2.3
ppfcoef_scale_eq_4_32_phases_flip.dat
12.3.4.4.2.4
ppfcoef_scale_eq_5_32_phases_flip.dat
12.3.4.4.2.5
ppfcoef_scale_eq_6_32_phases_flip.dat
12.3.4.4.2.6
ppfcoef_scale_eq_7_32_phases_flip.dat
12.3.4.4.2.6.1
ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.2
ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.3
ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.4
ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.5
ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.6
ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.7
ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.8
ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
12.3.4.4.2.6.9
ppcoef_scale_1x_ver_5tap.dat
12.3.4.4.3
VS (Bilinear Filter Coefficients)
12.3.4.4.3.1
ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
12.3.5
VPE Color Space Converter (CSC)
12.3.5.1
CSC Features
12.3.5.2
CSC Functional Description
12.3.5.3
2328
12.3.5.3.1
HDTV Application
12.3.5.3.1.1
HDTV Application with Video Data Range
12.3.5.3.1.2
HDTV Application with Graphics Data Range
12.3.5.3.1.3
Quantized Coefficients for Color Space Converter in HDTV
12.3.5.3.2
SDTV Application
12.3.5.3.2.1
SDTV Application with Video Data Range
12.3.5.3.2.2
SDTV Application with Graphics Data Range
12.3.5.3.2.3
Quantized Coefficients for Color Space Converter in SDTV
12.3.5.4
CSC Bypass Mode
12.3.6
VPE Chroma Up-Sampler (CHR_US)
12.3.6.1
Features
12.3.6.2
Functional Description
12.3.6.3
For Interlaced YUV420 Input Data
12.3.6.4
Edge Effects
12.3.6.5
Modes of Operation (VPDMA)
12.3.6.6
Coefficient Configuration
12.3.7
VPE Chroma Down-Sampler (CHR_DS)
12.3.8
VPE YUV422 to YUV444 Conversion
12.3.9
VPE Video Port Direct Memory Access (VPDMA)
12.3.9.1
VPDMA Introduction
12.3.9.2
VPDMA Basic Definitions
12.3.9.2.1
Client
12.3.9.2.2
Channel
12.3.9.2.3
List
12.3.9.2.4
Data Formats Supported
12.3.9.3
VPDMA Client Buffering and Functionality
12.3.9.4
VPDMA Channels Assignment
12.3.9.5
VPDMA Interrupts
12.3.9.6
VPDMA Descriptors
12.3.9.6.1
Data Transfer Descriptors
12.3.9.6.1.1
Data Packet Descriptor Word 0 (Data)
12.3.9.6.1.1.1
Data Type
12.3.9.6.1.1.2
Notify
12.3.9.6.1.1.3
Field
12.3.9.6.1.1.4
1D
12.3.9.6.1.1.5
Even Line Skip
12.3.9.6.1.1.6
Odd Line Skip
12.3.9.6.1.1.7
Line Stride
12.3.9.6.1.2
Data Packet Descriptor Word 1
12.3.9.6.1.2.1
Line Length
12.3.9.6.1.2.2
Transfer Height
12.3.9.6.1.3
Data Packet Descriptor Word 2
12.3.9.6.1.3.1
Start Address
12.3.9.6.1.4
Data Packet Descriptor Word 3
12.3.9.6.1.4.1
Packet Type
12.3.9.6.1.4.2
Mode
12.3.9.6.1.4.3
Direction
12.3.9.6.1.4.4
Channel
12.3.9.6.1.4.5
Priority
12.3.9.6.1.4.6
Next Channel
12.3.9.6.1.5
Data Packet Descriptor Word 4
12.3.9.6.1.5.1
Inbound data
12.3.9.6.1.5.1.1
Frame Width
12.3.9.6.1.5.1.2
Frame Height
12.3.9.6.1.5.2
Outbound data
12.3.9.6.1.5.2.1
Descriptor Write Address
12.3.9.6.1.5.2.2
Write Descriptor
12.3.9.6.1.5.2.3
Drop Data
12.3.9.6.1.5.2.4
Use Descriptor Register
12.3.9.6.1.6
Data Packet Descriptor Word 5
12.3.9.6.1.6.1
Outbound data
12.3.9.6.1.6.1.1
Max Width
12.3.9.6.1.6.1.2
Max Height
12.3.9.6.1.7
Data Packet Descriptor Word 6/7 (Data)
12.3.9.6.2
Configuration Descriptor
12.3.9.6.2.1
Configuration Descriptor Header Word0
12.3.9.6.2.2
Configuration Descriptor Header Word1
12.3.9.6.2.2.1
Number of Data Words
12.3.9.6.2.3
Configuration Descriptor Header Word2
12.3.9.6.2.3.1
Payload Location
12.3.9.6.2.4
Configuration Descriptor Header Word3
12.3.9.6.2.4.1
Packet Type
12.3.9.6.2.4.2
Direct
12.3.9.6.2.4.3
Class
12.3.9.6.2.4.3.1
Address Data Block Format
12.3.9.6.2.4.4
Destination
12.3.9.6.2.4.5
Descriptor Length
12.3.9.6.3
Control Descriptor
12.3.9.6.3.1
Generic Control Descriptor Format
12.3.9.6.3.2
Control Descriptor Header Description
12.3.9.6.3.2.1
Packet Type
12.3.9.6.3.2.2
Source
12.3.9.6.3.2.3
Control
12.3.9.6.3.3
Control Descriptor Types
12.3.9.6.3.3.1
Sync on Client
12.3.9.6.3.3.2
Sync on List
12.3.9.6.3.3.3
Sync on External Event
12.3.9.6.3.3.4
Sync on Channel
12.3.9.6.3.3.5
Sync on LM Timer
12.3.9.6.3.3.6
Change Client Interrupt
12.3.9.6.3.3.7
Send Interrupt
12.3.9.6.3.3.8
Reload List
12.3.9.6.3.3.9
Abort Channel
12.3.9.7
VPDMA Configuration
12.3.9.7.1
Regular List
12.3.9.7.2
Video Input Ports
12.3.9.7.2.1
Single YUV Color Separate
12.3.9.7.2.2
Dual YUV Interleaved
12.3.9.7.2.3
Single RGB Stream
12.3.9.8
VPDMA Data Formats
12.3.9.8.1
YUV Data Formats
12.3.9.8.1.1
Y 4:4:4 (Data Type 0)
12.3.9.8.1.2
Y 4:2:2 (Data Type 1)
12.3.9.8.1.3
Y 4:2:0 (Data Type 2)
12.3.9.8.1.4
C 4:4:4 (Data Type 4)
12.3.9.8.1.5
C 4:2:2 (Data Type 5)
12.3.9.8.1.6
C 4:2:0 (Data Type 6)
12.3.9.8.1.7
YC 4:2:2 (Data Type 7)
12.3.9.8.1.8
YC 4:4:4 (Data Type 8)
12.3.9.8.1.9
CY 4:2:2 (Data Type 23)
12.3.9.8.2
RGB Data Formats
12.3.9.8.2.1
Input Data Formats
12.3.9.8.2.1.1
RGB16-565 (Data Type 0)
12.3.9.8.2.1.2
ARGB-1555 (Data Type 1)
12.3.9.8.2.1.3
ARGB-4444 (Data Type 2)
12.3.9.8.2.1.4
RGBA-5551 (Data Type 3)
12.3.9.8.2.1.5
RGBA-4444 (Data Type 4)
12.3.9.8.2.1.6
ARGB24-6666 (Data Type 5)
12.3.9.8.2.1.7
RGB24-888 (Data Type 6)
12.3.9.8.2.1.8
ARGB32-8888 (Data Type 7)
12.3.9.8.2.1.9
RGBA24-6666 (Data Type 8)
12.3.9.8.2.1.10
RGBA32-8888 (Data Type 9)
12.3.9.8.2.2
Output Data Formats
12.3.9.8.2.2.1
RGB16-565 (Data Type 0)
12.3.9.8.2.2.2
ARGB-1555 (Data Type 1)
12.3.9.8.2.2.3
ARGB-4444 (Data Type 2)
12.3.9.8.2.2.4
RGBA-5551 (Data Type 3)
12.3.9.8.2.2.5
RGBA-4444 (Data Type 4)
12.3.9.8.2.2.6
ARGB24-6666 (Data Type 5)
12.3.9.8.2.2.7
RGB24-888 (Data Type 6)
12.3.9.8.2.2.8
ARGB32-8888 (Data Type 7)
12.3.9.8.2.2.9
RGBA24-6666 (Data Type 8)
12.3.9.8.2.2.10
RGBA32-8888 (Data Type 9)
12.3.9.8.3
Miscellaneous Data Type
12.3.10
VPE Software Reset
12.3.11
VPE Power and Clocks Management
12.3.11.1
VPE Clocks
12.3.11.2
VPE Idle Mode
12.3.11.3
VPE StandBy Mode
12.4
VPE Register Manual
12.4.1
VPE Instance Summary
12.4.2
VPE_CSC Registers
12.4.2.1
VPE_CSC Register Summary
12.4.2.2
VPE_CSC Register Description
12.4.3
VPE_SC Registers
12.4.3.1
VPE_SC Register Summary
12.4.3.2
VPE_SC Register Description
12.4.4
VPE_CHR_US Registers
12.4.4.1
VPE_CHR_US Register Summary
12.4.4.2
VPE_CHR_US Register Description
12.4.5
VPE_DEI Registers
12.4.5.1
VPE_DEI Register Summary
12.4.5.2
VPE_DEI Register Description
12.4.6
VPE_VPDMA Registers
12.4.6.1
VPE_VPDMA Register Summary
12.4.6.2
VPE_VPDMA Register Description
12.4.7
VPE_TOP_LEVEL Registers
12.4.7.1
VPE_TOP_LEVEL Register Summary
12.4.7.2
VPE_TOP_LEVEL Register Description
13
Display Subsystem
13.1
Display Subsystem Overview
13.1.1
Display Subsystem Environment
13.1.1.1
Display Subsystem LCD Support
13.1.1.1.1
Display Subsystem LCD with Parallel Interfaces
13.1.1.2
Display Subsystem TV Display Support
13.1.1.2.1
Display Subsystem TV With Parallel Interfaces
13.1.1.2.2
Display Subsystem TV With Serial Interfaces
13.1.2
Display Subsystem Integration
13.1.2.1
Display Subsystem Clocks
13.1.2.2
Display Subsystem Resets
13.1.2.3
Display Subsystem Power Management
13.1.2.3.1
Display Subsystem Standby Mode
13.1.2.3.2
2501
13.1.2.3.3
Display Subsystem Wake-Up Mode
13.1.3
Display Subsystem DPLL Controllers Functional Description
13.1.3.1
DPLL Controllers Overview
13.1.3.2
OCP2SCP2 Functional Description
13.1.3.2.1
OCP2SCP2 Reset
13.1.3.2.1.1
Hardware Reset
13.1.3.2.1.2
Software Reset
13.1.3.2.2
OCP2SCP2 Power Management
13.1.3.2.2.1
Idle Mode
13.1.3.2.2.2
Clock Gating
13.1.3.2.3
OCP2SCP2 Timing Registers
13.1.3.3
DPLL_VIDEO Functional Description
13.1.3.3.1
DPLL_VIDEO Controller Architecture
13.1.3.3.2
DPLL_VIDEO Operations
13.1.3.3.3
DPLL_VIDEO Error Handling
13.1.3.3.4
DPLL_VIDEO Software Reset
13.1.3.3.5
DPLL_VIDEO Power Management
13.1.3.3.6
DPLL_VIDEO HSDIVIDER Loading Operation
13.1.3.3.7
DPLL_VIDEO Clock Sequence
13.1.3.3.8
DPLL_VIDEO Go Sequence
13.1.3.3.9
DPLL_VIDEO Recommended Values
13.1.3.4
DPLL_HDMI Functional Description
13.1.3.4.1
DPLL_HDMI and PLLCTRL_HDMI Overview
13.1.3.4.2
DPLL_HDMI and PLLCTRL_HDMI Architecture
13.1.3.4.3
DPLL_HDMI Operations
13.1.3.4.4
DPLL_HDMI Register Access
13.1.3.4.5
DPLL_HDMI Error Handling
13.1.3.4.6
DPLL_HDMI Software Reset
13.1.3.4.7
DPLL_HDMI Power Management
13.1.3.4.8
DPLL_HDMI Lock Sequence
13.1.3.4.9
DPLL_HDMI Go Sequence
13.1.3.4.10
DPLL_HDMI Recommended Values
13.1.4
Display Subsystem Programming Guide
13.1.5
Display Subsystem Register Manual
13.1.5.1
Display Subsystem Instance Summary
13.1.5.2
Display Subsystem Registers
13.1.5.2.1
Display Subsystem Registers Mapping Summary
13.1.5.2.2
Display Subsystem Register Description
13.1.5.3
OCP2SCP2 registers
13.1.5.3.1
OCP2SCP2 Register Summary
13.1.5.3.2
OCP2SCP Register Description
13.1.5.4
DPLL_VIDEO Registers
13.1.5.4.1
DPLL_VIDEO Register Summary
13.1.5.4.2
DPLL_VIDEO Register Description
13.1.5.5
DPLL_HDMI Registers
13.1.5.5.1
DPLL_HDMI Registers Mapping Summary
13.1.5.5.2
DPLL_HDMI Register Description
13.1.5.6
HDMI_WP Registers
13.1.5.6.1
HDMI_WP Registers Mapping Summary
13.1.5.6.2
HDMI_WP Register Description
13.1.5.7
DSI Registers
13.1.5.7.1
DSI Register Summary
13.1.5.7.2
DSI Register Description
13.2
Display Controller
13.2.1
DISPC Overview
13.2.2
DISPC Environment
13.2.2.1
DISPC LCD Output and Data Format for the Parallel Interface
13.2.2.2
DISPC Transaction Timing Diagrams
13.2.2.3
DISPC TV Output and Data Format for the Parallel Interface
13.2.3
DISPC Integration
13.2.4
DISPC Functional Description
13.2.4.1
DISPC Clock Configuration
13.2.4.2
DISPC Software Reset
13.2.4.3
DISPC Power Management
13.2.4.3.1
DISPC Idle Mode
13.2.4.3.2
DISPC StandBy Mode
13.2.4.3.3
DISPC Wakeup
13.2.4.4
DISPC Interrupt Requests
13.2.4.5
DISPC DMA Requests
13.2.4.6
DISPC DMA Engine
13.2.4.6.1
DISPC Addressing and Bursts
13.2.4.6.2
DISPC Immediate Base Address Flip Mechanism
13.2.4.6.3
DISPC DMA Buffers
13.2.4.6.3.1
DISPC READ DMA Buffers (GFX and VID Pipelines)
13.2.4.6.3.2
DISPC WRITE DMA Buffer (WB Pipeline)
13.2.4.6.4
DISPC MFLAG Mechanism and Arbitration
13.2.4.6.5
DISPC Predecimation
13.2.4.6.6
DISPC Progressive-to-Interlaced Format Conversion
13.2.4.6.7
DISPC Arbitration
13.2.4.6.8
DISPC DMA Power Modes
13.2.4.6.8.1
DISPC DMA Low-Power Mode
13.2.4.6.8.2
DISPC DMA Ultralow-Power Mode
13.2.4.7
DISPC Rotation and Mirroring
13.2.4.8
DISPC Memory Format
13.2.4.9
DISPC Graphics Pipeline
13.2.4.9.1
DISPC Replication Logic
13.2.4.9.2
DISPC Antiflicker Filter
13.2.4.10
DISPC Video Pipelines
13.2.4.10.1
DISPC Replication Logic
13.2.4.10.2
DISPC VC-1 Range Mapping Unit
13.2.4.10.3
DISPC CSC Unit YUV to RGB
13.2.4.10.3.1
DISPC Chrominance Resampling
13.2.4.10.4
DISPC Scaler Unit
13.2.4.10.4.1
DISPC Scaling Algorithms
13.2.4.10.4.2
DISPC Scaling limitations
13.2.4.11
DISPC Write-Back Pipeline
13.2.4.11.1
DISPC Write-Back CSC Unit RGB to YUV
13.2.4.11.2
DISPC Write-Back Scaler Unit
13.2.4.11.3
DISPC Write-Back RGB Truncation Logic
13.2.4.12
DISPC Hardware Cursor
13.2.4.13
DISPC LCD Outputs
13.2.4.13.1
DISPC Overlay Manager
13.2.4.13.1.1
DISPC Priority Rule
13.2.4.13.1.2
DISPC Alpha Blender
13.2.4.13.1.3
DISPC Transparency Color Keys
13.2.4.13.1.4
DISPC Overlay Optimization
13.2.4.13.2
DISPC Gamma Correction Unit
13.2.4.13.3
DISPC Color Phase Rotation Unit
13.2.4.13.4
DISPC Color Space Conversion
13.2.4.13.5
DISPC BT.656 and BT.1120 Modes
13.2.4.13.5.1
Blanking
13.2.4.13.5.2
EAV and SAV
13.2.4.13.6
DISPC Active Matrix
13.2.4.13.6.1
DISPC Spatial/Temporal Dithering
13.2.4.13.6.2
DISPC Multiple Cycle Output Format (TDM)
13.2.4.13.7
DISPC Synchronized Buffer Update
13.2.4.13.8
DISPC Timing Generator and Panel Settings
13.2.4.14
DISPC TV Output
13.2.4.14.1
DISPC Overlay Manager
13.2.4.14.2
DISPC Gamma Correction Unit
13.2.4.14.3
DISPC Synchronized Buffer Update
13.2.4.14.4
DISPC Timing and TV Format Settings
13.2.4.15
DISPC Frame Width Considerations
13.2.4.16
DISPC Extended 3D Support
13.2.4.16.1
DISPC Extended 3D Support - Line Alternative Format
13.2.4.16.2
2627
13.2.4.16.3
DISPC Extended 3D Support - Frame Packing Format Format
13.2.4.16.4
DISPC Extended 3D Support - DLP 3D Format
13.2.4.17
DISPC Shadow Registers
13.2.5
DISPC Programming Guide
13.2.5.1
DISPC Low-Level Programming Models
13.2.5.1.1
DISPC Global Initialization
13.2.5.1.1.1
DISPC Surrounding Modules Global Initialization
13.2.5.1.2
DISPC Operational Modes Configuration
13.2.5.1.2.1
DISPC DMA Configuration
13.2.5.1.2.1.1
DISPC Main Sequence – DISPC DMA Channel Configuration
13.2.5.1.2.2
DISPC GFX Pipeline Configuration
13.2.5.1.2.2.1
DISPC Main Sequence – Configure the GFX Pipeline
13.2.5.1.2.2.2
DISPC Subsequence – Configure the GFX Window
13.2.5.1.2.2.3
DISPC Subsequence – Configure the GFX Pipeline Processing
13.2.5.1.2.2.4
DISPC Subsequence – Configure the GFX Pipeline Layer Output
13.2.5.1.2.3
DISPC Video Pipeline Configuration
13.2.5.1.2.3.1
DISPC Main Sequence – Configure the Video Pipeline
13.2.5.1.2.3.2
DISPC Subsequence – Configure the Video Window
13.2.5.1.2.3.3
DISPC Subsequence – Configure the Video Pipeline Processing
13.2.5.1.2.3.4
DISPC Subsequence – Configure the VC-1 Range Mapping
13.2.5.1.2.3.5
DISPC Subsequence – Configure the Video Color Space Conversion
13.2.5.1.2.3.6
DISPC Subsequence – Configure the Video Scaler Unit
13.2.5.1.2.3.7
DISPC Subsequence – Configure the Video Pipeline Layer Output
13.2.5.1.2.4
DISPC WB Pipeline Configuration
13.2.5.1.2.4.1
DISPC Main Sequence – Configure the WB Pipeline
13.2.5.1.2.4.2
DISPC Subsequence – Configure the Capture Window
13.2.5.1.2.4.3
DISPC Subsequence – Configure the WB Scaler Unit
13.2.5.1.2.4.4
DISPC Subsequence – Configure the WB Color Space Conversion Unit
13.2.5.1.2.5
DISPC LCD Output Configuration
13.2.5.1.2.5.1
DISPC Main Sequence – Configure the LCD Output
13.2.5.1.2.5.2
DISPC Subsequence – Configure the Overlay Manager
13.2.5.1.2.5.3
DISPC Subsequence – Configure the Gamma Table for Gamma Correction
13.2.5.1.2.5.4
DISPC Subsequence – Configure the Color Phase Rotation
13.2.5.1.2.5.5
DISPC Subsequence – Configure the LCD Panel Timings and Parameters
13.2.5.1.2.5.6
DISPC Subsequence – Configure BT.656 or BT.1120 Mode
13.2.5.1.2.6
DISPC TV Output Configuration
13.2.5.1.2.6.1
DISPC Main Sequence – Configure the TV Output
13.2.5.1.2.6.1.1
DISPC Subsequence – Configure the TV Overlay Manager
13.2.5.1.2.6.1.2
DISPC Subsequence – Configure the Gamma Table for Gamma Correction
13.2.5.1.2.6.1.3
DISPC Subsequence – Configure the TV Panel Timings and Parameters
13.2.6
DISPC Register Manual
13.2.6.1
DISPC Instance Summary
13.2.6.2
DISPC Logical Register Mapping
13.2.6.3
DISPC Registers
13.2.6.3.1
DISPC Register Summary
13.2.6.3.2
DISPC Register Description
13.3
High-Definition Multimedia Interface
13.3.1
HDMI Overview
13.3.1.1
HDMI Main Features
13.3.1.2
HDMI Video Formats and Timings
13.3.1.2.1
HDMI CEA-861-D Video Formats and Timings
13.3.1.2.2
VESA DMT Video Formats and Timings
14
3D Graphics Accelerator
14.1
GPU Overview
14.1.1
GPU Features Overview
14.1.2
Graphics Feature Overview
14.2
GPU Integration
14.3
GPU Functional Description
14.3.1
GPU Block Diagram
14.3.2
GPU Clock Configuration
14.3.3
GPU Software Reset
14.3.4
GPU Power Management
14.3.5
GPU Thermal Management
14.3.6
GPU Interrupt Requests
14.4
GPU Register Manual
14.4.1
GPU Instance Summary
14.4.2
GPU Registers
14.4.2.1
GPU_WRAPPER Register Summary
14.4.2.2
GPU_WRAPPER Register Description
15
2D Graphics Accelerator
15.1
BB2D Overview
15.1.1
BB2D Key Features Overview
15.2
BB2D Integration
15.3
BB2D Functional Description
15.3.1
BB2D Block Diagram
15.3.2
BB2D Clock Configuration
15.3.3
BB2D Software Reset
15.3.4
BB2D Power Management
15.4
BB2D Register Manual
15.4.1
BB2D Instance Summary
15.4.2
BB2D Registers
15.4.2.1
BB2D Register Summary
15.4.2.2
BB2D Register Description
16
Interconnect
16.1
Interconnect Overview
16.1.1
Terminology
16.1.2
Architecture Overview
16.2
L3_MAIN Interconnect
16.2.1
L3_MAIN Interconnect Overview
16.2.2
L3_MAIN Interconnect Integration
16.2.3
L3_MAIN Interconnect Functional Description
16.2.3.1
Module Use in L3_MAIN Interconnect
16.2.3.2
Module Distribution
16.2.3.2.1
L3_MAIN Interconnect Agents
16.2.3.2.2
L3_MAIN Connectivity Matrix
16.2.3.2.2.1
Clock Domain Mapping of the L3_MAIN Interconnect Modules
16.2.3.2.2.2
2724
16.2.3.2.3
Master NIU Identification
16.2.3.3
Bandwidth Regulators
16.2.3.4
Bandwidth Limiters
16.2.3.5
Flag Muxing
16.2.3.5.1
Flag Mux Time-out
16.2.3.6
Statistic Collectors Group
16.2.3.7
L3_MAIN Protection and Firewalls
16.2.3.7.1
L3_MAIN Firewall Reset
16.2.3.7.1.1
L3_MAIN Firewall – Exported Reset Values
16.2.3.7.2
Power Management
16.2.3.7.3
L3_MAIN Firewall Functionality
16.2.3.7.3.1
Protection Regions
16.2.3.7.3.2
L3_MAIN Firewall Registers Overview
16.2.3.7.3.3
Protection Mechanism per Region Examples
16.2.3.7.3.4
L3_MAIN Firewall Error Logging
16.2.3.7.3.5
L3_MAIN Firewall Default Configuration
16.2.3.8
L3_MAIN Interconnect Error Handling
16.2.3.8.1
Global Error-Routing Scheme
16.2.3.8.2
Slave NIU Error Logging
16.2.3.8.3
Flag Mux Error Logging
16.2.3.8.4
Severity Level of Standard and Custom Errors
16.2.3.8.5
Example for Decoding Standard/Custom Errors Logged in L3_MAIN
16.2.4
L3_MAIN Interconnect Programming Guide
16.2.4.1
L3 _MAIN Interconnect Low-Level Programming Models
16.2.4.1.1
Global Initialization
16.2.4.1.1.1
Global Initialization of Surrounding Modules
16.2.4.2
Operational Modes Configuration
16.2.4.2.1
L3_MAIN Interconnect Error Analysis Mode
16.2.4.2.1.1
Main Sequence: L3_MAIN Interconnect Error Analysis Mode
16.2.4.2.1.1.1
Subsequence: L3_MAIN Custom Error Identification
16.2.4.2.1.1.2
Subsequence: L3_MAIN Interconnect Protection Violation Error Identification
16.2.4.2.1.1.3
Subsequence: L3_MAIN Interconnect Standard Error Identification
16.2.4.2.1.1.4
Subsequence: L3_MAIN Interconnect FLAGMUX Configuration
16.2.5
L3_MAIN Interconnect Register Manual
16.2.5.1
L3_MAIN Register Group Summary
16.2.5.1.1
L3_MAIN Firewall Registers Summary and Description
16.2.5.1.1.1
L3_MAIN Firewall Registers Summary
16.2.5.1.1.2
L3_MAIN Firewall Registers Description
16.2.5.1.2
L3_MAIN Host Register Summary and Description
16.2.5.1.2.1
L3_MAIN HOST Register Summary
16.2.5.1.2.2
L3_MAIN HOST Register Description
16.2.5.1.3
L3_MAIN TARG Register Summary and Description
16.2.5.1.3.1
L3_MAIN TARG Register Summary
16.2.5.1.3.2
L3_MAIN TARG Register Description
16.2.5.1.4
L3_MAIN FLAGMUX Registers Summary and Description
16.2.5.1.4.1
L3_MAIN FLAGMUX Registers Summary
16.2.5.1.4.2
L3_MAIN FLAGMUX Rebisters Description
16.2.5.1.5
L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description
16.2.5.1.5.1
L3_MAIN FLAGMUX CLK1MERGE Registers Summary
16.2.5.1.5.2
L3_MAIN FLAGMUX CLK1MERGE Registers Description
16.2.5.1.6
L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description
16.2.5.1.6.1
L3_MAIN FLAGMUX TIMEOUT Registers Summary
16.2.5.1.6.2
L3_MAIN FLAGMUX TIMEOUT Registers Description
16.2.5.1.7
L3_MAIN BW Regulator Register Summary and Description
16.2.5.1.7.1
L3_MAIN BW_REGULATOR Register Summary
16.2.5.1.7.2
L3_MAIN BW_REGULATOR Register Description
16.2.5.1.8
L3_MAIN Bandwidth Limiter Register Summary and Description
16.2.5.1.8.1
L3_MAIN BW Limiter Register Summary
16.2.5.1.8.2
L3_MAIN BW Limiter Register Description
16.2.5.1.9
L3_MAIN STATCOLL Register Summary and Description
16.2.5.1.9.1
L3_MAIN STATCOLL Register Summary
16.2.5.1.9.2
L3_MAIN STATCOLL Register Description
16.3
L4 Interconnects
16.3.1
L4 Interconnect Overview
16.3.2
L4 Interconnect Integration
16.3.3
L4 Interconnect Functional Description
16.3.3.1
Module Distribution
16.3.3.1.1
L4_PER1 Interconnect Agents
16.3.3.1.2
L4_PER2 Interconnect Agents
16.3.3.1.3
L4_PER3 Interconnect Agents
16.3.3.1.4
L4_CFG Interconnect Agents
16.3.3.1.5
L4_WKUP Interconnect Agents
16.3.3.2
Power Management
16.3.3.3
L4 Firewalls
16.3.3.3.1
Protection Group
16.3.3.3.2
Segments and Regions
16.3.3.3.3
L4 Firewall Address and Protection Register Settings
16.3.3.4
L4 Error Detection and Reporting
16.3.3.4.1
IA and TA Error Detection and Logging
16.3.3.4.2
Time-Out
16.3.3.4.3
Error Reporting
16.3.3.4.4
Error Recovery
16.3.3.4.5
Firewall Error Logging in the Control Module
16.3.4
L4 Interconnect Programming Guide
16.3.4.1
L4 Interconnect Low-level Programming Models
16.3.4.1.1
Global Initialization
16.3.4.1.1.1
Surrounding Modules Global Initialization
16.3.4.1.2
Operational Modes Configuration
16.3.4.1.2.1
L4 Interconnect Error Analysis Mode
16.3.4.1.2.1.1
Main Sequence: L4 Interconnect Error Analysis Mode
16.3.4.1.2.1.2
Subsequence: L4 Interconnect Protection Violation Error Identification
16.3.4.1.2.1.3
Subsequence: L4 Interconnect Unsupported Command/Address Hole Error Identification
16.3.4.1.2.1.4
Subsequence: L4 Interconnect Reset TA and Module
16.3.4.1.2.2
L4 Interconnect Time-Out Configuration Mode
16.3.4.1.2.2.1
Main Sequence: L4 Interconnect Time-Out Configuration Mode
16.3.4.1.2.3
L4 Interconnect Firewall Configuration Mode
16.3.4.1.2.3.1
Main Sequence: L4 Interconnect Firewall Configuration Mode
16.3.5
L4 Interconnects Register Manual
16.3.5.1
L4 Interconnects Instance Summary
16.3.5.2
L4 Initiator Agent (L4 IA)
16.3.5.2.1
L4 Initiator Agent (L4 IA) Register Summary
16.3.5.2.2
L4 Initiator Agent (L4 IA) Register Description
16.3.5.3
L4 Target Agent (L4 TA)
16.3.5.3.1
L4 Target Agent (L4 TA) Register Summary
16.3.5.3.2
L4 Target Agent (L4 TA) Register Description
16.3.5.4
L4 Link Agent (L4 LA)
16.3.5.4.1
L4 Link Agent (L4 LA) Register Summary
16.3.5.4.2
L4 Link Agent (L4 LA) Register Description
16.3.5.5
L4 Address Protection (L4 AP)
16.3.5.5.1
L4 Address Protection (L4 AP) Register Summary
16.3.5.5.2
L4 Address Protection (L4 AP) Register Description
17
Memory Subsystem
17.1
Memory Subsystem Overview
17.1.1
DMM Overview
17.1.2
TILER Overview
17.1.3
EMIF Overview
17.1.4
GPMC Overview
17.1.5
ELM Overview
17.1.6
OCM Overview
17.2
Dynamic Memory Manager
17.2.1
DMM Overview
17.2.2
DMM Integration
17.2.2.1
DMM Configuration
17.2.3
DMM Functional Description
17.2.3.1
DMM Block Diagram
17.2.3.2
DMM Clock Configuration
17.2.3.3
DMM Power Management
17.2.3.4
DMM Interrupt Requests
17.2.3.5
DMM
17.2.3.5.1
DMM Concepts
17.2.3.5.1.1
Dynamic Mapping
17.2.3.5.1.2
Address Mapping
17.2.3.5.1.3
Address Translation
17.2.3.5.1.3.1
PAT View Mappings
17.2.3.5.1.3.2
PAT View Map Base Address
17.2.3.5.1.3.3
PAT Views
17.2.3.5.1.3.3.1
PAT Direct Access Translation
17.2.3.5.1.3.3.2
PAT Indirect Access Translation
17.2.3.5.1.3.3.3
PAT View Configuration
17.2.3.5.1.3.3.4
PAT Address Translation LUT
17.2.3.5.1.3.3.5
Direct Access to the PAT Table Vectors
17.2.3.5.1.3.3.6
Automatic Refill Through the Refill Engines
17.2.3.5.2
DMM Transaction Flows
17.2.3.5.2.1
Nontiled Transaction Flow
17.2.3.5.2.2
Tiled Transaction Flow
17.2.3.5.3
DMM Internal Macro-Architecture
17.2.3.5.3.1
LISA Description
17.2.3.5.3.2
PAT Description
17.2.3.5.3.3
PEG Description
17.2.3.5.3.4
LISA Interconnect Arbitration
17.2.3.5.3.5
ROBIN Description
17.2.3.5.3.6
TILER Description
17.2.3.6
TILER
17.2.3.6.1
TILER Concepts
17.2.3.6.1.1
TILER Rationale
17.2.3.6.1.1.1
The TILER is a 4-GiB Virtual Address Space Composed of Eight Views
17.2.3.6.1.1.2
A View is a 512-MiB Virtual Address Space Composed of Four Containers
17.2.3.6.1.1.3
A Container is a 128-MiB Virtual Address Space
17.2.3.6.1.1.4
A Page is a 4-kiB Virtual Address Space
17.2.3.6.1.1.5
A Tile is a 1-kiB Address Space
17.2.3.6.1.1.6
2885
17.2.3.6.1.1.7
A Subtile is a 128-Bit Address Space
17.2.3.6.1.2
TILER Modes
17.2.3.6.1.2.1
Bypass Mode
17.2.3.6.1.2.2
Page Mode
17.2.3.6.1.2.3
Tiled Mode
17.2.3.6.1.3
Object Container Definition
17.2.3.6.1.4
Page Definition
17.2.3.6.1.4.1
Container Geometry With 4-kiB Pages
17.2.3.6.1.4.2
Container Geometry and Page Mapping Summary
17.2.3.6.1.5
Orientation
17.2.3.6.1.6
Tile Definition
17.2.3.6.1.7
Subtiles
17.2.3.6.1.7.1
Subtiling Definition
17.2.3.6.1.8
TILER Virtual Addressing
17.2.3.6.1.8.1
Page Mode Virtual Addressing and Characteristics
17.2.3.6.1.8.2
Tiled Mode Virtual Addressing and Characteristics
17.2.3.6.1.8.3
Element Ordering in the TILER Container
17.2.3.6.1.8.3.1
Natural View or 0-Degree View (Orientation 0)
17.2.3.6.1.8.3.2
0-Degree View With Vertical Mirror or 180-Degree View With Horizontal Mirror (Orientation 1)
17.2.3.6.1.8.3.3
0-Degree View With Horizontal Mirror or 180-Degree View With Vertical Mirror (Orientation 2)
17.2.3.6.1.8.3.4
180-Degree View (Orientation 3)
17.2.3.6.1.8.3.5
90-Degree View With Vertical Mirror or 270-Degree View With Horizontal Mirror (Orientation 4)
17.2.3.6.1.8.3.6
270-Degree View (Orientation 5)
17.2.3.6.1.8.3.7
90-Degree View (Orientation 6)
17.2.3.6.1.8.3.8
90-Degree View With Horizontal Mirror or 270-Degree View With Vertical Mirror (Orientation 7)
17.2.3.6.2
TILER Macro-Architecture
17.2.3.6.3
TILER Guidelines for Initiators
17.2.3.6.3.1
Buffered Raster-Based Initiators
17.2.3.6.3.1.1
Buffer Size
17.2.3.6.3.1.2
Performance
17.2.4
DMM Use Cases and Tips
17.2.4.1
PAT Use Cases
17.2.4.1.1
Simple Manual Area Refill
17.2.4.1.2
Single Auto-Configured Area Refill
17.2.4.1.3
Chained Auto-Configured Area Refill
17.2.4.1.4
Synchronized Auto-Configured Area Refill
17.2.4.1.5
Cyclic Synchronized Auto-Configured Area Refill
17.2.4.2
Addressing Management with LISA
17.2.4.2.1
Case 1: Use of One Memory Controller
17.2.4.2.2
Case 2: Use of Two Memory Controllers
17.2.4.2.2.1
Address Upper Bits Shifting
17.2.5
DMM Basic Programming Model
17.2.5.1
Global Initialization
17.2.5.2
DMM Module Global Initialization
17.2.5.3
DMM Operational Modes Configuration
17.2.5.3.1
Different Operational Modes
17.2.5.3.2
Configuration Settings and LUT Refill
17.2.5.3.3
Interleaving Settings
17.2.5.3.4
Aliased Tiled View Orientation Settings and LUT Refill
17.2.5.3.5
Priority Settings
17.2.5.3.6
Error Handling
17.2.5.3.7
PAT Programming Model
17.2.5.3.7.1
PAT in Direct Translation Mode
17.2.5.3.7.2
PAT in Indirect Translation Mode
17.2.5.4
Addressing an Object in Tiled Mode
17.2.5.4.1
Frame-Buffer Addressing
17.2.5.4.2
TILER Page Mapping
17.2.5.5
Addressing an Object in Page Mode
17.2.5.6
Sharing Containers Between Different Modes
17.2.6
DMM Register Manual
17.2.6.1
DMM Instance Summary
17.2.6.2
DMM Registers
17.2.6.2.1
DMM Register Summary
17.2.6.2.2
DMM Register Description
17.3
EMIF Controller
17.3.1
EMIF Controller Overview
17.3.2
EMIF Module Environment
17.3.3
EMIF Module Integration
17.3.4
EMIF Functional Description
17.3.4.1
Block Diagram
17.3.4.1.1
Local Interface
17.3.4.1.2
FIFO Description
17.3.4.1.3
MPU Port Restrictions
17.3.4.1.4
Arbitration of Commands in the Command FIFO
17.3.4.2
Clock Management
17.3.4.2.1
EMIF_FICLK Overview
17.3.4.2.2
EMIF Dependency on MPU Clock Rate
17.3.4.3
Reset
17.3.4.4
System Power Management
17.3.4.4.1
Power-Down Mode
17.3.4.4.2
Self-Refresh Mode
17.3.4.5
Interrupt Requests
17.3.4.6
SDRAM Refresh Scheduling
17.3.4.7
SDRAM Initialization
17.3.4.7.1
DDR2 SDRAM Initialization
17.3.4.7.2
DDR3 SDRAM Initialization
17.3.4.8
DDR3 Read-Write Leveling
17.3.4.8.1
Full Leveling
17.3.4.8.2
Software Leveling
17.3.4.9
EMIF Access Cycles
17.3.4.10
Turnaround Time
17.3.4.11
PHY DLL Calibration
17.3.4.12
SDRAM Address Mapping
17.3.4.12.1
Address Mapping for IBANK_POS = 0 and EBANK_POS = 0
17.3.4.12.2
Address Mapping for IBANK_POS = 1 and EBANK_POS = 0
17.3.4.12.3
Address Mapping for IBANK_POS = 2 and EBANK_POS = 0
17.3.4.12.4
Address Mapping for IBANK_POS = 3 and EBANK_POS = 0
17.3.4.12.5
Address Mapping for IBANK_POS = 0 and EBANK_POS = 1
17.3.4.12.6
Address Mapping for IBANK_POS = 1 and EBANK_POS = 1
17.3.4.12.7
Address Mapping for IBANK_POS = 2 and EBANK_POS = 1
17.3.4.12.8
2986
17.3.4.12.9
Address Mapping for IBANK_POS = 3 and EBANK_POS = 1
17.3.4.13
DDR3 Output Impedance Calibration
17.3.4.14
Error Correction And Detection Feature
17.3.4.14.1
Read-Modify-Write Module
17.3.4.15
Class of Service
17.3.4.16
Performance Counters
17.3.4.16.1
Performance Counters General Examples
17.3.4.17
Forcing CKE to tri-state
17.3.5
EMIF Programming Guide
17.3.5.1
EMIF Low-Level Programming Models
17.3.5.1.1
Global Initialization
17.3.5.1.1.1
EMIF Configuration Sequence
17.3.5.1.2
Operational Modes Configuration
17.3.5.1.2.1
EMIF Output Impedance Calibration Mode
17.3.5.1.2.2
EMIF SDRAM Self-Refresh
17.3.5.1.2.3
EMIF SDRAM Power-Down Mode
17.3.5.1.2.4
EMIF ECC Configuration
17.3.6
EMIF Register Manual
17.3.6.1
EMIF Instance Summary
17.3.6.2
EMIF Registers
17.3.6.2.1
EMIF Register Summary
17.3.6.2.2
EMIF Register Description
17.4
General-Purpose Memory Controller
17.4.1
GPMC Overview
17.4.2
GPMC Environment
17.4.2.1
GPMC Modes
17.4.2.2
GPMC Signals
17.4.3
GPMC Integration
17.4.4
GPMC Functional Description
17.4.4.1
GPMC Block Diagram
17.4.4.2
GPMC Clock Configuration
17.4.4.3
GPMC Software Reset
17.4.4.4
GPMC Power Management
17.4.4.5
GPMC Interrupt Requests
17.4.4.6
L3 Interconnect Interface
17.4.4.7
GPMC Address and Data Bus
17.4.4.7.1
GPMC I/O Configuration Setting
17.4.4.7.2
GPMC CS0 Default Configuration at Device Reset
17.4.4.8
Address Decoder and Chip-Select Configuration
17.4.4.8.1
Chip-Select Base Address and Region Size
17.4.4.8.2
Access Protocol
17.4.4.8.2.1
Supported Devices
17.4.4.8.2.2
Access Size Adaptation and Device Width
17.4.4.8.2.3
Address/Data-Multiplexing Interface
17.4.4.8.3
External Signals
17.4.4.8.3.1
Wait Pin Monitoring Control
17.4.4.8.3.1.1
Wait Monitoring During Asynchronous Read Access
17.4.4.8.3.1.2
Wait Monitoring During Asynchronous Write Access
17.4.4.8.3.1.3
Wait Monitoring During Synchronous Read Access
17.4.4.8.3.1.4
Wait Monitoring During Synchronous Write Access
17.4.4.8.3.1.5
Wait With NAND Device
17.4.4.8.3.1.6
Idle Cycle Control Between Successive Accesses
17.4.4.8.3.1.6.1
Bus Turnaround (BUSTURNAROUND)
17.4.4.8.3.1.6.2
Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
17.4.4.8.3.1.6.3
Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
17.4.4.8.3.1.7
Slow Device Support (TIMEPARAGRANULARITY Parameter)
17.4.4.8.3.2
Reset
17.4.4.8.3.3
Byte Enable (nBE1/nBE0)
17.4.4.8.4
Error Handling
17.4.4.9
Timing Setting
17.4.4.9.1
Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
17.4.4.9.2
nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
17.4.4.9.3
nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
17.4.4.9.4
nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
17.4.4.9.5
nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
17.4.4.9.6
GPMC_CLK
17.4.4.9.7
GPMC_CLK and Control Signals Setup and Hold
17.4.4.9.8
Access Time (RDACCESSTIME / WRACCESSTIME)
17.4.4.9.8.1
Access Time on Read Access
17.4.4.9.8.2
Access Time on Write Access
17.4.4.9.9
Page Burst Access Time (PAGEBURSTACCESSTIME)
17.4.4.9.9.1
Page Burst Access Time on Read Access
17.4.4.9.9.2
Page Burst Access Time on Write Access
17.4.4.9.10
Bus Keeping Support
17.4.4.10
NOR Access Description
17.4.4.10.1
Asynchronous Access Description
17.4.4.10.1.1
Access on Address/Data Multiplexed Devices
17.4.4.10.1.1.1
Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
17.4.4.10.1.1.2
Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
17.4.4.10.1.1.3
Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
17.4.4.10.1.2
Access on Address/Address/Data-Multiplexed Devices
17.4.4.10.1.2.1
Asynchronous Single Read Operation on an AAD-Multiplexed Device
17.4.4.10.1.2.2
Asynchronous Single-Write Operation on an AAD-Multiplexed Device
17.4.4.10.1.2.3
Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
17.4.4.10.2
Synchronous Access Description
17.4.4.10.2.1
Synchronous Single Read
17.4.4.10.2.2
Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
17.4.4.10.2.3
Synchronous Single Write
17.4.4.10.2.4
Synchronous Multiple (Burst) Write
17.4.4.10.3
Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
17.4.4.10.3.1
Asynchronous Single-Read Operation on Nonmultiplexed Device
17.4.4.10.3.2
Asynchronous Single-Write Operation on Nonmultiplexed Device
17.4.4.10.3.3
Asynchronous Multiple (Page Mode) Read Operation on Nonmultiplexed Device
17.4.4.10.3.4
Synchronous Operations on a Nonmultiplexed Device
17.4.4.10.4
Page and Burst Support
17.4.4.10.5
System Burst vs External Device Burst Support
17.4.4.11
pSRAM Access Specificities
17.4.4.12
NAND Access Description
17.4.4.12.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
17.4.4.12.1.1
Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
17.4.4.12.1.2
NAND Device Command and Address Phase Control
17.4.4.12.1.3
Command Latch Cycle
17.4.4.12.1.4
Address Latch Cycle
17.4.4.12.1.5
NAND Device Data Read and Write Phase Control in Stream Mode
17.4.4.12.1.6
NAND Device General Chip-Select Timing Control Requirement
17.4.4.12.1.7
Read and Write Access Size Adaptation
17.4.4.12.1.7.1
8-Bit-Wide NAND Device
17.4.4.12.1.7.2
16-Bit-Wide NAND Device
17.4.4.12.2
NAND Device-Ready Pin
17.4.4.12.2.1
Ready Pin Monitored by Software Polling
17.4.4.12.2.2
Ready Pin Monitored by Hardware Interrupt
17.4.4.12.3
ECC Calculator
17.4.4.12.3.1
Hamming Code
17.4.4.12.3.1.1
ECC Result Register and ECC Computation Accumulation Size
17.4.4.12.3.1.2
ECC Enabling
17.4.4.12.3.1.3
ECC Computation
17.4.4.12.3.1.4
ECC Comparison and Correction
17.4.4.12.3.1.5
ECC Calculation Based on 8-Bit Word
17.4.4.12.3.1.6
ECC Calculation Based on 16-Bit Word
17.4.4.12.3.2
BCH Code
17.4.4.12.3.2.1
Requirements
17.4.4.12.3.2.2
Memory Mapping of BCH Codeword
17.4.4.12.3.2.2.1
Memory Mapping of Data Message
17.4.4.12.3.2.2.2
Memory-Mapping of the ECC
17.4.4.12.3.2.2.3
Wrapping Modes
4.4.12.3.2.2.3.1
Manual Mode (0x0)
4.4.12.3.2.2.3.2
Mode 0x1
4.4.12.3.2.2.3.3
Mode 0xA (10)
4.4.12.3.2.2.3.4
Mode 0x2
4.4.12.3.2.2.3.5
Mode 0x3
4.4.12.3.2.2.3.6
Mode 0x7
4.4.12.3.2.2.3.7
Mode 0x8
4.4.12.3.2.2.3.8
Mode 0x4
4.4.12.3.2.2.3.9
Mode 0x9
4.4.12.3.2.2.3.10
Mode 0x5
4.4.12.3.2.2.3.11
Mode 0xB (11)
4.4.12.3.2.2.3.12
Mode 0x6
17.4.4.12.3.2.3
Supported NAND Page Mappings and ECC Schemes
17.4.4.12.3.2.3.1
Per-Sector Spare Mappings
17.4.4.12.3.2.3.2
Pooled Spare Mapping
17.4.4.12.3.2.3.3
Per-Sector Spare Mapping, with ECC Separated at the End of the Page
17.4.4.12.4
Prefetch and Write-Posting Engine
17.4.4.12.4.1
General Facts About the Engine Configuration
17.4.4.12.4.2
Prefetch Mode
17.4.4.12.4.3
FIFO Control in Prefetch Mode
17.4.4.12.4.4
Write-Posting Mode
17.4.4.12.4.5
FIFO Control in Write-Posting Mode
17.4.4.12.4.6
Optimizing NAND Access Using the Prefetch and Write-Posting Engine
17.4.4.12.4.7
Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
17.4.5
GPMC Basic Programming Model
17.4.5.1
GPMC High-Level Programming Model Overview
17.4.5.2
GPMC Initialization
17.4.5.3
GPMC Configuration in NOR Mode
17.4.5.4
GPMC Configuration in NAND Mode
17.4.5.5
Set Memory Access
17.4.5.6
GPMC Timing Parameters
17.4.5.6.1
GPMC Timing Parameters Formulas
17.4.5.6.1.1
NAND Flash Interface Timing Parameters Formulas
17.4.5.6.1.2
Synchronous NOR Flash Timing Parameters Formulas
17.4.5.6.1.3
Asynchronous NOR Flash Timing Parameters Formulas
17.4.6
GPMC Use Cases and Tips
17.4.6.1
How to Set GPMC Timing Parameters for Typical Accesses
17.4.6.1.1
External Memory Attached to the GPMC Module
17.4.6.1.2
Typical GPMC Setup
17.4.6.1.2.1
GPMC Configuration for Synchronous Burst Read Access
17.4.6.1.2.2
GPMC Configuration for Asynchronous Read Access
17.4.6.1.2.3
GPMC Configuration for Asynchronous Single Write Access
17.4.6.2
How to Choose a Suitable Memory to Use With the GPMC
17.4.6.2.1
Supported Memories or Devices
17.4.6.2.1.1
Memory Pin Multiplexing
17.4.6.2.1.2
NAND Interface Protocol
17.4.6.2.1.3
NOR Interface Protocol
17.4.6.2.1.4
Other Technologies
17.4.6.2.1.5
Supported Protocols
17.4.6.2.2
GPMC Features and Settings
17.4.7
GPMC Register Manual
17.4.7.1
GPMC Register Summary
17.4.7.2
GPMC Register Descriptions
17.5
Error Location Module
17.5.1
Error Location Module Overview
17.5.2
ELM Integration
17.5.3
ELM Functional Description
17.5.3.1
ELM Software Reset
17.5.3.2
ELM Power Management
17.5.3.3
ELM Interrupt Requests
17.5.3.4
Processing Initialization
17.5.3.5
Processing Sequence
17.5.3.6
Processing Completion
17.5.4
ELM Basic Programming Model
17.5.4.1
ELM Low-Level Programming Model
17.5.4.1.1
Processing Initialization
17.5.4.1.2
Read Results
17.5.4.1.3
3179
17.5.4.2
Use Case: ELM Used in Continuous Mode
17.5.4.3
Use Case: ELM Used in Page Mode
17.5.5
ELM Register Manual
17.5.5.1
ELM Instance Summary
17.5.5.2
ELM Registers
17.5.5.2.1
ELM Register Summary
17.5.5.2.2
ELM Register Description
17.6
On-Chip Memory (OCM) Subsystem
17.6.1
OCM Subsystem Overview
17.6.2
OCM Subsystem Integration
17.6.3
OCM Subsystem Functional Desctiption
17.6.3.1
Block Diagram
17.6.3.2
Resets
17.6.3.3
Clock Management
17.6.3.4
Interrupt Requests
17.6.3.5
OCM Subsystem Memory Regions
17.6.3.6
OCM Controller Modes Of Operation
17.6.3.7
ECC Associated FIFOs
17.6.3.8
ECC Counters And Corrected Bit Distribution Register
17.6.3.9
ECC Support
17.6.3.10
Circular Buffer (CBUF) Support
17.6.3.11
CBUF Mode Error Handling
17.6.3.11.1
VBUF Address Not Mapped to a CBUF Memory Space
17.6.3.11.2
VBUF Access Not Starting At The Base Address
17.6.3.11.3
Illegal Address Change Between Two Same Type Accesses
17.6.3.11.4
Illegal Frame SIze (Short Frame Detection)
17.6.3.11.5
CBUF Overflow
17.6.3.11.6
CBUF Underflow
17.6.3.12
Status Reporting
17.6.4
OCM Subsystem Register Manual
17.6.4.1
OCM Subsystem Instance Summary
17.6.4.2
OCM Subsystem Registers
17.6.4.2.1
OCM Subsystem Register Summary
17.6.4.2.2
OCM Subsystem Register Description
18
DMA Controllers
18.1
System DMA
18.1.1
DMA_SYSTEM Module Overview
18.1.2
DMA_SYSTEM Controller Environment
18.1.3
DMA_SYSTEM Module Integration
18.1.3.1
DMA Requests to the DMA_SYSTEM Controller
18.1.3.2
Mapping of DMA Requests to DMA_CROSSBAR Inputs
18.1.4
DMA_SYSTEM Functional Description
18.1.4.1
DMA_SYSTEM Controller Power Management
18.1.4.2
DMA_SYSTEM Controller Interrupt Requests
18.1.4.2.1
Interrupt Generation
18.1.4.3
Logical Channel Transfer Overview
18.1.4.4
FIFO Queue Memory Pool
18.1.4.5
Addressing Modes
18.1.4.6
Packed Accesses
18.1.4.7
Burst Transactions
18.1.4.8
Endianism Conversion
18.1.4.9
Transfer Synchronization
18.1.4.9.1
Software Synchronization
18.1.4.9.2
Hardware Synchronization
18.1.4.10
Thread Budget Allocation
18.1.4.11
FIFO Budget Allocation
18.1.4.12
Chained Logical Channel Transfers
18.1.4.13
Reprogramming an Active Channel
18.1.4.14
Packet Synchronization
18.1.4.15
Graphics Acceleration Support
18.1.4.16
Supervisor Modes
18.1.4.17
Posted and Nonposted Writes
18.1.4.18
Disabling a Channel During Transfer
18.1.4.19
FIFO Draining Mechanism
18.1.4.20
Linked List
18.1.4.20.1
Overview
18.1.4.20.2
Link-List Transfer Profile
18.1.4.20.3
Descriptors
18.1.4.20.3.1
Type 1
18.1.4.20.3.2
Type 2
18.1.4.20.3.3
Type 3
18.1.4.20.4
Linked-List Control and Monitoring
18.1.4.20.4.1
Transfer Mode Setting
18.1.4.20.4.2
Starting a Linked List
18.1.4.20.4.3
Monitoring a Linked-List Progression
18.1.4.20.4.4
Interrupt During Linked-List Execution
18.1.4.20.4.5
Pause a Linked List
18.1.4.20.4.6
Stop a Linked List (Abort or Drain)
18.1.4.20.4.6.1
Drain
18.1.4.20.4.6.2
Abort
18.1.4.20.4.7
Status Bit Behavior
18.1.4.20.4.8
Linked-List Channel Linking
18.1.5
DMA_SYSTEM Basic Programming Model
18.1.5.1
Setup Configuration
18.1.5.2
Software-Triggered (Nonsynchronized) Transfer
18.1.5.3
Hardware-Synchronized Transfer
18.1.5.4
Synchronized Transfer Monitoring Using CDAC
18.1.5.5
Concurrent Software and Hardware Synchronization
18.1.5.6
Chained Transfer
18.1.5.7
90-Degree Clockwise Image Rotation
18.1.5.8
Graphic Operations
18.1.5.9
Linked-List Programming Guidelines
18.1.6
DMA_SYSTEM Register Manual
18.1.6.1
DMA_SYSTEM Instance Summary
18.1.6.2
DMA_SYSTEM Registers
18.1.6.2.1
DMA_SYSTEM Register Summary
18.1.6.2.2
DMA_SYSTEM Register Description
18.2
Enhanced DMA
18.2.1
EDMA Module Overview
18.2.1.1
EDMA Features
18.2.1.2
3280
18.2.1.3
EDMA Controllers Configuration
18.2.2
EDMA Controller Environment
18.2.3
EDMA Controller Integration
18.2.3.1
EDMA Requests to the EDMA Controller
18.2.4
EDMA Controller Functional Description
18.2.4.1
Block Diagram
18.2.4.1.1
Third-Party Channel Controller
18.2.4.1.2
Third-Party Transfer Controller
18.2.4.2
Types of EDMA controller Transfers
18.2.4.2.1
A-Synchronized Transfers
18.2.4.2.2
AB-Synchronized Transfers
18.2.4.3
Parameter RAM (PaRAM)
18.2.4.3.1
PaRAM
18.2.4.3.2
EDMA Channel PaRAM Set Entry Fields
18.2.4.3.2.1
Channel Options Parameter (OPT)
18.2.4.3.2.2
Channel Source Address (SRC)
18.2.4.3.2.3
Channel Destination Address (DST)
18.2.4.3.2.4
Count for 1st Dimension (ACNT)
18.2.4.3.2.5
Count for 2nd Dimension (BCNT)
18.2.4.3.2.6
Count for 3rd Dimension (CCNT)
18.2.4.3.2.7
BCNT Reload (BCNTRLD)
18.2.4.3.2.8
Source B Index (SBIDX)
18.2.4.3.2.9
Destination B Index (DBIDX)
18.2.4.3.2.10
Source C Index (SCIDX)
18.2.4.3.2.11
Destination C Index (DCIDX)
18.2.4.3.2.12
Link Address (LINK)
18.2.4.3.3
Null PaRAM Set
18.2.4.3.4
Dummy PaRAM Set
18.2.4.3.5
Dummy Versus Null Transfer Comparison
18.2.4.3.6
Parameter Set Updates
18.2.4.3.7
Linking Transfers
18.2.4.3.8
Constant Addressing Mode Transfers/Alignment Issues
18.2.4.3.9
Element Size
18.2.4.4
Initiating a DMA Transfer
18.2.4.4.1
DMA Channel
18.2.4.4.1.1
Event-Triggered Transfer Request
18.2.4.4.1.2
Manually-Triggered Transfer Request
18.2.4.4.1.3
Chain-Triggered Transfer Request
18.2.4.4.2
QDMA Channels
18.2.4.4.2.1
Auto-triggered and Link-Triggered Transfer Request
18.2.4.4.3
Comparison Between DMA and QDMA Channels
18.2.4.5
Completion of a DMA Transfer
18.2.4.5.1
Normal Completion
18.2.4.5.2
Early Completion
18.2.4.5.3
Dummy or Null Completion
18.2.4.6
Event, Channel, and PaRAM Mapping
18.2.4.6.1
DMA Channel to PaRAM Mapping
18.2.4.6.2
QDMA Channel to PaRAM Mapping
18.2.4.7
EDMA Channel Controller Regions
18.2.4.7.1
Region Overview
18.2.4.7.2
Channel Controller Regions
18.2.4.7.2.1
Resource Pool Division Across Two Regions
18.2.4.7.3
Region Interrupts
18.2.4.8
Chaining EDMA Channels
18.2.4.9
EDMA Interrupts
18.2.4.9.1
Transfer Completion Interrupts
18.2.4.9.1.1
Enabling Transfer Completion Interrupts
18.2.4.9.1.2
Clearing Transfer Completion Interrupts
18.2.4.9.2
EDMA Interrupt Servicing
18.2.4.9.3
Interrupt Servicing
18.2.4.9.4
3341
18.2.4.9.5
Interrupt Servicing
18.2.4.9.6
Interrupt Evaluation Operations
18.2.4.9.7
Error Interrupts
18.2.4.9.8
3345
18.2.4.10
Memory Protection
18.2.4.10.1
Active Memory Protection
18.2.4.10.2
Proxy Memory Protection
18.2.4.11
Event Queue(s)
18.2.4.11.1
DMA/QDMA Channel to Event Queue Mapping
18.2.4.11.2
Queue RAM Debug Visibility
18.2.4.11.3
Queue Resource Tracking
18.2.4.11.4
Performance Considerations
18.2.4.12
EDMA Transfer Controller (EDMA_TPTC)
18.2.4.12.1
Architecture Details
18.2.4.12.1.1
Command Fragmentation
18.2.4.12.1.2
TR Pipelining
18.2.4.12.1.3
Command Fragmentation (DBS = 64)
18.2.4.12.1.4
Performance Tuning
18.2.4.12.2
Memory Protection
18.2.4.12.3
Error Generation
18.2.4.12.4
Debug Features
18.2.4.12.4.1
Destination FIFO Register Pointer
18.2.4.12.5
EDMA_TPTC Configuration
18.2.4.13
Event Dataflow
18.2.4.14
EDMA controller Prioritization
18.2.4.14.1
Channel Priority
18.2.4.14.2
Trigger Source Priority
18.2.4.14.3
Dequeue Priority
18.2.4.15
EDMA Power, Reset and Clock Management
18.2.4.15.1
Clock and Power Management
18.2.4.15.2
Reset Considerations
18.2.4.16
Emulation Considerations
18.2.5
EDMA Transfer Examples
18.2.5.1
Block Move Example
18.2.5.2
Subframe Extraction Example
18.2.5.3
Data Sorting Example
18.2.5.4
Peripheral Servicing Example
18.2.5.4.1
Non-bursting Peripherals
18.2.5.4.2
Bursting Peripherals
18.2.5.4.3
Continuous Operation
18.2.5.4.3.1
Receive Channel
18.2.5.4.3.2
Transmit Channel
18.2.5.4.3.3
3384
18.2.5.4.4
Ping-Pong Buffering
18.2.5.4.4.1
Synchronization with the CPU
18.2.5.4.5
Transfer Chaining Examples
18.2.5.4.5.1
Servicing Input/Output FIFOs with a Single Event
18.2.5.4.5.2
Breaking Up Large Transfers with Intermediate Chaining
18.2.5.5
Setting Up an EDMA Transfer
18.2.5.5.1
3391
18.2.6
EDMA Debug Checklist and Programming Tips
18.2.6.1
EDMA Debug Checklist
18.2.6.2
EDMA Programming Tips
18.2.7
EDMA Register Manual
18.2.7.1
EDMA Instance Summary
18.2.7.2
EDMA Registers
18.2.7.2.1
EDMA Register Summary
18.2.7.2.2
EDMA Register Description
18.2.7.2.2.1
EDMA_TPCC Register Description
18.2.7.2.2.2
EDMA_TPTC0 and EDMA_TPTC1 Register Description
19
Interrupt Controllers
19.1
Interrupt Controllers Overview
19.2
Interrupt Controllers Environment
19.3
Interrupt Controllers Integration
19.3.1
Interrupt Requests to MPU_INTC
19.3.2
Interrupt Requests to DSP1_INTC
19.3.3
Interrupt Requests to DSP2_INTC
19.3.4
Interrupt Requests to IPU1_Cx_INTC
19.3.5
Interrupt Requests to IPU2_Cx_INTC
19.3.6
Interrupt Requests to EVE1_INTC1
19.3.7
Interrupt Requests to EVE2_INTC1
19.3.8
Mapping of Device Interrupts to IRQ_CROSSBAR Inputs
19.4
Interrupt Controllers Functional Description
20
Control Module
20.1
Control Module Overview
20.2
Control Module Environment
20.3
Control Module Integration
20.4
Control Module Functional Description
20.4.1
Control Module Clock Configuration
20.4.2
Control Module Resets
20.4.3
Control Module Power Management
20.4.3.1
Power Management Protocols
20.4.4
Hardware Requests
20.4.5
Control Module Initialization
20.4.6
Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule
20.4.6.1
Pad Configuration
20.4.6.1.1
Pad Configuration Registers
20.4.6.1.1.1
Permanent PU/PD disabling
20.4.6.1.2
Pull Selection
20.4.6.1.3
Pad multiplexing
20.4.6.1.4
IOSETs
20.4.6.1.5
Virtual IO Timing Modes
20.4.6.1.6
Manual IO Timing Modes
20.4.6.1.7
Isolation Requirements
20.4.6.1.8
IO Delay Recalibration
20.4.6.2
Thermal Management Related Registers
20.4.6.2.1
Temperature Sensors Control Registers
20.4.6.2.2
Registers For The Thermal Alert Comparators
20.4.6.2.3
Thermal Shutdown Comparators
20.4.6.2.4
Temperature Timestamp Registers
20.4.6.2.5
Other Thermal Management Related Registers
20.4.6.2.6
Summary of the Thermal Management Related Registers
20.4.6.2.7
ADC Values Versus Temperature
20.4.6.3
PBIAS Cell And MMC1 I/O Cells Control Registers
20.4.6.4
IRQ_CROSSBAR Module Functional Description
20.4.6.5
DMA_CROSSBAR Module Functional Description
20.4.6.6
SDRAM Initiator Priority Registers
20.4.6.7
L3_MAIN Initiator Priority Registers
20.4.6.8
Memory Region Lock Registers
20.4.6.9
NMI Mapping To Respective Cores
20.4.6.10
Software Controls for the DDR2/DDR3 I/O Cells
20.4.6.11
Reference Voltage for the Device DDR2/DDR3 Receivers
20.4.6.12
AVS Class 0 Associated Registers
20.4.6.13
ABB Associated Registers
20.4.6.14
Registers For Other Miscellaneous Functions
20.4.6.14.1
System Boot Status Settings
20.4.6.14.2
Force MPU Write Nonposted Transactions
20.4.6.14.3
Firewall Error Status Registers
20.4.6.14.4
Settings Related To Different Peripheral Modules
20.4.7
Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule
20.4.7.1
Registers For Basic EMIF Configuration
20.5
Control Module Register Manual
20.6
IODELAYCONFIG Module Integration
20.7
IODELAYCONFIG Module Register Manual
21
Mailbox
21.1
Mailbox Overview
21.2
Mailbox Integration
21.2.1
System MAILBOX Integration
21.2.2
IVA Mailbox Integration
21.2.3
EVE Mailbox Integration
21.3
Mailbox Functional Description
21.3.1
Mailbox Block Diagram
21.3.1.1
3474
21.3.2
Mailbox Software Reset
21.3.3
Mailbox Power Management
21.3.4
Mailbox Interrupt Requests
21.3.5
Mailbox Assignment
21.3.5.1
Description
21.3.6
Sending and Receiving Messages
21.3.6.1
Description
21.3.7
16-Bit Register Access
21.3.7.1
Description
21.3.8
Example of Communication
21.4
Mailbox Programming Guide
21.4.1
Mailbox Low-level Programming Models
21.4.1.1
Global Initialization
21.4.1.1.1
Surrounding Modules Global Initialization
21.4.1.1.2
Mailbox Global Initialization
21.4.1.1.2.1
Main Sequence - Mailbox Global Initialization
21.4.1.2
Mailbox Operational Modes Configuration
21.4.1.2.1
Mailbox Processing modes
21.4.1.2.1.1
Main Sequence - Sending a Message (Polling Method)
21.4.1.2.1.2
Main Sequence - Sending a Message (Interrupt Method)
21.4.1.2.1.3
Main Sequence - Receiving a Message (Polling Method)
21.4.1.2.1.4
Main Sequence - Receiving a Message (Interrupt Method)
21.4.1.3
Mailbox Events Servicing
21.4.1.3.1
Events Servicing in Sending Mode
21.4.1.3.2
Events Servicing in Receiving Mode
21.5
Mailbox Register Manual
21.5.1
Mailbox Instance Summary
21.5.2
Mailbox Registers
21.5.2.1
Mailbox Register Summary
21.5.2.2
Mailbox Register Description
22
Memory Management Units
22.1
MMU Overview
22.2
MMU Integration
22.3
MMU Functional Description
22.3.1
MMU Block Diagram
22.3.1.1
MMU Address Translation Process
22.3.1.2
Translation Tables
22.3.1.2.1
Translation Table Hierarchy
22.3.1.2.2
First-Level Translation Table
22.3.1.2.2.1
First-Level Descriptor Format
22.3.1.2.2.2
First-Level Page Descriptor Format
22.3.1.2.2.3
First-Level Section Descriptor Format
22.3.1.2.2.4
Section Translation Summary
22.3.1.2.2.5
Supersection Translation Summary
22.3.1.2.3
Two-Level Translation
22.3.1.2.3.1
Second-Level Descriptor Format
22.3.1.2.3.2
Small Page Translation Summary
22.3.1.2.3.3
Large Page Translation Summary
22.3.1.3
Translation Lookaside Buffer
22.3.1.3.1
TLB Entry Format
22.3.1.4
No Translation (Bypass) Regions
22.3.2
MMU Software Reset
22.3.3
MMU Power Management
22.3.4
MMU Interrupt Requests
22.3.5
MMU Error Handling
22.4
MMU Low-level Programming Models
22.4.1
Global Initialization
22.4.1.1
Surrounding Modules Global Initialization
22.4.1.2
MMU Global Initialization
22.4.1.2.1
Main Sequence - MMU Global Initialization
22.4.1.2.2
Subsequence - Configure a TLB entry
22.4.1.3
Operational Modes Configuration
22.4.1.3.1
Main Sequence - Writing TLB Entries Statically
22.4.1.3.2
Main Sequence - Protecting TLB Entries
22.4.1.3.3
Main Sequence - Deleting TLB Entries
22.4.1.3.4
Main Sequence - Read TLB Entries
22.5
MMU Register Manual
22.5.1
MMU Instance Summary
22.5.2
MMU Registers
22.5.2.1
MMU Register Summary
22.5.2.2
MMU Register Description
23
Spinlock
23.1
Spinlock Overview
23.2
Spinlock Integration
23.3
Spinlock Functional Description
23.3.1
Spinlock Software Reset
23.3.2
Spinlock Power Management
23.3.3
About Spinlocks
23.3.4
Spinlock Functional Operation
23.4
Spinlock Programming Guide
23.4.1
Spinlock Low-level Programming Models
23.4.1.1
Surrounding Modules Global Initialization
23.4.1.2
Basic Spinlock Operations
23.4.1.2.1
Spinlocks Clearing After a System Bug Recovery
23.4.1.2.2
Take and Release Spinlock
23.5
Spinlock Register Manual
23.5.1
Spinlock Instance Summary
23.5.2
Spinlock Registers
23.5.2.1
Spinlock Register Summary
23.5.2.2
Spinlock Register Description
24
Timers
24.1
Timers Overview
24.2
General-Purpose Timers
24.2.1
General-Purpose Timers Overview
24.2.1.1
GP Timer Features
24.2.2
GP Timer Environment
24.2.2.1
GP Timer External System Interface
24.2.3
GP Timer Integration
24.2.4
GP Timer Functional Description
24.2.4.1
GP Timer Block Diagram
24.2.4.2
TIMER1, TIMER2 and TIMER10 Power Management
24.2.4.2.1
Wake-Up Capability
24.2.4.3
Power Management of Other GP Timers
24.2.4.3.1
Wake-Up Capability
24.2.4.4
Software Reset
24.2.4.5
GP Timer Interrupts
24.2.4.6
Timer Mode Functionality
24.2.4.6.1
1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10)
24.2.4.7
Capture Mode Functionality
24.2.4.8
Compare Mode Functionality
24.2.4.9
Prescaler Functionality
24.2.4.10
Pulse-Width Modulation
24.2.4.11
Timer Counting Rate
24.2.4.12
Timer Under Emulation
24.2.4.13
Accessing GP Timer Registers
24.2.4.13.1
Writing to Timer Registers
24.2.4.13.1.1
Write Posting Synchronization Mode
24.2.4.13.1.2
Write Nonposting Synchronization Mode
24.2.4.13.2
Reading From Timer Counter Registers
24.2.4.13.2.1
Read Posted
24.2.4.13.2.2
Read Non-Posted
24.2.4.14
Posted Mode Selection
24.2.5
GP Timer Low-Level Programming Models
24.2.5.1
Global Initialization
24.2.5.1.1
Global Initialization of Surrounding Modules
24.2.5.1.2
GP Timer Module Global Initialization
24.2.5.1.2.1
Main Sequence – GP Timer Module Global Initialization
24.2.5.2
Operational Mode Configuration
24.2.5.2.1
GP Timer Mode
24.2.5.2.1.1
Main Sequence – GP Timer Mode Configuration
24.2.5.2.2
GP Timer Compare Mode
24.2.5.2.2.1
Main Sequence – GP Timer Compare Mode Configuration
24.2.5.2.3
GP Timer Capture Mode
24.2.5.2.3.1
Main Sequence – GP Timer Capture Mode Configuration
24.2.5.2.3.2
Subsequence – Initialize Capture Mode
24.2.5.2.3.3
Subsequence – Detect Event
24.2.5.2.4
GP Timer PWM Mode
24.2.5.2.4.1
Main Sequence – GP Timer PWM Mode Configuration
24.2.6
GP Timer Register Manual
24.2.6.1
GP Timer Instance Summary
24.2.6.2
GP Timer Registers
24.2.6.2.1
GP Timer Register Summary
24.2.6.2.2
GP Timer Register Description
24.2.6.2.3
TIMER1, TIMER2, and TIMER10 Register Description
24.3
32-kHz Synchronized Timer (COUNTER_32K)
24.3.1
32-kHz Synchronized Timer Overview
24.3.1.1
32-kHz Synchronized Timer Features
24.3.2
32-kHz Synchronized Timer Integration
24.3.3
32-kHz Synchronized Timer Functional Description
24.3.3.1
Reading the 32-kHz Synchronized Timer
24.3.4
COUNTER_32K Timer Register Manual
24.3.4.1
COUNTER_32K Timer Register Mapping Summary
24.3.4.2
COUNTER_32K Timer Register Description
24.4
Watchdog Timer
24.4.1
Watchdog Timer Overview
24.4.1.1
Watchdog Timer Features
24.4.2
Watchdog Timer Integration
24.4.3
Watchdog Timer Functional Description
24.4.3.1
Power Management
24.4.3.1.1
Wake-Up Capability
24.4.3.2
Interrupts
24.4.3.3
General Watchdog Timer Operation
24.4.3.4
Reset Context
24.4.3.5
Overflow/Reset Generation
24.4.3.6
Prescaler Value/Timer Reset Frequency
24.4.3.7
Triggering a Timer Reload
24.4.3.8
Start/Stop Sequence for Watchdog Timer (Using the WSPR Register)
24.4.3.9
Modifying Timer Count/Load Values and Prescaler Setting
24.4.3.10
Watchdog Counter Register Access Restriction (WCRR)
24.4.3.11
Watchdog Timer Interrupt Generation
24.4.3.12
Watchdog Timer Under Emulation
24.4.3.13
Accessing Watchdog Timer Registers
24.4.4
Watchdog Timer Low-Level Programming Model
24.4.4.1
Global Initialization
24.4.4.1.1
Surrounding Modules Global Initialization
24.4.4.1.2
Watchdog Timer Module Global Initialization
24.4.4.1.2.1
Main Sequence – Watchdog Timer Module Global Initialization
24.4.4.2
Operational Mode Configuration
24.4.4.2.1
Watchdog Timer Basic Configuration
24.4.4.2.1.1
Main Sequence – Watchdog Timer Basic Configuration
24.4.4.2.1.2
Subsequence – Disable the Watchdog Timer
24.4.4.2.1.3
Subsequence – Enable the Watchdog Timer
24.4.5
Watchdog Timer Register Manual
24.4.5.1
Watchdog Timer Instance Summary
24.4.5.2
Watchdog Timer Registers
24.4.5.2.1
Watchdog Timer Register Summary
24.4.5.2.2
3661
24.4.5.2.3
Watchdog Timer Register Description
25
Real-Time Clock (RTC)
25.1
RTC Overview
25.1.1
RTC Features
25.2
RTC Environment
25.2.1
RTC External Interface
25.3
RTC Integration
25.4
RTC Functional Description
25.4.1
Clock Source
25.4.2
Interrupt Support
25.4.2.1
CPU Interrupts
25.4.2.2
Interrupt Description
25.4.2.2.1
Timer Interrupt (timer_intr)
25.4.2.2.2
Alarm Interrupt (alarm_intr)
25.4.3
RTC Programming/Usage Guide
25.4.3.1
Time/Calendar Data Format
25.4.3.2
Register Access
25.4.3.3
Register Spurious Write Protection
25.4.3.4
Reading the Timer/Calendar (TC) Registers
25.4.3.4.1
Rounding Seconds
25.4.3.5
Modifying the TC Registers
25.4.3.5.1
General Registers
25.4.3.6
Crystal Compensation
25.4.4
Scratch Registers
25.4.5
Debouncing
25.4.6
Power Management
25.4.6.1
Device-Level Power Management
25.4.6.2
Subsystem-Level Power Management — PMIC Mode
25.5
RTC Low-Level Programming Guide
25.5.1
Global Initialization
25.5.1.1
Surrounding Modules Global Initialization
25.5.1.2
RTC Module Global Initialization
25.5.1.2.1
Main Sequence – RTC Module Global Initialization
25.6
RTC Register Manual
25.6.1
RTC Instance Summary
25.6.2
RTC_SS Registers
25.6.2.1
RTC_SS Register Summary
25.6.2.2
RTC_SS Register Description
26
Serial Communication Interfaces
26.1
Multimaster High-Speed I2C Controller
26.1.1
HS I2C Overview
26.1.2
HS I2C Environment
26.1.2.1
HS I2C Typical Application
26.1.2.1.1
HS I2C Pins for Typical Connections in I2C Mode
26.1.2.1.2
HS I2C Interface Typical Connections
26.1.2.2
HS I2C Typical Connection Protocol and Data Format
26.1.2.2.1
HS I2C Serial Data Format
26.1.2.2.2
HS I2C Data Validity
26.1.2.2.3
HS I2C Start and Stop Conditions
26.1.2.2.4
HS I2C Addressing
26.1.2.2.4.1
Data Transfer Formats in F/S Mode
26.1.2.2.4.2
Data Transfer Format in HS Mode
26.1.2.2.5
HS I2C Master Transmitter
26.1.2.2.6
HS I2C Master Receiver
26.1.2.2.7
HS I2C Slave Transmitter
26.1.2.2.8
HS I2C Slave Receiver
26.1.2.2.9
HS I2C Bus Arbitration
26.1.2.2.10
HS I2C Clock Generation and Synchronization
26.1.3
HS I2C Integration
26.1.4
HS I2C Functional Description
26.1.4.1
HS I2C Block Diagram
26.1.4.2
HS I2C Clocks
26.1.4.2.1
HS I2C Clocking
26.1.4.2.2
HS I2C Automatic Blocking of the I2C Clock Feature
26.1.4.3
HS I2C Software Reset
26.1.4.4
HS I2C Power Management
26.1.4.5
HS I2C Interrupt Requests
26.1.4.6
HS I2C DMA Requests
26.1.4.7
HS I2C Programmable Multislave Channel Feature
26.1.4.8
HS I2C FIFO Management
26.1.4.8.1
HS I2C FIFO Interrupt Mode
26.1.4.8.2
HS I2C FIFO Polling Mode
26.1.4.8.3
HS I2C FIFO DMA Mode
26.1.4.8.4
HS I2C Draining Feature
26.1.4.9
HS I2C Noise Filter
26.1.4.10
HS I2C System Test Mode
26.1.5
HS I2C Programming Guide
26.1.5.1
HS I2C Low-Level Programming Models
26.1.5.1.1
HS I2C Programming Model
26.1.5.1.1.1
Main Program
26.1.5.1.1.1.1
Configure the Module Before Enabling the I2C Controller
26.1.5.1.1.1.2
Initialize the I2C Controller
26.1.5.1.1.1.3
Configure Slave Address and the Data Control Register
26.1.5.1.1.1.4
Initiate a Transfer
26.1.5.1.1.1.5
Receive Data
26.1.5.1.1.1.6
Transmit Data
26.1.5.1.1.2
Interrupt Subroutine Sequence
26.1.5.1.1.3
Programming Flow-Diagrams
26.1.6
HS I2C Register Manual
26.1.6.1
HS I2C Instance Summary
26.1.6.2
HS I2C Registers
26.1.6.2.1
HS I2C Register Summary
26.1.6.2.2
HS I2C Register Description
26.2
HDQ/1-Wire
26.2.1
HDQ1W Overview
26.2.2
HDQ1W Environment
26.2.2.1
HDQ1W Functional Modes
26.2.2.2
HDQ and 1-Wire (SDQ) Protocols
26.2.2.2.1
HDQ Protocol Initialization (Default)
26.2.2.2.2
1-Wire (SDQ) Protocol Initialization
26.2.2.2.3
Communication Sequence (HDQ and 1-Wire Protocols)
26.2.3
HDQ1W Integration
26.2.4
HDQ1W Functional Description
26.2.4.1
HDQ1W Block Diagram
26.2.4.2
HDQ1W Clocking Configuration
26.2.4.2.1
HDQ1W Clocks
26.2.4.3
HDQ1W Hardware and Software Reset
26.2.4.4
HDQ1W Power Management
26.2.4.4.1
Auto-Idle Mode
26.2.4.4.2
Power-Down Mode
26.2.4.4.3
3772
26.2.4.5
HDQ Interrupt Requests
26.2.4.6
HDQ Mode (Default)
26.2.4.6.1
HDQ Mode Features
26.2.4.6.2
Description
26.2.4.6.3
Single-Bit Mode
26.2.4.6.4
Interrupt Conditions
26.2.4.7
1-Wire Mode
26.2.4.7.1
1-Wire Mode Features
26.2.4.7.2
Description
26.2.4.7.3
1-Wire Single-Bit Mode Operation
26.2.4.7.4
Interrupt Conditions
26.2.4.7.5
Status Flags
26.2.4.8
BITFSM Delay
26.2.5
HDQ1W Low-Level Programming Model
26.2.5.1
Global Initialization
26.2.5.1.1
Surrounding Modules Global Initialization
26.2.5.1.2
HDQ1W Module Global Initialization
26.2.5.2
HDQ Operational Modes Configuration
26.2.5.2.1
Main Sequence - HDQ Write Operation Mode
26.2.5.2.2
Main Sequence - HDQ Read Operation Mode
26.2.5.2.2.1
Sub-sequence - Initialize HDQ Slave
26.2.5.3
1-Wire Operational Modes Configuration
26.2.5.3.1
Main Sequence - 1-Wire Write Operation Mode
26.2.5.3.2
Main Sequence - 1-Wire Read Operation Mode
26.2.5.3.3
Sub-sequence - Initialize 1-Wire Slave
26.2.6
HDQ1W Register Manual
26.2.6.1
HDQ1W Instance Summary
26.2.6.2
HDQ1W Registers
26.2.6.2.1
HDQ1W Register Summary
26.2.6.2.2
HDQ1W Register Description
26.3
UART/IrDA/CIR
26.3.1
UART/IrDA/CIR Overview
26.3.1.1
UART Features
26.3.1.2
IrDA Features
26.3.1.3
CIR Features
26.3.2
UART/IrDA/CIR Environment
26.3.2.1
UART Interface
26.3.2.1.1
System Using UART Communication With Hardware Handshake
26.3.2.1.2
UART Interface Description
26.3.2.1.3
UART Protocol and Data Format
26.3.2.2
IrDA Functional Interfaces
26.3.2.2.1
System Using IrDA Communication Protocol
26.3.2.2.2
IrDA Interface Description
26.3.2.2.3
IrDA Protocol and Data Format
26.3.2.2.3.1
SIR Mode
26.3.2.2.3.1.1
Frame Format
26.3.2.2.3.1.2
Asynchronous Transparency
26.3.2.2.3.1.3
Abort Sequence
26.3.2.2.3.1.4
Pulse Shaping
26.3.2.2.3.1.5
Encoder
26.3.2.2.3.1.6
Decoder
26.3.2.2.3.1.7
IR Address Checking
26.3.2.2.3.2
SIR Free-Format Mode
26.3.2.2.3.3
MIR Mode
26.3.2.2.3.3.1
MIR Encoder/Decoder
26.3.2.2.3.3.2
SIP Generation
26.3.2.2.3.4
FIR Mode
26.3.2.3
CIR Functional Interfaces
26.3.2.3.1
System Using CIR Communication Protocol With Remote Control
26.3.2.3.2
CIR Interface Description
26.3.2.3.3
CIR Protocol and Data Format
26.3.2.3.3.1
Carrier Modulation
26.3.2.3.3.2
Pulse Duty Cycle
26.3.2.3.3.3
Consumer IR Encoding/Decoding
26.3.3
UART/IrDA/CIR Integration
26.3.3.1
3838
26.3.4
UART/IrDA/CIR Functional Description
26.3.4.1
Block Diagram
26.3.4.2
Clock Configuration
26.3.4.3
Software Reset
26.3.4.4
Power Management
26.3.4.4.1
UART Mode Power Management
26.3.4.4.1.1
Module Power Saving
26.3.4.4.1.2
System Power Saving
26.3.4.4.2
IrDA Mode Power Management (UART3 Only)
26.3.4.4.2.1
Module Power Saving
26.3.4.4.2.2
System Power Saving
26.3.4.4.3
CIR Mode Power Management (UART3 Only)
26.3.4.4.3.1
Module Power Saving
26.3.4.4.3.2
System Power Saving
26.3.4.4.4
Local Power Management
26.3.4.5
Interrupt Requests
26.3.4.5.1
UART Mode Interrupt Management
26.3.4.5.1.1
UART Interrupts
26.3.4.5.1.2
Wake-Up Interrupt
26.3.4.5.2
IrDA Mode Interrupt Management
26.3.4.5.2.1
IrDA Interrupts
26.3.4.5.2.2
Wake-Up Interrupts
26.3.4.5.3
CIR Mode Interrupt Management
26.3.4.5.3.1
CIR Interrupts
26.3.4.5.3.2
Wake-Up Interrupts
26.3.4.6
FIFO Management
26.3.4.6.1
FIFO Trigger
26.3.4.6.1.1
Transmit FIFO Trigger
26.3.4.6.1.2
Receive FIFO Trigger
26.3.4.6.2
FIFO Interrupt Mode
26.3.4.6.3
FIFO Polled Mode Operation
26.3.4.6.4
FIFO DMA Mode Operation
26.3.4.6.4.1
DMA sequence to disable TX DMA
26.3.4.6.4.2
DMA Transfers (DMA Mode 1, 2, or 3)
26.3.4.6.4.3
DMA Transmission
26.3.4.6.4.4
DMA Reception
26.3.4.7
Mode Selection
26.3.4.7.1
Register Access Modes
26.3.4.7.1.1
Operational Mode and Configuration Modes
26.3.4.7.1.2
Register Access Submode
26.3.4.7.1.3
Registers Available for the Register Access Modes
26.3.4.7.2
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
26.3.4.7.2.1
Registers Available for the UART Function
26.3.4.7.2.2
Registers Available for the IrDA Function (UART3 Only)
26.3.4.7.2.3
Registers Available for the CIR Function (UART3 Only)
26.3.4.8
Protocol Formatting
26.3.4.8.1
UART Mode
26.3.4.8.1.1
UART Clock Generation: Baud Rate Generation
26.3.4.8.1.2
Choosing the Appropriate Divisor Value
26.3.4.8.1.3
UART Data Formatting
26.3.4.8.1.3.1
Frame Formatting
26.3.4.8.1.3.2
Hardware Flow Control
26.3.4.8.1.3.3
Software Flow Control
26.3.4.8.1.3.3.1
Receive (RX)
26.3.4.8.1.3.3.2
Transmit (TX)
26.3.4.8.1.3.4
Autobauding Modes
26.3.4.8.1.3.5
Error Detection
26.3.4.8.1.3.6
Overrun During Receive
26.3.4.8.1.3.7
Time-Out and Break Conditions
26.3.4.8.1.3.7.1
Time-Out Counter
26.3.4.8.1.3.7.2
Break Condition
26.3.4.8.2
IrDA Mode (UART3 Only)
26.3.4.8.2.1
IrDA Clock Generation: Baud Generator
26.3.4.8.2.2
Choosing the Appropriate Divisor Value
26.3.4.8.2.3
IrDA Data Formatting
26.3.4.8.2.3.1
IR RX Polarity Control
26.3.4.8.2.3.2
IrDA Reception Control
26.3.4.8.2.3.3
IR Address Checking
26.3.4.8.2.3.4
Frame Closing
26.3.4.8.2.3.5
Store and Controlled Transmission
26.3.4.8.2.3.6
Error Detection
26.3.4.8.2.3.7
Underrun During Transmission
26.3.4.8.2.3.8
Overrun During Receive
26.3.4.8.2.3.9
Status FIFO
26.3.4.8.2.4
SIR Mode Data Formatting
26.3.4.8.2.4.1
Abort Sequence
26.3.4.8.2.4.2
Pulse Shaping
26.3.4.8.2.4.3
SIR Free Format Programming
26.3.4.8.2.5
MIR and FIR Mode Data Formatting
26.3.4.8.3
CIR Mode (UART3 Only)
26.3.4.8.3.1
CIR Mode Clock Generation
26.3.4.8.3.2
CIR Data Formatting
26.3.4.8.3.2.1
IR RX Polarity Control
26.3.4.8.3.2.2
CIR Transmission
26.3.5
UART/IrDA/CIR Basic Programming Model
26.3.5.1
Global Initialization
26.3.5.1.1
Surrounding Modules Global Initialization
26.3.5.1.2
UART/IrDA/CIR Module Global Initialization
26.3.5.2
Mode selection
26.3.5.3
Submode selection
26.3.5.4
Load FIFO trigger and DMA mode settings
26.3.5.4.1
DMA mode Settings
26.3.5.4.2
FIFO Trigger Settings
26.3.5.5
Protocol, Baud rate and interrupt settings
26.3.5.5.1
Baud rate settings
26.3.5.5.2
Interrupt settings
26.3.5.5.3
Protocol settings
26.3.5.5.4
UART/IrDA(SIR/MIR/FIR)/CIR
26.3.5.6
Hardware and Software Flow Control Configuration
26.3.5.6.1
Hardware Flow Control Configuration
26.3.5.6.2
Software Flow Control Configuration
26.3.5.7
IrDA Programming Model (UART3 Only)
26.3.5.7.1
SIR mode
26.3.5.7.1.1
Receive
26.3.5.7.1.2
Transmit
26.3.5.7.2
MIR mode
26.3.5.7.2.1
Receive
26.3.5.7.2.2
Transmit
26.3.5.7.3
FIR mode
26.3.5.7.3.1
Receive
26.3.5.7.3.2
Transmit
26.3.6
UART/IrDA/CIR Register Manual
26.3.6.1
UART/IrDA/CIR Instance Summary
26.3.6.2
UART/IrDA/CIR Registers
26.3.6.2.1
UART/IrDA/CIR Register Summary
26.3.6.2.2
UART/IrDA/CIR Register Description
26.4
Multichannel Serial Peripheral Interface
26.4.1
McSPI Overview
26.4.2
McSPI Environment
26.4.2.1
Basic McSPI Pins for Master Mode
26.4.2.2
Basic McSPI Pins for Slave Mode
26.4.2.3
Multichannel SPI Protocol and Data Format
26.4.2.3.1
Transfer Format
26.4.2.4
SPI in Master Mode
26.4.2.5
SPI in Slave Mode
26.4.3
McSPI Integration
26.4.4
McSPI Functional Description
26.4.4.1
McSPI Block Diagram
26.4.4.2
Reset
26.4.4.3
Master Mode
26.4.4.3.1
Master Mode Features
26.4.4.3.2
Master Transmit-and-Receive Mode (Full Duplex)
26.4.4.3.3
Master Transmit-Only Mode (Half Duplex)
26.4.4.3.4
Master Receive-Only Mode (Half Duplex)
26.4.4.3.5
Single-Channel Master Mode
26.4.4.3.5.1
Programming Tips When Switching to Another Channel
26.4.4.3.5.2
Force SPIEN[x] Mode
26.4.4.3.5.3
Turbo Mode
26.4.4.3.6
Start-Bit Mode
26.4.4.3.7
Chip-Select Timing Control
26.4.4.3.8
Programmable SPI Clock
26.4.4.3.8.1
Clock Ratio Granularity
26.4.4.4
Slave Mode
26.4.4.4.1
Dedicated Resources
26.4.4.4.2
Slave Transmit-and-Receive Mode
26.4.4.4.3
Slave Transmit-Only Mode
26.4.4.4.4
Slave Receive-Only Mode
26.4.4.5
3-Pin or 4-Pin Mode
26.4.4.6
FIFO Buffer Management
26.4.4.6.1
Buffer Almost Full
26.4.4.6.2
Buffer Almost Empty
26.4.4.6.3
End of Transfer Management
26.4.4.7
Interrupts
26.4.4.7.1
Interrupt Events in Master Mode
26.4.4.7.1.1
TXx_EMPTY
26.4.4.7.1.2
TXx_UNDERFLOW
26.4.4.7.1.3
RXx_ FULL
26.4.4.7.1.4
End Of Word Count
26.4.4.7.2
Interrupt Events in Slave Mode
26.4.4.7.2.1
TXx_EMPTY
26.4.4.7.2.2
TXx_UNDERFLOW
26.4.4.7.2.3
RXx_FULL
26.4.4.7.2.4
RX0_OVERFLOW
26.4.4.7.2.5
End Of Word Count
26.4.4.7.3
Interrupt-Driven Operation
26.4.4.7.4
Polling
26.4.4.8
DMA Requests
26.4.4.9
Power Saving Management
26.4.4.9.1
Normal Mode
26.4.4.9.2
Idle Mode
26.4.4.9.2.1
Wake-Up Event in Smart-Idle Mode
26.4.4.9.2.2
Transitions From Smart-Idle Mode to Normal Mode
26.4.4.9.2.3
Force-Idle Mode
26.4.5
McSPI Programming Guide
26.4.5.1
Global Initialization
26.4.5.1.1
Surrounding Modules Global Initialization
26.4.5.1.2
McSPI Global Initialization
26.4.5.1.2.1
Main Sequence – McSPI Global Initialization
26.4.5.2
Operational Mode Configuration
26.4.5.2.1
McSPI Operational Modes
26.4.5.2.1.1
Common Transfer Sequence
26.4.5.2.1.2
End of Transfer Sequences
26.4.5.2.1.3
Transmit-and-Receive (Master and Slave)
26.4.5.2.1.4
Transmit-Only (Master and Slave)
26.4.5.2.1.4.1
Based on Interrupt Requests
26.4.5.2.1.4.2
Based on DMA Write Requests
26.4.5.2.1.5
Master Normal Receive-Only
26.4.5.2.1.5.1
Based on Interrupt Requests
26.4.5.2.1.5.2
Based on DMA Read Requests
26.4.5.2.1.6
Master Turbo Receive-Only
26.4.5.2.1.6.1
Based on Interrupt Requests
26.4.5.2.1.6.2
Based on DMA Read Requests
26.4.5.2.1.7
Slave Receive-Only
26.4.5.2.1.8
Transfer Procedures With FIFO
26.4.5.2.1.8.1
Common Transfer Sequence in FIFO Mode
26.4.5.2.1.8.2
End of Transfer Sequences in FIFO Mode
26.4.5.2.1.8.3
Transmit-and-Receive With Word Count
26.4.5.2.1.8.4
Transmit-and-Receive Without Word Count
26.4.5.2.1.8.5
Transmit-Only
26.4.5.2.1.8.6
Receive-Only With Word Count
26.4.5.2.1.8.7
Receive-Only Without Word Count
26.4.5.3
Common Transfer Procedures Without FIFO – Polling Method
26.4.5.3.1
Receive-Only Procedure – Polling Method
26.4.5.3.2
Receive-Only Procedure – Interrupt Method
26.4.5.3.3
Transmit-Only Procedure – Polling Method
26.4.5.3.4
Transmit-and-Receive Procedure – Polling Method
26.4.6
McSPI Register Manual
26.4.6.1
McSPI Instance Summary
26.4.6.2
McSPI Registers
26.4.6.2.1
McSPI Register Summary
26.4.6.2.2
McSPI Register Description
26.5
Quad Serial Peripheral Interface
26.5.1
Quad Serial Peripheral Interface Overview
26.5.2
QSPI Environment
26.5.3
QSPI Integration
26.5.4
QSPI Functional Description
26.5.4.1
QSPI Block Diagram
26.5.4.1.1
SFI Register Control
26.5.4.1.2
SFI Translator
26.5.4.1.3
SPI Control Interface
26.5.4.1.4
SPI Clock Generator
26.5.4.1.5
SPI Control State-Machine
26.5.4.1.6
SPI Data Shifter
26.5.4.2
QSPI Clock Configuration
26.5.4.3
QSPI Interrupt Requests
26.5.4.4
QSPI Memory Regions
26.5.5
QSPI Register Manual
26.5.5.1
QSPI Instance Summary
26.5.5.2
QSPI registers
26.5.5.2.1
QSPI Register Summary
26.5.5.2.2
QSPI Register Description
26.6
Multichannel Audio Serial Port
26.6.1
McASP Overview
26.6.2
McASP Environment
26.6.2.1
McASP Signals
26.6.2.2
Protocols and Data Formats
26.6.2.2.1
Protocols Supported
26.6.2.2.2
Definition of Terms
26.6.2.2.3
TDM Format
26.6.2.2.4
I2S Format
26.6.2.2.5
S/PDIF Coding Format
26.6.2.2.5.1
Biphase-Mark Code
26.6.2.2.5.2
S/PDIF Subframe Format
26.6.2.2.5.3
Frame Format
26.6.3
McASP Integration
26.6.4
McASP Functional Description
26.6.4.1
McASP Block Diagram
26.6.4.2
McASP Clock and Frame-Sync Configurations
26.6.4.2.1
McASP Transmit Clock
26.6.4.2.2
McASP Receive Clock
26.6.4.2.3
Frame-Sync Generator
26.6.4.2.4
Synchronous and Asynchronous Transmit and Receive Operations
26.6.4.3
Serializers
26.6.4.4
Format Units
26.6.4.4.1
Transmit Format Unit
26.6.4.4.1.1
TDM Mode Transmission Data Alignment Settings
26.6.4.4.1.2
DIT Mode Transmission Data Alignment Settings
26.6.4.4.2
Receive Format Unit
26.6.4.4.2.1
TDM Mode Reception Data Alignment Settings
26.6.4.5
State-Machines
26.6.4.6
TDM Sequencers
26.6.4.7
McASP Software Reset
26.6.4.8
McASP Power Management
26.6.4.9
Transfer Modes
26.6.4.9.1
Burst Transfer Mode
26.6.4.9.2
Time-Division Multiplexed (TDM) Transfer Mode
26.6.4.9.2.1
TDM Time Slots Generation and Processing
26.6.4.9.2.2
Special 384-Slot TDM Mode for Connection to External DIR
26.6.4.9.3
DIT Transfer Mode
26.6.4.9.3.1
Transmit DIT Encoding
26.6.4.9.3.2
Transmit DIT Clock and Frame-Sync Generation
26.6.4.9.3.3
DIT Channel Status and User Data Register Files
26.6.4.10
Data Transmission and Reception
26.6.4.10.1
Data Ready Status and Event/Interrupt Generation
26.6.4.10.1.1
Transmit Data Ready
26.6.4.10.1.2
Receive Data Ready
26.6.4.10.1.3
Transfers Through the Data Port (DATA)
26.6.4.10.1.4
Transfers Through the Configuration Bus (CFG)
26.6.4.10.1.5
Using a Device CPU for McASP Servicing
26.6.4.10.1.6
Using the DMA for McASP Servicing
26.6.4.11
McASP Audio FIFO (AFIFO)
26.6.4.11.1
AFIFO Data Transmission
26.6.4.11.1.1
Transmit DMA Event Pacer
26.6.4.11.2
AFIFO Data Reception
26.6.4.11.2.1
Receive DMA Event Pacer
26.6.4.11.3
Arbitration Between Transmit and Receive DMA Requests
26.6.4.12
McASP Events and Interrupt Requests
26.6.4.12.1
Transmit Data Ready Event and Interrupt
26.6.4.12.2
Receive Data Ready Event and Interrupt
26.6.4.12.3
Error Interrupt
26.6.4.12.4
Multiple Interrupts
26.6.4.13
DMA Requests
26.6.4.14
Loopback Modes
26.6.4.14.1
Loopback Mode Configurations
26.6.4.15
Error Reporting
26.6.4.15.1
Buffer Underrun Error -Transmitter
26.6.4.15.2
Buffer Overrun Error-Receiver
26.6.4.15.3
DATA Port Error - Transmitter
26.6.4.15.4
DATA Port Error - Receiver
26.6.4.15.5
Unexpected Frame Sync Error
26.6.4.15.6
Clock Failure Detection
26.6.4.15.6.1
Clock Failure Check Startup
26.6.4.15.6.2
Transmit Clock Failure Check and Recovery
26.6.4.15.6.3
Receive Clock Failure Check and Recovery
26.6.5
McASP Low-Level Programming Model
26.6.5.1
Global Initialization
26.6.5.1.1
Surrounding Modules Global Initialization
26.6.5.1.2
McASP Global Initialization
26.6.5.1.2.1
Main Sequence – McASP Global Initialization for DIT-Transmission
26.6.5.1.2.1.1
Subsequence – Transmit Format Unit Configuration for DIT-Transmission
26.6.5.1.2.1.2
Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
26.6.5.1.2.1.3
Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
26.6.5.1.2.1.4
Subsequence - McASP Pins Functional Configuration
26.6.5.1.2.1.5
Subsequence – DIT-specific Subframe Fields Configuration
26.6.5.1.2.2
Main Sequence – McASP Global Initialization for TDM-Reception
26.6.5.1.2.2.1
Subsequence – Receive Format Unit Configuration in TDM Mode
26.6.5.1.2.2.2
Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
26.6.5.1.2.2.3
Subsequence – Receive Clock Generator Configuration
26.6.5.1.2.2.4
Subsequence—McASP Receiver Pins Functional Configuration
26.6.5.1.2.3
Main Sequence – McASP Global Initialization for TDM -Transmission
26.6.5.1.2.3.1
Subsequence – Transmit Format Unit Configuration in TDM Mode
26.6.5.1.2.3.2
Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
26.6.5.1.2.3.3
Subsequence – Transmit Clock Generator Configuration for TDM Cases
26.6.5.1.2.3.4
Subsequence—McASP Transmit Pins Functional Configuration
26.6.5.2
Operational Modes Configuration
26.6.5.2.1
McASP Transmission Modes
26.6.5.2.1.1
Main Sequence – McASP DIT- /TDM- Polling Transmission Method
26.6.5.2.1.2
Main Sequence – McASP DIT- /TDM - Interrupt Transmission Method
26.6.5.2.1.3
Main Sequence –McASP DIT- /TDM - Mode DMA Transmission Method
26.6.5.2.2
McASP Reception Modes
26.6.5.2.2.1
Main Sequence – McASP Polling Reception Method
26.6.5.2.2.2
Main Sequence – McASP TDM - Interrupt Reception Method
26.6.5.2.2.3
Main Sequence – McASP TDM - Mode DMA Reception Method
26.6.5.2.3
McASP Event Servicing
26.6.5.2.3.1
McASP DIT-/TDM- Transmit Interrupt Events Servicing
26.6.5.2.3.2
McASP TDM- Receive Interrupt Events Servicing
26.6.5.2.3.3
4175
26.6.5.2.3.4
Subsequence – McASP DIT-/TDM -Modes Transmit Error Handling
26.6.5.2.3.5
Subsequence – McASP Receive Error Handling
26.6.6
McASP Register Manual
26.6.6.1
McASP Instance Summary
26.6.6.2
McASP Registers
26.6.6.2.1
MCASP_CFG Register Summary
26.6.6.2.2
MCASP_CFG Register Description
26.6.6.2.3
MCASP_AFIFO Register Summary
26.6.6.2.4
MCASP_AFIFO Register Description
26.6.6.2.5
MCASP_DAT Register Summary
26.6.6.2.6
MCASP_DAT Register Description
26.7
SuperSpeed USB DRD
26.7.1
SuperSpeed USB DRD Subsystem Overview
26.7.1.1
Main Features
26.7.2
SuperSpeed USB DRD Subsystem Environment
26.7.2.1
SuperSpeed USB DRD Subsystem I/O Interfaces
26.7.2.2
SuperSpeed USB Subsystem Application
26.7.2.2.1
USB3.0 DRD Application
26.7.2.2.2
USB2.0 DRD Internal PHY
26.7.2.2.3
USB2.0 DRD External PHY
26.7.2.2.4
4196
26.7.2.2.5
Host Mode
26.7.2.2.6
Device Mode
26.7.3
SuperSpeed USB Subsystem Integration
26.8
SATA Controller
26.8.1
SATA Controller Overview
26.8.1.1
SATA Controller
26.8.1.1.1
AHCI Mode Overview
26.8.1.1.2
Native Command Queuing
26.8.1.1.3
SATA Transport Layer Functionalities
26.8.1.1.4
SATA Link Layer Functionalities
26.8.1.2
SATA Controller Features
26.8.2
SATA Controller Environment
26.8.3
SATA Controller Integration
26.8.4
SATA Controller Functional Description
26.8.4.1
SATA Controller Block Diagram
26.8.4.2
SATA Controller Link Layer Protocol and Data Format
26.8.4.2.1
SATA 8b/10b Parallel Encoding/Decoding
26.8.4.2.2
SATA Stream Dword Components
26.8.4.2.3
Scrambling/Descrambling Processing
26.8.4.3
Resets
26.8.4.3.1
Hardware Reset
26.8.4.3.2
Software Initiated Resets
26.8.4.3.2.1
Software Reset
26.8.4.3.2.2
Port Reset
26.8.4.3.2.3
HBA Reset
26.8.4.4
Power Management
26.8.4.4.1
SATA Specific Power Management
26.8.4.4.1.1
PARTIAL Power Mode
26.8.4.4.1.2
Slumber Power Mode
26.8.4.4.1.3
Software Control over Low Power States
26.8.4.4.1.4
Aggressive Power Management
26.8.4.4.2
Master Standby and Slave Idle Management Protocols
26.8.4.4.3
Clock Gating Synchronization
26.8.4.4.4
4230
26.8.4.5
Interrupt Requests
26.8.4.5.1
Interrupt Generation
26.8.4.5.2
Levels of Interrupt Control
26.8.4.5.3
Interrupt Events Description
26.8.4.5.3.1
Task File Error Status
26.8.4.5.3.2
Host Bus Fatal Error
26.8.4.5.3.3
Interface Fatal Error Status
26.8.4.5.3.4
Interface Non-Fatal Error Status
26.8.4.5.3.5
Overflow Status
26.8.4.5.3.6
Incorrect Port Multiplier Status
26.8.4.5.3.7
PHYReady Change Status
26.8.4.5.3.8
Port Connect Change Status
26.8.4.5.3.9
Descriptor Processed
26.8.4.5.3.10
Unknown FIS Interrupt
26.8.4.5.3.11
Set Device Bits Interrupt
26.8.4.5.3.12
DMA Setup FIS Interrupt
26.8.4.5.3.13
PIO Setup FIS Interrupt
26.8.4.5.3.14
Device to Host Register FIS Interrupt
26.8.4.5.4
Interrupt Condition Control
26.8.4.5.5
Command Completion Coalescing Interrupts
26.8.4.5.5.1
CCC Interrupt Based on Expired Timeout Value
26.8.4.5.5.2
CCC Interrupt Based on Completion Count
26.8.4.6
System Memory FIS Descriptors
26.8.4.6.1
Command List Structure Basics
26.8.4.6.2
Supported Types of Commands
26.8.4.6.3
Received FIS Structures
26.8.4.6.4
FIS Descriptors Summary
26.8.4.7
Transport Layer FIS-Based Interactions
26.8.4.7.1
Software Processing of the Port Command List
26.8.4.7.2
Handling the Received FIS Descriptors
26.8.4.8
DMA Port Configuration
26.8.4.9
Port Multiplier Operation
26.8.4.9.1
Command-Based Switching Mode
26.8.4.9.1.1
Port Multiplier NCQ and Non-NCQ Commands Generation
26.8.4.9.2
Port Multiplier Enumeration
26.8.4.10
Activity LED Generation Functionality
26.8.4.11
Supported Types of SATA Transfers
26.8.4.11.1
Supported Higher Level Protocols
26.8.4.12
SATA Controller AHCI Hardware Register Interface
26.8.5
SATA Controller Low Level Programming Model
26.8.5.1
Global Initialization
26.8.5.1.1
Surrounding Modules Global Initialization
26.8.5.1.2
SATA Controller Global Initialization
26.8.5.1.2.1
Main Sequence SATA Controller Global Initialization
26.8.5.1.2.2
SubSequence – Firmware Capability Writes
26.8.5.1.3
Issue Command - Main Sequence
26.8.5.1.4
Receive FIS—Main Sequence
26.8.6
SATA Controller Register Manual
26.8.6.1
SATA Controller Instance Summary
26.8.6.2
DWC_ahsata Registers
26.8.6.2.1
DWC_ahsata Register Summary
26.8.6.2.2
DWC_ahsata Register Description
26.8.6.3
SATAMAC_wrapper Registers
26.8.6.3.1
SATAMAC_wrapper Register Summary
26.8.6.3.2
SATAMAC_wrapper Register Description
26.9
PCIe Controller
26.9.1
PCIe Controller Subsystem Overview
26.9.1.1
PCIe Controllers Key Features
26.9.2
PCIe Controller Environment
26.9.3
PCIe Controllers Integration
26.9.4
PCIe SS Controller Functional Description
26.9.4.1
PCIe Controller Functional Block Diagram
26.9.4.2
PCIe Traffics
26.9.4.3
PCIe Controller Ports on L3_MAIN Interconnect
26.9.4.3.1
PCIe Controller Master Port
26.9.4.3.1.1
PCIe Controller Master Port to MMU Routing
26.9.4.3.2
PCIe Controller Slave Port
26.9.4.3.3
4298
26.9.4.4
PCIe Controller Reset Management
26.9.4.4.1
PCIe Reset Types and Stickiness
26.9.4.4.2
PCIe Reset Conditions
26.9.4.4.2.1
PCIe Main Reset
26.9.4.4.2.1.1
PCIe Subsystem Cold Main Reset Source
26.9.4.4.2.1.2
PCIe Subsystem Warm Main Reset Sources
26.9.4.4.2.2
PCIe Standard Specific Resets to the PCIe Core Logic
26.9.4.5
PCIe Controller Power Management
26.9.4.5.1
PCIe Protocol Power Management
26.9.4.5.1.1
PCIe Device/function power state (D-state)
26.9.4.5.1.2
PCIe Controller PIPE Powerstate (Powerdown Control)
26.9.4.5.2
PCIE Controller Clocks Management
26.9.4.5.2.1
PCIe Clock Domains
26.9.4.5.2.2
PCIe Controller Idle/Standby Clock Management Interfaces
26.9.4.5.2.2.1
PCIe Controller Master Standby Behavior
26.9.4.5.2.2.2
PCIe Controller Slave Idle/Disconnect Behavior
26.9.4.5.2.2.2.1
PCIe Controller Idle Sequence During D3cold/L3 State
26.9.4.6
PCIe Controller Interrupt Requests
26.9.4.6.1
PCIe Controller Main Hardware Management
26.9.4.6.1.1
PCIe Management Interrupt Events
26.9.4.6.1.2
PCIe Error Interrupt Events
26.9.4.6.1.3
Summary of PCIe Controller Main Hardware Interrupt Events
26.9.4.6.2
PCIe Controller Legacy and MSI Virtual Interrupts Management
26.9.4.6.2.1
Legacy PCI Interrupts (INTx)
26.9.4.6.2.1.1
Legacy PCI Interrupt Events Overview
26.9.4.6.2.1.2
Legacy PCI Interrupt Transmission (EP mode only)
26.9.4.6.2.1.3
Legacy PCI Interrupt Reception (RC mode only)
26.9.4.6.2.2
PCIe Controller Message Signaled Interrupts (MSI)
26.9.4.6.2.2.1
PCIe Specific MSI Interrupt Event Overview
26.9.4.6.2.2.2
PCIe Controller MSI Transmission Methods (EP mode)
26.9.4.6.2.2.2.1
PCIe Controller MSI transmission, hardware method
26.9.4.6.2.2.2.2
PCIe Controller MSI transmission, software method
26.9.4.6.2.2.3
PCIe Controller MSI Reception (RC mode)
26.9.4.6.3
PCIe Controller MSI Hardware Interrupt Events
26.9.4.7
PCIe Controller Address Spaces and Address Translation
26.9.4.8
PCIe Traffic Requesting and Responding
26.9.4.8.1
PCIe Memory-type (Mem) Traffic Management
26.9.4.8.1.1
PCIe Memory Requesting
26.9.4.8.1.2
PCIe Memory Responding
26.9.4.8.2
PCIe Configuration Type (Cfg) Traffic Management
26.9.4.8.2.1
RC Self-configuration (RC Only)
26.9.4.8.2.2
Configuration Requests over PCIe (RC Only)
26.9.4.8.2.3
Configuration Responding over PCIe (EP Only)
26.9.4.8.3
PCIe I/O-type (IO) traffic management
26.9.4.8.3.1
PCIe I/O requesting (RC only)
26.9.4.8.3.2
PCIe IO BAR initialization before enumeration (EP only)
26.9.4.8.3.3
PCIe I/O responding (PCI legacy EP only)
26.9.4.8.4
PCIe Message-type (Msg) traffic management
26.9.4.9
PCIe Programming Register Interface
26.9.4.9.1
PCIe Register Access
26.9.4.9.2
Double Mapping of the PCIe Local Control Registers
26.9.4.9.3
Base Address Registers (BAR) Initialization
26.9.5
PCIe Controller Low Level Programming Model
26.9.5.1
Surrounding Modules Global Initialization
26.9.5.2
Main Sequence of PCIe Controllers Initalization
26.9.6
PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping
26.9.7
PCIe Controller Register Manual
26.9.7.1
PCIe Controller Instance Summary
26.9.7.2
PCIe_SS_EP_CFG_PCIe Registers
26.9.7.2.1
PCIe_SS_EP_CFG_PCIe Register Summary
26.9.7.2.2
PCIe_SS_EP_CFG_PCIe Register Description
26.9.7.2.3
4360
26.9.7.3
PCIe_SS_EP_CFG_DBICS Registers
26.9.7.3.1
PCIe_SS_EP_CFG_DBICS Register Summary
26.9.7.3.2
PCIe_SS_EP_CFG_DBICS Register Description
26.9.7.4
PCIe_SS_RC_CFG_DBICS Registers
26.9.7.4.1
PCIe_SS_RC_CFG_DBICS Register Summary
26.9.7.4.2
PCIe_SS_RC_CFG_DBICS Register Description
26.9.7.5
PCIe_SS_PL_CONF Registers
26.9.7.5.1
PCIe_SS_PL_CONF Register Summary
26.9.7.5.2
PCIe_SS_PL_CONF Register Description
26.9.7.6
PCIe_SS_EP_CFG_DBICS2 Registers
26.9.7.6.1
PCIe_SS_EP_CFG_DBICS2 Register Summary
26.9.7.6.2
PCIe_SS_EP_CFG_DBICS2 Register Description
26.9.7.7
PCIe_SS_RC_CFG_DBICS2 Registers
26.9.7.7.1
PCIe_SS_RC_CFG_DBICS2 Register Summary
26.9.7.7.2
PCIe_SS_RC_CFG_DBICS2 Register Description
26.9.7.8
PCIe_SS_TI_CONF Registers
26.9.7.8.1
PCIe_SS_TI_CONF Register Summary
26.9.7.8.2
PCIe_SS_TI_CONF Register Description
26.10
DCAN
26.10.1
DCAN Overview
26.10.1.1
Features
26.10.2
DCAN Environment
26.10.2.1
CAN Network Basics
26.10.3
DCAN Integration
26.10.4
DCAN Functional Description
26.10.4.1
Module Clocking Requirements
26.10.4.2
Interrupt Functionality
26.10.4.2.1
Message Object Interrupts
26.10.4.2.2
Status Change Interrupts
26.10.4.2.3
Error Interrupts
26.10.4.3
DMA Functionality
26.10.4.4
Local Power-Down Mode
26.10.4.4.1
Entering Local Power-Down Mode
26.10.4.4.2
Wakeup From Local Power Down
26.10.4.5
Parity Check Mechanism
26.10.4.5.1
Behavior on Parity Error
26.10.4.5.2
Parity Testing
26.10.4.6
Debug/Suspend Mode
26.10.4.7
Configuration of Message Objects Description
26.10.4.7.1
Configuration of a Transmit Object for Data Frames
26.10.4.7.2
Configuration of a Transmit Object for Remote Frames
26.10.4.7.3
Configuration of a Single Receive Object for Data Frames
26.10.4.7.4
Configuration of a Single Receive Object for Remote Frames
26.10.4.7.5
Configuration of a FIFO Buffer
26.10.4.8
Message Handling
26.10.4.8.1
Message Handler Overview
26.10.4.8.2
Receive/Transmit Priority
26.10.4.8.3
Transmission of Messages in Event Driven CAN Communication
26.10.4.8.4
Updating a Transmit Object
26.10.4.8.5
Changing a Transmit Object
26.10.4.8.6
Acceptance Filtering of Received Messages
26.10.4.8.7
Reception of Data Frames
26.10.4.8.8
Reception of Remote Frames
26.10.4.8.9
Reading Received Messages
26.10.4.8.10
Requesting New Data for a Receive Object
26.10.4.8.11
Storing Received Messages in FIFO Buffers
26.10.4.8.12
Reading From a FIFO Buffer
26.10.4.9
CAN Bit Timing
26.10.4.9.1
Bit Time and Bit Rate
26.10.4.9.1.1
Synchronization Segment
26.10.4.9.1.2
Propagation Time Segment
26.10.4.9.1.3
Phase Buffer Segments and Synchronization
26.10.4.9.1.4
Oscillator Tolerance Range
26.10.4.9.2
DCAN Bit Timing Registers
26.10.4.9.2.1
Calculation of the Bit Timing Parameters
26.10.4.9.2.2
Example for Bit Timing Calculation
26.10.4.10
Message Interface Register Sets
26.10.4.10.1
Message Interface Register Sets 1 and 2
26.10.4.10.2
IF3 Register Set
26.10.4.11
Message RAM
26.10.4.11.1
Structure of Message Objects
26.10.4.11.2
Addressing Message Objects in RAM
26.10.4.11.3
Message RAM Representation in Debug/Suspend Mode
26.10.4.11.4
Message RAM Representation in Direct Access Mode
26.10.4.12
CAN Operation
26.10.4.12.1
CAN Module Initialization
26.10.4.12.1.1
Configuration of CAN Bit Timing
26.10.4.12.1.2
Configuration of Message Objects
26.10.4.12.1.3
DCAN RAM Hardware Initialization
26.10.4.12.2
CAN Message Transfer (Normal Operation)
26.10.4.12.2.1
Automatic Retransmission
26.10.4.12.2.2
Auto-Bus-On
26.10.4.12.3
Test Modes
26.10.4.12.3.1
Silent Mode
26.10.4.12.3.2
Loopback Mode
26.10.4.12.3.3
External Loopback Mode
26.10.4.12.3.4
Loopback Mode Combined With Silent Mode
26.10.4.12.3.5
Software Control of CAN_TX Pin
26.10.4.13
GPIO Support
26.10.5
DCAN Register Manual
26.10.5.1
DCAN Instance Summary
26.10.5.2
DCAN Registers
26.10.5.2.1
DCAN Register Summary
26.10.5.2.2
DCAN Register Description
26.11
MCAN
26.11.1
MCAN Overview
26.11.1.1
Features
26.11.2
MCAN Environment
26.11.2.1
CAN Network Basics
26.11.3
MCAN Integration
26.11.4
MCAN Functional Description
26.11.4.1
Module Clocking Requirements
26.11.4.2
Interrupt and DMA Requests
26.11.4.2.1
Interrupt Requests
26.11.4.2.2
DMA Requests
26.11.4.2.3
4466
26.11.4.3
Fuseable CAN FD Operation Enable
26.11.4.4
Operating Modes
26.11.4.4.1
Software Initialization
26.11.4.4.2
Normal Operation
26.11.4.4.3
CAN FD Operation
26.11.4.4.4
Transmitter Delay Compensation
26.11.4.4.4.1
Description
26.11.4.4.4.2
Transmitter Delay Compensation Measurement
26.11.4.4.5
Restricted Operation Mode
26.11.4.4.6
Bus Monitoring Mode
26.11.4.4.7
Disabled Automatic Retransmission (DAR) Mode
26.11.4.4.7.1
Frame Transmission in DAR Mode
26.11.4.4.8
Power Down (Sleep Mode)
26.11.4.4.8.1
External Clock Stop Mode
26.11.4.4.8.2
Suspend Mode
26.11.4.4.8.3
Wakeup request
26.11.4.4.9
Test Modes
26.11.4.4.9.1
Internal Loop Back Mode
26.11.4.5
Timestamp Generation
26.11.4.5.1
External Timestamp Counter
26.11.4.6
Timeout Counter
26.11.4.7
Safety
26.11.4.7.1
ECC Wrapper
26.11.4.7.2
ECC Aggregator
26.11.4.7.2.1
ECC Aggregator Overview
26.11.4.7.2.2
ECC Aggregator Registers
26.11.4.7.2.3
Reads to ECC Control and Status Registers
26.11.4.7.2.4
ECC Interrupts
26.11.4.8
Rx Handling
26.11.4.8.1
Acceptance Filtering
26.11.4.8.1.1
Range Filter
26.11.4.8.1.2
Filter for specific IDs
26.11.4.8.1.3
Classic Bit Mask Filter
26.11.4.8.1.4
Standard Message ID Filtering
26.11.4.8.1.5
Extended Message ID Filtering
26.11.4.8.2
Rx FIFOs
26.11.4.8.2.1
Rx FIFO Blocking Mode
26.11.4.8.2.2
Rx FIFO Overwrite Mode
26.11.4.8.3
Dedicated Rx Buffers
26.11.4.8.3.1
Rx Buffer Handling
26.11.4.9
Tx Handling
26.11.4.9.1
Transmit Pause
26.11.4.9.2
Dedicated Tx Buffers
26.11.4.9.3
Tx FIFO
26.11.4.9.4
Tx Queue
26.11.4.9.5
Mixed Dedicated Tx Buffers/Tx FIFO
26.11.4.9.6
Mixed Dedicated Tx Buffers/Tx Queue
26.11.4.9.7
Transmit Cancellation
26.11.4.9.8
Tx Event Handling
26.11.4.10
FIFO Acknowledge Handling
26.11.4.11
Message RAM
26.11.4.11.1
Message RAM Configuration
26.11.4.11.2
Rx Buffer and FIFO Element
26.11.4.11.3
Tx Buffer Element
26.11.4.11.4
Tx Event FIFO Element
26.11.4.11.5
Standard Message ID Filter Element
26.11.4.11.6
Extended Message ID Filter Element
26.11.5
MCAN Register Manual
26.11.5.1
MCAN Instance Summary
26.11.5.2
MCAN Registers
26.11.5.2.1
MCAN Register Summary
26.11.5.2.2
MCAN Register Description
26.12
Gigabit Ethernet Switch (GMAC_SW)
26.12.1
GMAC_SW Overview
26.12.1.1
Features
26.12.1.2
4532
26.12.2
GMAC_SW Environment
26.12.2.1
G/MII Interface
26.12.2.2
RMII Interface
26.12.2.3
RGMII Interface
26.12.3
GMAC_SW Integration
26.12.4
GMAC_SW Functional Description
26.12.4.1
Functional Block Diagram
26.12.4.2
GMAC_SW Ports
26.12.4.2.1
Interface Mode Selection
26.12.4.3
Clocking
26.12.4.3.1
Subsystem Clocking
26.12.4.3.2
Interface Clocking
26.12.4.3.2.1
G/MII Interface Clocking
26.12.4.3.2.2
RGMII Interface Clocking
26.12.4.3.2.3
RMII Interface Clocking
26.12.4.3.2.4
MDIO Clocking
26.12.4.4
Software IDLE
26.12.4.5
Interrupt Functionality
26.12.4.5.1
Receive Packet Completion Pulse Interrupt (RX_PULSE)
26.12.4.5.2
Transmit Packet Completion Pulse Interrupt (TX_PULSE)
26.12.4.5.3
Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
26.12.4.5.4
Miscellaneous Pulse Interrupt (MISC_PULSE)
26.12.4.5.4.1
EVNT_PEND( CPTS_PEND) Interrupt
26.12.4.5.4.2
Statistics Interrupt
26.12.4.5.4.3
Host Error interrupt
26.12.4.5.4.4
MDIO Interrupts
26.12.4.5.5
Interrupt Pacing
26.12.4.6
Reset Isolation
26.12.4.6.1
Reset Isolation Functional Description
26.12.4.7
Software Reset
26.12.4.8
CPSW_3G
26.12.4.8.1
CPDMA RX and TX Interfaces
26.12.4.8.1.1
Functional Operation
26.12.4.8.1.2
Receive DMA Interface
26.12.4.8.1.2.1
Receive DMA Host Configuration
26.12.4.8.1.2.2
Receive Channel Teardown
26.12.4.8.1.3
Transmit DMA Interface
26.12.4.8.1.3.1
Transmit DMA Host Configuration
26.12.4.8.1.3.2
Transmit Channel Teardown
26.12.4.8.1.4
Transmit Rate Limiting
26.12.4.8.1.5
Command IDLE
26.12.4.8.2
Address Lookup Engine (ALE)
26.12.4.8.2.1
Address Table Entry
26.12.4.8.2.1.1
Free Table Entry
26.12.4.8.2.1.2
Multicast Address Table Entry
26.12.4.8.2.1.3
VLAN/Multicast Address Table Entry
26.12.4.8.2.1.4
Unicast Address Table Entry
26.12.4.8.2.1.5
OUI Unicast Address Table Entry
26.12.4.8.2.1.6
VLAN/Unicast Address Table Entry
26.12.4.8.2.1.7
VLAN Table Entry
26.12.4.8.2.2
Packet Forwarding Processes
26.12.4.8.2.3
Learning Process
26.12.4.8.2.4
VLAN Aware Mode
26.12.4.8.2.5
VLAN Unaware Mode
26.12.4.8.3
Packet Priority Handling
26.12.4.8.4
FIFO Memory Control
26.12.4.8.5
FIFO Transmit Queue Control
26.12.4.8.5.1
Normal Priority Mode
26.12.4.8.5.2
Dual MAC Mode
26.12.4.8.5.3
Rate Limit Mode
26.12.4.8.6
Audio Video Bridging
26.12.4.8.6.1
IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
26.12.4.8.6.1.1
IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
26.12.4.8.6.1.2
IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
26.12.4.8.6.2
IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
26.12.4.8.6.2.1
Configuring the Device for 802.1Qav Operation:
26.12.4.8.7
Ethernet MAC Sliver (CPGMAC_SL)
26.12.4.8.7.1
G/MII Media Independent Interface
26.12.4.8.7.1.1
Data Reception
26.12.4.8.7.1.1.1
Receive Control
26.12.4.8.7.1.1.2
Receive Inter-Frame Interval
26.12.4.8.7.1.2
Data Transmission
26.12.4.8.7.1.2.1
Transmit Control
26.12.4.8.7.1.2.2
CRC Insertion
26.12.4.8.7.1.2.3
MTXER
26.12.4.8.7.1.2.4
Adaptive Performance Optimization (APO)
26.12.4.8.7.1.2.5
Inter-Packet-Gap Enforcement
26.12.4.8.7.1.2.6
Back Off
26.12.4.8.7.1.2.7
Programmable Transmit Inter-Packet Gap
26.12.4.8.7.1.2.8
Speed, Duplex and Pause Frame Support Negotiation
26.12.4.8.7.2
RMII Interface
26.12.4.8.7.2.1
Features
26.12.4.8.7.2.2
RMII Receive (RX)
26.12.4.8.7.2.3
RMII Transmit (TX)
26.12.4.8.7.3
RGMII Interface
26.12.4.8.7.3.1
RGMII Features
26.12.4.8.7.3.2
RGMII Receive (RX)
26.12.4.8.7.3.3
In-Band Mode of Operation
26.12.4.8.7.3.4
Forced Mode of Operation
26.12.4.8.7.3.5
RGMII Transmit (TX)
26.12.4.8.7.4
Frame Classification
26.12.4.8.8
Embedded Memories
26.12.4.8.9
Flow Control
26.12.4.8.9.1
CPPI Port Flow Control
26.12.4.8.9.2
Ethernet Port Flow Control
26.12.4.8.9.2.1
Receive Flow Control
26.12.4.8.9.2.1.1
Collision Based Receive Buffer Flow Control
26.12.4.8.9.2.1.2
IEEE 802.3X Based Receive Flow Control
26.12.4.8.9.2.2
Transmit Flow Control
26.12.4.8.10
Short Gap
26.12.4.8.11
Switch Latency
26.12.4.8.12
Emulation Control
26.12.4.8.13
FIFO Loopback
26.12.4.8.14
Device Level Ring (DLR) Support
26.12.4.8.15
Energy Efficient Ethernet Support (802.3az)
26.12.4.8.16
CPSW_3G Network Statistics
26.12.4.8.16.1
4639
26.12.4.9
Static Packet Filter (SPF)
26.12.4.9.1
SPF Overview
26.12.4.9.2
SPF Functional Description
26.12.4.9.2.1
SPF Block Diagram
26.12.4.9.2.2
Interrupts
26.12.4.9.2.3
Protocol Header Extractor
26.12.4.9.2.4
Programmable Rule Engine
26.12.4.9.2.4.1
Internal Registers
26.12.4.9.2.4.2
Packet Buffer
26.12.4.9.2.5
Intrusion Event Logger
26.12.4.9.2.6
Rate Limiter
26.12.4.9.2.7
Rule Engine Instruction Set Architecture
26.12.4.9.2.7.1
Instruction Format
26.12.4.9.2.7.2
Operand Field
26.12.4.9.2.7.3
Arithmetic/Logical Function Field
26.12.4.9.2.7.4
Operation Field
26.12.4.9.3
Programming Guide
26.12.4.9.3.1
Initialization Routine
26.12.4.9.3.2
Interrupt Service Routine
26.12.4.9.3.3
Rule Engine Example Program
26.12.4.10
Common Platform Time Sync (CPTS)
26.12.4.10.1
CPTS Architecture
26.12.4.10.2
CPTS Initialization
26.12.4.10.3
Time Stamp Value
26.12.4.10.4
Event FIFO
26.12.4.10.5
Time Sync Events
26.12.4.10.5.1
Time Stamp Push Event
26.12.4.10.5.2
Time Stamp Counter Rollover Event
26.12.4.10.5.3
Time Stamp Counter Half-rollover Event
26.12.4.10.5.4
Hardware Time Stamp Push Event
26.12.4.10.5.5
Ethernet Port Events
26.12.4.10.6
CPTS Interrupt Handling
26.12.4.11
CPPI Buffer Descriptors
26.12.4.11.1
TX Buffer Descriptors
26.12.4.11.1.1
CPPI TX Data Word 0
26.12.4.11.1.2
CPPI TX Data Word 1
26.12.4.11.1.3
CPPI TX Data Word 2
26.12.4.11.1.4
CPPI TX Data Word 3
26.12.4.11.2
RX Buffer Descriptors
26.12.4.11.2.1
CPPI RX Data Word 0
26.12.4.11.2.2
CPPI RX Data Word 1
26.12.4.11.2.3
CPPI RX Data Word 2
26.12.4.11.2.4
CPPI RX Data Word 3
26.12.4.12
MDIO
26.12.4.12.1
MDIO Frame Formats
26.12.4.12.2
MDIO Functional Description
26.12.5
GMAC_SW Programming Guide
26.12.5.1
Transmit Operation
26.12.5.2
Receive Operation
26.12.5.3
MDIO Software Interface
26.12.5.3.1
Initializing the MDIO Module
26.12.5.3.2
Writing Data To a PHY Register
26.12.5.3.3
Reading Data From a PHY Register
26.12.5.4
Initialization and Configuration of CPSW
26.12.6
GMAC_SW Register Manual
26.12.6.1
GMAC_SW Instance Summary
26.12.6.2
SS Registers
26.12.6.2.1
SS Register Summary
26.12.6.2.2
SS Register Description
26.12.6.3
PORT Registers
26.12.6.3.1
PORT Register Summary
26.12.6.3.2
PORT Register Description
26.12.6.4
CPDMA registers
26.12.6.4.1
CPDMA Register Summary
26.12.6.4.2
CPDMA Register Description
26.12.6.5
STATS Registers
26.12.6.5.1
STATS Register Summary
26.12.6.5.2
STATS Register Description
26.12.6.6
STATERAM Registers
26.12.6.6.1
STATERAM Register Summary
26.12.6.6.2
STATERAM Register Description
26.12.6.7
CPTS registers
26.12.6.7.1
CPTS Register Summary
26.12.6.7.2
CPTS Register Description
26.12.6.8
ALE registers
26.12.6.8.1
ALE Register Summary
26.12.6.8.2
ALE Register Description
26.12.6.9
SL registers
26.12.6.9.1
SL Register Summary
26.12.6.9.2
SL Register Description
26.12.6.10
MDIO registers
26.12.6.10.1
MDIO Register Summary
26.12.6.10.2
MDIO Register Description
26.12.6.11
WR registers
26.12.6.11.1
WR Register Summary
26.12.6.11.2
WR Register Description
26.12.6.12
SPF Registers
26.12.6.12.1
SPF Register Summary
26.12.6.12.2
SPF Register Description
26.13
Media Local Bus (MLB)
26.13.1
MLB Overview
26.13.2
MLB Environment
26.13.2.1
MLB IO Cell Controls
26.13.2.2
Doubling the MLB Clock Line Frequency
26.13.3
MLB Integration
26.13.4
MLB Functional Description
26.13.4.1
Block Diagram
26.13.4.1.1
MediaLB Core Block
26.13.4.1.2
Routing Fabric Block
26.13.4.1.3
Data Buffer RAM
26.13.4.1.4
Channel Table RAM
26.13.4.1.4.1
Channel Allocation Table
26.13.4.1.4.2
Channel Descriptor Table
26.13.4.1.5
DMA Block
26.13.4.1.5.1
Synchronous Channel Descriptor
26.13.4.1.5.2
Isochronous Channel Descriptors
26.13.4.1.5.3
Asynchronous and Control Channel Descriptors
26.13.4.1.5.3.1
Single-Packet Mode
26.13.4.1.5.3.2
Multiple-Packet Mode
26.13.4.2
Software and Data Flow for MLBSS
26.13.4.2.1
Data Flow For Receive Channels
26.13.4.2.2
Data Flow for Transmit Channels
26.13.4.3
MLB Priority On The L3_MAIN Interconnect
26.13.5
MLB Programming Guide
26.13.5.1
Global Initialization
26.13.5.1.1
Surrounding Modules Global Initialization
26.13.5.1.2
MLBSS Global Initialization
26.13.5.1.2.1
Channel Initialization
26.13.5.2
MLBSS Operational Modes Configuration
26.13.5.2.1
Channel Servicing
26.13.5.2.2
Channel Table RAM Access
26.13.6
MLB Register Manual
26.13.6.1
MLB Instance Summary
26.13.6.2
MLB registers
26.13.6.2.1
MLB Register Summary
26.13.6.2.2
MLB Register Description
27
eMMC/SD/SDIO
27.1
eMMC/SD/SDIO Overview
27.1.1
eMMC/SD/SDIO Features
27.2
eMMC/SD/SDIO Environment
27.2.1
eMMC/SD/SDIO Functional Modes
27.2.1.1
eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
27.2.2
Protocol and Data Format
27.2.2.1
Protocol
27.2.2.2
Data Format
27.3
eMMC/SD/SDIO Integration
27.4
eMMC/SD/SDIO Functional Description
27.4.1
Block Diagram
27.4.2
Resets
27.4.2.1
Hardware Reset
27.4.2.2
Software Reset
27.4.3
Power Management
27.4.4
Interrupt Requests
27.4.4.1
Interrupt-Driven Operation
27.4.4.2
Polling
27.4.4.3
Asynchronous Interrupt
27.4.5
DMA Modes
27.4.5.1
Master DMA Operations
27.4.5.1.1
Descriptor Table Description
27.4.5.1.2
Requirements for Descriptors
27.4.5.1.2.1
Data Length
27.4.5.1.2.2
Supported Features
27.4.5.1.2.3
Error Generation
27.4.5.1.3
Advanced DMA Description
27.4.5.2
Slave DMA Operations
27.4.5.2.1
DMA Receive Mode
27.4.5.2.2
DMA Transmit Mode
27.4.6
Mode Selection
27.4.7
Buffer Management
27.4.7.1
Data Buffer
27.4.7.1.1
Memory Size, Block Length, and Buffer-Management Relationship
27.4.7.1.2
Data Buffer Status
27.4.8
Transfer Process
27.4.8.1
Different Types of Commands
27.4.8.2
Different Types of Responses
27.4.9
Transfer or Command Status and Errors Reporting
27.4.9.1
Busy Time-Out for R1b, R5b Response Type
27.4.9.2
Busy Time-Out After Write CRC Status
27.4.9.3
Write CRC Status Time-Out
27.4.9.4
Read Data Time-Out
27.4.9.5
Boot Acknowledge Time-Out
27.4.10
Auto Command 12 Timings
27.4.10.1
Auto CMD12 Timings During Write Transfer
27.4.10.2
Auto CMD12 Timings During Read Transfer
27.4.11
Transfer Stop
27.4.12
Output Signals Generation
27.4.12.1
Generation on Falling Edge of MMC Clock
27.4.12.2
Generation on Rising Edge of MMC Clock
27.4.13
Sampling Clock Tuning
27.4.14
Card Boot Mode Management
27.4.14.1
Boot Mode Using CMD0
27.4.14.2
Boot Mode With CMD Line Tied to 0
27.4.15
MMC CE-ATA Command Completion Disable Management
27.4.16
Test Registers
27.4.17
eMMC/SD/SDIO Hardware Status Features
27.5
eMMC/SD/SDIO Programming Guide
27.5.1
Low-Level Programming Models
27.5.1.1
Global Initialization
27.5.1.1.1
Surrounding Modules Global Initialization
27.5.1.1.2
eMMC/SD/SDIO Host Controller Initialization Flow
27.5.1.1.2.1
Enable Interface and Functional Clock for MMC Controller
27.5.1.1.2.2
MMCHS Soft Reset Flow
27.5.1.1.2.3
Set MMCHS Default Capabilities
27.5.1.1.2.4
Wake-Up Configuration
27.5.1.1.2.5
MMC Host and Bus Configuration
27.5.1.2
Operational Modes Configuration
27.5.1.2.1
Basic Operations for eMMC/SD/SDIO Host Controller
27.5.1.2.1.1
Card Detection, Identification, and Selection
27.5.1.2.1.1.1
CMD Line Reset Procedure
27.5.1.2.1.2
Read/Write Transfer Flow in DMA Mode With Interrupt
27.5.1.2.1.2.1
DATA Lines Reset Procedure
27.5.1.2.1.3
Read/Write Transfer Flow in DMA Mode With Polling
27.5.1.2.1.4
Read/Write Transfer Flow Without DMA With Polling
27.5.1.2.1.5
Read/Write Transfer Flow in CE-ATA Mode
27.5.1.2.1.6
Suspend-Resume Flow
27.5.1.2.1.6.1
Suspend Flow
27.5.1.2.1.6.2
Resume Flow
27.5.1.2.1.7
Basic Operations – Steps Detailed
27.5.1.2.1.7.1
Command Transfer Flow
27.5.1.2.1.7.2
MMCHS Clock Frequency Change
27.5.1.2.1.7.3
Bus Width Selection
27.5.1.2.2
Bus Voltage Selection
27.5.1.2.3
Boot Mode Configuration
27.5.1.2.3.1
Boot Using CMD0
27.5.1.2.3.2
Boot With CMD Line Tied to 0
27.5.1.2.4
SDR104/HS200 DLL Tuning Procedure
27.6
eMMC/SD/SDIO Register Manual
27.6.1
eMMC/SD/SDIO Instance Summary
27.6.2
eMMC/SD/SDIO Registers
27.6.2.1
eMMC/SD/SDIO Register Summary
27.6.2.2
eMMC/SD/SDIO Register Description
28
Shared PHY Component Subsystem
28.1
SATA PHY Subsystem
28.1.1
SATA PHY Subsystem Overview
28.1.2
SATA PHY Subsystem Environment
28.1.2.1
SATA PHY I/O Signals
28.1.3
SATA PHY Subsystem Integration
28.1.4
SATA PHY Subsystem Functional Description
28.1.4.1
SATA PLL Controller L4 Interface Adapter Functional Description
28.1.4.2
SATA PHY Serializer and Deserializer Functional Descriptions
28.1.4.2.1
SATA PHY Reset
28.1.4.2.2
SATA_PHY Clocking
28.1.4.2.2.1
SATA_PHY Input Clocks
28.1.4.2.2.2
SATA_PHY Output Clocks
28.1.4.2.3
SATA_PHY Power Management
28.1.4.2.3.1
SATA_PHY Power-Up/-Down Sequences
28.1.4.2.3.2
SATA_PHY Low-Power Modes
28.1.4.2.4
SATA_PHY Hardware Requests
28.1.4.3
SATA Clock Generator Subsystem Functional Description
28.1.4.3.1
SATA DPLL Clock Generator Overview
28.1.4.3.2
SATA DPLL Clock Generator Reset
28.1.4.3.3
SATA DPLL Low-Power Modes
28.1.4.3.4
SATA DPLL Clocks Configuration
28.1.4.3.4.1
SATA DPLL Input Clock Control
28.1.4.3.4.2
SATA DPLL Output Clock Configuration
28.1.4.3.4.2.1
SATA DPLL Output Clock Gating
28.1.4.3.5
SATA DPLL Subsystem Architecture
28.1.4.3.6
SATA DPLL Clock Generator Modes and State Transitions
28.1.4.3.6.1
SATA Clock Generator Power Up
28.1.4.3.6.2
SATA DPLL Sequences
28.1.4.3.6.3
SATA DPLL Locked Mode
28.1.4.3.6.4
SATA DPLL Idle-Bypass Mode
28.1.4.3.6.5
SATA DPLL MN-Bypass Mode
28.1.4.3.6.6
SATA DPLL Error Conditions
28.1.4.3.7
SATA PLL Controller Functions
28.1.4.3.7.1
SATA PLL Controller Register Access
28.1.4.3.7.2
SATA DPLL Clock Programming Sequence
28.1.4.3.7.3
SATA DPLL Recommended Values
28.1.5
SATA PHY Subsystem Low-Level Programming Model
28.2
USB3_PHY Subsystem
28.2.1
USB3_PHY Subsystem Overview
28.2.2
USB3_PHY Subsystem Environment
28.2.2.1
USB3_PHY I/O Signals
28.2.3
USB3_PHY Subsystem Integration
28.2.4
USB3_PHY Subsystem Functional Description
28.2.4.1
Super-Speed USB PLL Controller L4 Interface Adapter Functional Description
28.2.4.2
USB3_PHY Serializer and Deserializer Functional Descriptions
28.2.4.2.1
USB3_PHY Module Resets
28.2.4.2.1.1
Hardware Reset
28.2.4.2.1.2
Software Reset
28.2.4.2.2
USB3_PHY Subsystem Clocking
28.2.4.2.2.1
USB3_PHY Subsystem Input Clocks
28.2.4.2.2.2
USB3_PHY Subsystem Output Clocks
28.2.4.2.3
USB3_PHY Power Management
28.2.4.2.3.1
USB3_PHY Power-Up/-Down Sequences
28.2.4.2.3.2
USB3_PHY Low-Power Modes
28.2.4.2.3.3
Clock Gating
28.2.4.2.4
USB3_PHY Hardware Requests
28.2.4.3
USB3_PHY Clock Generator Subsystem Functional Description
28.2.4.3.1
USB3_PHY DPLL Clock Generator Overview
28.2.4.3.2
USB3_PHY DPLL Clock Generator Reset
28.2.4.3.3
USB3_PHY DPLL Low-Power Modes
28.2.4.3.4
USB3_PHY DPLL Clocks Configuration
28.2.4.3.4.1
USB3_PHY DPLL Input Clock Control
28.2.4.3.4.2
USB3_PHY DPLL Output Clock Configuration
28.2.4.3.4.2.1
USB3_PHY DPLL Output Clock Gating
28.2.4.3.5
USB3_PHY DPLL Subsystem Architecture
28.2.4.3.6
USB3_PHY DPLL Clock Generator Modes and State Transitions
28.2.4.3.6.1
USB3_PHY Clock Generator Power Up
28.2.4.3.6.2
USB3_PHY DPLL Sequences
28.2.4.3.6.3
USB3_PHY DPLL Locked Mode
28.2.4.3.6.4
USB3_PHY DPLL Idle-Bypass Mode
28.2.4.3.6.5
USB3_PHY DPLL MN-Bypass Mode
28.2.4.3.6.6
USB3_PHY DPLL Error Conditions
28.2.4.3.7
USB3_PHY PLL Controller Functions
28.2.4.3.7.1
USB3_PHY PLL Controller Register Access
28.2.4.3.7.2
4936
28.2.4.3.7.3
USB3_PHY DPLL Clock Programming Sequence
28.2.4.3.7.4
USB3_PHY DPLL Recommended Values
28.2.5
USB3_PHY Subsystem Low-Level Programming Model
28.3
USB3 PHY and SATA PHY Register Manual
28.3.1
USB3 PHY and SATA PHY Instance Summary
28.3.2
USB3_PHY_RX Registers
28.3.2.1
USB3_PHY_RX Register Summary
28.3.2.2
USB3_PHY_RX Register Description
28.3.3
USB3_PHY_TX Registers
28.3.3.1
USB3_PHY_TX Register Summary
28.3.3.2
USB3_PHY_TX Register Description
28.3.4
SATA_PHY_RX Registers
28.3.4.1
SATA_PHY_RX Register Summary
28.3.4.2
SATA_PHY_RX Register Description
28.3.5
SATA_PHY_TX Registers
28.3.5.1
SATA_PHY_TX Register Summary
28.3.5.2
SATA_PHY_TX Register Description
28.3.6
DPLLCTRL Registers
28.3.6.1
DPLLCTRL Register Summary
28.3.6.2
DPLLCTRL Register Description
28.4
PCIe PHY Subsystem
28.4.1
PCIe PHY Subsystem Overview
28.4.1.1
PCIe PHY Subsystem Key Features
28.4.2
PCIe PHY Subsystem Environment
28.4.2.1
PCIe PHY I/O Signals
28.4.3
PCIe Shared PHY Subsystem Integration
28.4.4
PCIe PHY Subsystem Functional Description
28.4.4.1
PCIe PHY Subsystem Block Diagram
28.4.4.2
OCP2SCP Functional Description
28.4.4.2.1
OCP2SCP Reset
28.4.4.2.1.1
Hardware Reset
28.4.4.2.1.2
Software Reset
28.4.4.2.2
OCP2SCP Power Management
28.4.4.2.2.1
Idle Mode
28.4.4.2.2.2
Clock Gating
28.4.4.2.3
OCP2SCP Timing Registers
28.4.4.3
PCIe PHY Serializer and Deserializer Functional Descriptions
28.4.4.3.1
PCIe PHY Module Resets
28.4.4.3.1.1
Hardware Reset
28.4.4.3.1.2
Software Reset
28.4.4.3.2
PCIe PHY Subsystem Clocking
28.4.4.3.2.1
PCIe PHY Subsystem Input Clocks
28.4.4.3.2.2
PCIe PHY Subsystem Output Clocks
28.4.4.3.3
PCIe PHY Power Management
28.4.4.3.3.1
PCIe PHY Power-Up/-Down Sequences
28.4.4.3.3.2
PCIe PHY Low-Power Modes
28.4.4.3.3.3
Clock Gating
28.4.4.3.4
PCIe PHY Hardware Requests
28.4.4.4
PCIe PHY Clock Generator Subsystem Functional Description
28.4.4.4.1
PCIe PHY DPLL Clock Generator
28.4.4.4.1.1
PCIe PHY DPLL Clock Generator Overview
28.4.4.4.1.2
PCIe PHY DPLL Clock Generator Reset
28.4.4.4.1.3
PCIe PHY DPLL Low-Power Modes
28.4.4.4.1.4
PCIe PHY DPLL Clocks Configuration
28.4.4.4.1.4.1
PCIe PHY DPLL Input Clock Control
28.4.4.4.1.4.2
PCIe PHY DPLL Output Clock Configuration
28.4.4.4.1.4.2.1
PCIe PHY DPLL Output Clock Gating
28.4.4.4.1.5
PCIe PHY DPLL Subsystem Architecture
28.4.4.4.1.6
PCIe PHY DPLL Clock Generator Modes and State Transitions
28.4.4.4.1.6.1
PCIe PHY Clock Generator Power Up
28.4.4.4.1.6.2
PCIe PHY DPLL Sequences
28.4.4.4.1.6.3
PCIe PHY DPLL Locked Mode
28.4.4.4.1.6.4
PCIe PHY DPLL Idle-Bypass Mode
28.4.4.4.1.6.5
PCIe PHY DPLL Low Power Stop Mode
28.4.4.4.1.6.6
PCIe PHY DPLL Clock Programming Sequence
28.4.4.4.1.6.7
PCIe PHY DPLL Recommended Values
28.4.4.4.2
PCIe PHY APLL Clock Generator
28.4.4.4.2.1
PCIe PHY APLL Clock Generator Overview
28.4.4.4.2.2
PCIe PHY APLL Clock Generator Reset
28.4.4.4.2.3
PCIe PHY APLL Low-Power Mode
28.4.4.4.2.4
PCIe PHY APLL Clocks Configuration
28.4.4.4.2.4.1
PCIe PHY APLL Input Clock Control
28.4.4.4.2.4.2
PCIe PHY APLL Output Clock Configuration
28.4.4.4.2.4.2.1
PCIe PHY APLL Output Clock Gating
28.4.4.4.2.5
PCIe PHY APLL Subsystem Architecture
28.4.4.4.2.6
PCIe PHY APLL Clock Generator Modes and State Transitions
28.4.4.4.2.6.1
PCIe PHY APLL Clock Generator Power Up
28.4.4.4.2.6.2
PCIe PHY APLL Sequences
28.4.4.4.2.6.3
PCIe PHY APLL Locked Mode
28.4.4.4.3
ACSPCIE reference clock buffer
28.4.5
PCIePHY Subsystem Low-Level Programming Model
28.4.6
PCIe PHY Subsystem Register Manual
28.4.6.1
PCIe PHY Instance Summary
28.4.6.1.1
PCIe_PHY_RX Registers
28.4.6.1.1.1
PCIe_PHY_RX Register Summary
28.4.6.1.1.2
PCIe_PHY_RX Register Description
28.4.6.1.2
PCIe_PHY_TX Registers
28.4.6.1.2.1
PCIe_PHY_TX Register Summary
28.4.6.1.2.2
PCIe_PHY_TX Register Description
28.4.6.1.3
OCP2SCP Registers
28.4.6.1.3.1
OCP2SCP Register Summary
28.4.6.1.3.2
OCP2SCP Register Description
29
General-Purpose Interface
29.1
General-Purpose Interface Overview
29.2
General-Purpose Interface Environment
29.2.1
General-Purpose Interface as a Keyboard Interface
29.2.2
General-Purpose Interface Signals
29.3
General-Purpose Interface Integration
29.4
General-Purpose Interface Functional Description
29.4.1
General-Purpose Interface Block Diagram
29.4.2
General-Purpose Interface Interrupt and Wake-Up Features
29.4.2.1
Synchronous Path: Interrupt Request Generation
29.4.2.2
Asynchronous Path: Wake-Up Request Generation
29.4.2.3
Wake-Up Event Conditions During Transition To/From IDLE State
29.4.2.4
Interrupt (or Wake-Up) Line Release
29.4.3
General-Purpose Interface Clock Configuration
29.4.3.1
Clocking
29.4.4
General-Purpose Interface Hardware and Software Reset
29.4.5
General-Purpose Interface Power Management
29.4.5.1
Power Domain
29.4.5.2
Power Management
29.4.5.2.1
Idle Scheme
29.4.5.2.2
Operating Modes
29.4.5.2.3
System Power Management and Wakeup
29.4.5.2.4
Module Power Saving
29.4.6
General-Purpose Interface Interrupt and Wake-Up Requests
29.4.6.1
Interrupt Requests Generation
29.4.6.2
Wake-Up Requests Generation
29.4.7
General-Purpose Interface Channels Description
29.4.8
General-Purpose Interface Data Input/Output Capabilities
29.4.9
General-Purpose Interface Set-and-Clear Protocol
29.4.9.1
Description
29.4.9.2
Clear Instruction
29.4.9.2.1
Clear Register Addresses
29.4.9.2.2
Clear Instruction Example
29.4.9.3
Set Instruction
29.4.9.3.1
Set Register Addresses
29.4.9.3.2
Set Instruction Example
29.5
General-Purpose Interface Programming Guide
29.5.1
General-Purpose Interface Low-Level Programming Models
29.5.1.1
Global Initialization
29.5.1.1.1
Surrounding Modules Global Initialization
29.5.1.1.2
General-Purpose Interface Module Global Initialization
29.5.1.2
General-Purpose Interface Operational Modes Configuration
29.5.1.2.1
General-Purpose Interface Read Input Register
29.5.1.2.2
General-Purpose Interface Set Bit Function
29.5.1.2.3
General-Purpose Interface Clear Bit Function
29.6
General-Purpose Interface Register Manual
29.6.1
General-Purpose Interface Instance Summary
29.6.2
General-Purpose Interface Registers
29.6.2.1
General-Purpose Interface Register Summary
29.6.2.2
General-Purpose Interface Register Description
30
Keyboard Controller
30.1
Keyboard Controller Overview
30.2
Keyboard Controller Environment
30.2.1
Keyboard Controller Functions/Modes
30.2.2
Keyboard Controller Signals
30.2.3
Protocols and Data Formats
30.3
Keyboard Controller Integration
30.4
Keyboard Controller Functional Description
30.4.1
Keyboard Controller Block Diagram
30.4.2
Keyboard Controller Software Reset
30.4.3
Keyboard Controller Power Management
30.4.4
Keyboard Controller Interrupt Requests
30.4.5
Keyboard Controller Software Mode
30.4.6
Keyboard Controller Hardware Decoding Modes
30.4.6.1
Functional Modes
30.4.6.2
Keyboard Controller Timer
30.4.6.3
State-Machine Status
30.4.6.4
Keyboard Controller Interrupt Generation
30.4.6.4.1
Interrupt-Generation Scheme
30.4.6.4.2
Keyboard Buffer and Missed Events (Overrun Feature)
30.4.7
Keyboard Controller Key Coding Registers
30.4.8
Keyboard Controller Register Access
30.4.8.1
Write Registers Access
30.4.8.2
Read Registers Access
30.5
Keyboard Controller Programming Guide
30.5.1
Keyboard Controller Low-Level Programming Models
30.5.1.1
Global Initialization
30.5.1.1.1
Surrounding Modules Global Initialization
30.5.1.1.2
Keyboard Controller Global Initialization
30.5.1.1.2.1
Main Sequence – Keyboard Controller Global Initialization
30.5.1.2
Operational Modes Configuration
30.5.1.2.1
Keyboard Controller in Hardware Decoding Mode (Default Mode)
30.5.1.2.1.1
Main Sequence – Keyboard Controller Hardware Mode
30.5.1.2.2
Keyboard Controller Software Scanning Mode
30.5.1.2.2.1
Main Sequence – Keyboard Controller Software Mode
30.5.1.2.3
Using the Timer
30.5.1.2.4
State-Machine Status Register
30.5.1.3
Keyboard Controller Events Servicing
30.6
Keyboard Controller Register Manual
30.6.1
Keyboard Controller Instance Summary
30.6.2
Keyboard Controller Registers
30.6.2.1
Keyboard Controller Register Summary
30.6.2.2
Keyboard Controller Register Description
31
Pulse-Width Modulation Subsystem
31.1
PWM Subsystem Resources
31.1.1
PWMSS Overview
31.1.1.1
PWMSS Key Features
31.1.1.2
PWMSS Unsupported Fetaures
31.1.2
PWMSS Environment
31.1.2.1
PWMSS I/O Interface
31.1.3
PWMSS Integration
31.1.3.1
PWMSS Module Interfaces Implementation
31.1.3.1.1
Device Specific PWMSS Features
31.1.3.1.2
Daisy-Chain Connectivity between PWMSS Modules
31.1.3.1.3
eHRPWM Modules Time Base Clock Gating
31.1.4
PWMSS Subsystem Power, Reset and Clock Configuration
31.1.4.1
PWMSS Local Clock Management
31.1.4.2
PWMSS Modules Local Clock Gating
31.1.4.3
PWMSS Software Reset
31.1.5
PWMSS_CFG Register Manual
31.1.5.1
PWMSS_CFG Instance Summary
31.1.5.2
PWMSS_CFG Registers
31.1.5.2.1
PWMSS_CFG Register Summary
31.1.5.2.2
PWMSS_CFG Register Description
31.2
Enhanced PWM (ePWM) Module
31.3
Enhanced Capture (eCAP) Module
31.4
Enhanced Quadrature Encoder Pulse (eQEP) Module
32
Viterbi-Decoder Coprocessor
32.1
VCP Overview
32.1.1
VCP Features
32.2
VCP Integration
32.3
VCP Functional Description
32.3.1
VCP Block Diagram
32.3.2
VCP Internal Interfaces
32.3.2.1
VCP Power Management
32.3.2.1.1
Idle Mode
32.3.2.2
VCP Clocks
32.3.2.3
VCP Resets
32.3.2.4
Interrupt Requests
32.3.2.5
EDMA Requests
32.3.3
Functional Overview
32.3.3.1
Theoretical Basics of the Convolutional Code.
32.3.3.2
5161
32.3.4
VCP Architecture
32.3.4.1
Sliding Windows Processing
32.3.4.1.1
Tailed Traceback Mode
32.3.4.1.2
Mixed Traceback Mode
32.3.4.1.3
Convergent Traceback Mode
32.3.4.1.4
F, R, and C Limitations
32.3.4.1.5
Yamamoto Parameters
32.3.4.1.6
Input FIFO (Branch Metrics)
32.3.4.1.7
Output FIFO (Decisions)
32.3.5
VCP Input Data
32.3.5.1
Branch Metrics Calculations
32.3.6
Soft Input Dynamic Ranges
32.3.7
VCP Memory Sleep Mode
32.3.8
Decision Data
32.3.9
Endianness
32.3.9.1
Branch Metrics
32.3.9.1.1
Hard Decisions
32.3.9.1.2
Soft Decisions
32.3.10
VCP Output Parameters
32.3.11
Event Generation
32.3.11.1
VCPnXEVT Generation
32.3.11.2
VCPnREVT Generation
32.3.12
Operational Modes
32.3.12.1
Debugging Features
32.3.13
Errors and Status
32.4
VCP Modules Programming Guide
32.4.1
EDMA Resources
32.4.1.1
VCP1 and VCP2 Dedicated EDMA Resources
32.4.1.2
Special VCP EDMA Programming Considerations
32.4.1.2.1
Input Configuration Parameters Transfer
32.4.1.2.2
Branch Metrics Transfer
32.4.1.2.3
Decisions Transfer
32.4.1.2.4
Hard-Decisions Mode
32.4.1.2.5
Soft-Decisions Mode
32.4.1.2.6
Output Parameters Transfer
32.4.2
Input Configuration Words
32.5
VCP Register Manual
32.5.1
VCP1 and VCP2 Instance Summary
32.5.2
VCP Registers
32.5.2.1
VCP Register Summary
32.5.2.2
VCP1 and VCP2 Data Registers Description
32.5.2.3
VCP1 and VCP2 Configuration Registers Description
33
Audio Tracking Logic
33.1
ATL Overview
33.2
ATL Environment
33.2.1
ATL Functions
33.2.2
ATL Signals Descriptions
33.3
ATL Integration
33.3.1
ATL Distribution on Interconnects
33.3.2
ATL Regions Allocations
33.4
ATL Functional Description
33.4.1
Block Diagram
33.4.2
Source Signal Control
33.4.3
ATL Clock and Reset Configuration
33.5
ATL Register Manual
33.5.1
ATL Instance Summary
33.5.2
ATL Register Summary
33.5.3
ATL Register Description
34
Initialization
34.1
Initialization Overview
34.1.1
Terminology
34.1.2
Initialization Process
34.2
Preinitialization
34.2.1
Power Requirements
34.2.2
Interaction With the PMIC Companion
34.2.3
Clock, Reset, and Control
34.2.3.1
Overview
34.2.3.2
Clocking Scheme
34.2.3.3
Reset Configuration
34.2.3.3.1
ON/OFF Interconnect and Power-On-Reset
34.2.3.3.2
Warm Reset
34.2.3.3.3
Peripheral Reset by GPIO
34.2.3.3.4
Warm Reset Impact on GPIOs
34.2.3.4
PMIC Control
34.2.3.5
PMIC Request Signals
34.2.4
Sysboot Configuration
34.2.4.1
GPMC Configuration for XIP/NAND
34.2.4.2
System Clock Speed Selection
34.2.4.3
QSPI Redundant SBL Images Offset
34.2.4.4
Booting Device Order Selection
34.2.4.5
5242
34.2.4.6
Boot Peripheral Pin Multiplexing
34.3
Device Initialization by ROM Code
34.3.1
Booting Overview
34.3.1.1
Booting Types
34.3.1.2
ROM Code Architecture
34.3.2
Memory Maps
34.3.2.1
ROM Memory Map
34.3.2.2
RAM Memory Map
34.3.3
Overall Booting Sequence
34.3.4
Startup and Configuration
34.3.4.1
Startup
34.3.4.2
Control Module Configuration
34.3.4.3
PRCM Module Mode Configuration
34.3.4.4
Clocking Configuration
34.3.4.5
Booting Device List Setup
34.3.5
Peripheral Booting
34.3.5.1
Description
34.3.5.2
Initialization Phase for UART Boot
34.3.5.3
Initialization Phase for USB Boot
34.3.5.3.1
Initialization Procedure
34.3.5.3.2
SATA Peripheral Device Flashing over USB Interface
34.3.5.3.3
USB Driver Descriptors
34.3.5.3.4
5265
34.3.5.3.5
USB Customized Vendor and Product IDs
34.3.5.3.6
USB Driver Functionality
34.3.6
Fast External Booting
34.3.6.1
Overview
34.3.6.2
Fast External Booting Procedure
34.3.7
Memory Booting
34.3.7.1
Overview
34.3.7.2
Non-XIP Memory
34.3.7.3
XIP Memory
34.3.7.3.1
GPMC Initialization
34.3.7.4
NAND
34.3.7.4.1
Initialization and NAND Detection
34.3.7.4.2
NAND Read Sector Procedure
34.3.7.5
SPI/QSPI Flash Devices
34.3.7.6
eMMC Memories and SD Cards
34.3.7.6.1
eMMC Memories
34.3.7.6.1.1
System Conditions and Limitations
34.3.7.6.1.2
eMMC Memory Connection
34.3.7.6.2
SD Cards
34.3.7.6.2.1
System Conditions and Limitations
34.3.7.6.2.2
SD Card Connection
34.3.7.6.2.3
Booting Procedure
34.3.7.6.2.4
eMMC Partitions Handling in Alternative Boot Operation Mode
34.3.7.6.2.4.1
eMMC Devices Preflashing
34.3.7.6.2.4.2
eMMC Device State After ROM Code Execution
34.3.7.6.2.4.3
Consideration on device Global Warm Reset
34.3.7.6.2.4.4
Booting Image Size
34.3.7.6.2.4.5
Booting Image Layout
34.3.7.6.3
Initialization and Detection
34.3.7.6.4
Read Sector Procedure
34.3.7.6.5
File System Handling
34.3.7.6.5.1
MBR and FAT File System
34.3.7.7
SATA Device Boot Operation
34.3.7.7.1
SATA Booting Overview
34.3.7.7.2
SATA Power-Up Initialization Sequence
34.3.7.7.3
System Conditions and Limitations for SATA Boot
34.3.7.7.4
SATA Read Sector Procedure in FAT Mode
34.3.8
Image Format
34.3.8.1
Overview
34.3.8.2
Configuration Header
34.3.8.2.1
CHSETTINGS Item
34.3.8.2.2
CHFLASH Item
34.3.8.2.3
CHMMCSD Item
34.3.8.2.4
CHQSPI Item
34.3.8.3
GP Header
34.3.8.4
Image Execution
34.3.9
Tracing
34.4
Services for HLOS Support
34.4.1
Hypervisor
34.4.2
Caches Maintenance
34.4.3
CP15 Registers
34.4.4
Wakeup Generator
34.4.5
Arm Timer
34.4.6
MReq Domain
35
On-Chip Debug Support
35.1
Introduction
35.1.1
Key Features
35.2
Debug Interfaces
35.2.1
IEEE1149.1
35.2.2
Debug (Trace) Port
35.2.3
Trace Connector and Board Layout Considerations
35.3
Debugger Connection
35.3.1
ICEPick Module
35.3.2
ICEPick Boot Modes
35.3.2.1
Default Boot Mode
35.3.2.2
Wait-In-Reset
35.3.3
Dynamic TAP Insertion
35.3.3.1
ICEPick Secondary TAPs
35.4
Primary Debug Support
35.4.1
Processor Native Debug Support
35.4.1.1
Cortex-A15 Processor
35.4.1.2
Cortex-M4 Processor
35.4.1.3
DSP C66x
35.4.1.4
IVA Arm968
35.4.1.5
ARP32
35.4.1.6
5341
35.4.2
Cross-Triggering
35.4.2.1
SoC-Level Cross-Triggering
35.4.2.2
Cross-Triggering With External Device
35.4.3
Suspend
35.4.3.1
Debug Aware Peripherals and Host Processors
35.5
Real-Time Debug
35.5.1
Real-Time Debug Events
35.5.1.1
Emulation Interrupts
35.6
Power, Reset, and Clock Management Debug Support
35.6.1
Power and Clock Management
35.6.1.1
Power and Clock Control Override From Debugger
35.6.1.1.1
Debugger Directives
35.6.1.1.1.1
FORCEACTIVE Debugger Directive
35.6.1.1.1.2
INHIBITSLEEP Debugger Directive
35.6.1.1.2
Intrusive Debug Model
35.6.1.2
Debug Across Power Transition
35.6.1.2.1
Nonintrusive Debug Model
35.6.1.2.2
Debug Context Save and Restore
35.6.1.2.2.1
Debug Context Save
35.6.1.2.2.2
Debug Context Restore
35.6.2
Reset Management
35.6.2.1
Debugger Directives
35.6.2.1.1
Assert Reset
35.6.2.1.2
Block Reset
35.6.2.1.3
Wait-In-Reset
35.7
Performance Monitoring
35.7.1
MPU Subsystem Performance Monitoring
35.7.1.1
Performance Monitoring Unit
35.7.1.2
L2 Cache Controller
35.7.2
IPU Subsystem Performance Monitoring
35.7.2.1
Subsystem Counter Timer Module
35.7.2.2
Cache Events
35.7.3
DSP Subsystem Performance Monitoring
35.7.3.1
Advanced Event Triggering
35.7.4
EVE Subsystem Performance Monitoring
35.7.4.1
EVE Subsystem Counter Timer Module
35.7.4.2
EVE Subsystem SCTM Events
35.8
MPU Memory Adaptor (MPU_MA) Watchpoint
35.9
Processor Trace
35.9.1
Cortex-A15 Processor Trace
35.9.2
DSP Processor Trace
35.9.3
Trace Export
35.9.3.1
Trace Exported to External Trace Receiver
35.9.3.2
Trace Captured Into On-Chip Trace Buffer
35.9.3.3
Trace Exported Through USB
35.10
System Instrumentation
35.10.1
MIPI STM (CT_STM)
35.10.2
System Trace Export
35.10.2.1
CT_STM ATB Export
35.10.2.2
Trace Streams Interleaving
35.10.3
Software Instrumentation
35.10.3.1
MPU Software Instrumentation
35.10.3.2
SoC Software Instrumentation
35.10.4
OCP Watchpoint
35.10.4.1
OCP Target Traffic Monitoring
35.10.4.2
Messages Triggered from System Events
35.10.4.3
DMA Transfer Profiling
35.10.5
IVA Pipeline
35.10.6
EVE SMSET
35.10.7
L3 NOC Statistics Collector
35.10.7.1
L3 Target Load Monitoring
35.10.7.2
L3 Master Latency Monitoring
35.10.7.2.1
SC_LAT0 Configuration
35.10.7.2.2
SC_LAT1 Configuration
35.10.7.2.3
SC_LAT2 Configuration
35.10.7.2.4
SC_LAT3 Configuration
35.10.7.2.5
SC_LAT4 Configuration
35.10.7.2.6
SC_LAT5 Configuration
35.10.7.2.7
SC_LAT6 Configuration
35.10.7.2.8
SC_LAT7 Configuration
35.10.7.2.9
SC_LAT8 Configuration
35.10.7.2.10
Statistics Collector Alarm Mode
35.10.7.2.11
Statistics Collector Suspend Mode
35.10.8
PM Instrumentation
35.10.9
CM Instrumentation
35.10.10
Master-ID Encoding
35.10.10.1
Software Masters
35.10.10.2
Hardware Masters
35.11
Concurrent Debug Modes
35.12
DRM Register Manual
35.12.1
DRM Instance Summary
35.12.2
DRM Registers
35.12.2.1
DRM Register Summary
35.12.2.2
DRM Register Description
36
Revision History
28.4.4.2.1
OCP2SCP Reset