SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4C00 0000 0x4D00 0000 | Instance | EMIF1 EMIF2 |
Description | Revision number register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | Module revision | R | 0x- (1) |
EMIF Controller |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4C00 0004 0x4D00 0004 | Instance | EMIF1 EMIF2 |
Description | SDRAM Status Register (STATUS) | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BE | DUAL_CLK_MODE | FAST_INIT | RESERVED | RDLVLGATETO | RDLVLTO | WRLVLTO | RESERVED | PHY_DLL_READY | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | BE | Big endian mode select for 8 and 16-bit devices, set to 1 for big endian or 0 for little endian operation. In current implementation, only 32-bit devices are supported - this bit is don't care. | R | 0 |
30 | DUAL_CLK_MODE | Dual Clock mode. Defines whether the EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous. EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous, if set to 1. | R | 0 |
29 | FAST_INIT | Fast Init. Defines whether the EMIF fast initialization mode has been enabled. Fast initialization is enabled if set to 1. | R | 0 |
28:7 | RESERVED | Reserved | R | 0x00 0000 |
6 | RDLVLGATETO | Read DQS Gate Training Timeout. Value of 1 indicates read DQS gate training has timed out because read DQS gate training done was not received from the PHY. | R | 0 |
5 | RDLVLTO | Read Data Eye Training Timeout. Value of 1 indicates read data eye training has timed out because read data eye training done was not received from the PHY. | R | 0 |
4 | WRLVLTO | Write Leveling Timeout. Value of 1 indicates write leveling has timed out because write leveling done was not received from the PHY. | R | 0 |
3 | RESERVED | R | 0 | |
2 | PHY_DLL_READY | DDR PHY Ready. The DDR PHY is ready for normal operation, if set to 1. | R | 0 |
1:0 | RESERVED | Reserved | R | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4C00 0008 0x4D00 0008 | Instance | EMIF1 EMIF2 |
Description | SDRAM Config Register. A write to this register will cause the EMIF to start the SDRAM initialization sequence. CAUTION: This register is loaded with values by control module at device reset. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDRAM_TYPE | IBANK_POS | DDR_TERM | DDR2_DDQS | DYN_ODT | DDR_DISABLE_DLL | SDRAM_DRIVE | CWL | NARROW_MODE | CL | ROWSIZE | IBANK | RESERVED | PAGESIZE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | SDRAM_TYPE | SDRAM Type selection. This field is loaded from e-fuse. Set to 2 for DDR2 Set to 3 for DDR3 All other values are reserved. | RW | 0x0 |
28:27 | IBANK_POS | Internal bank position. See Section 17.3.4.12, SDRAM Address Mapping. | RW | 0x0 |
26:24 | DDR_TERM | DDR3 termination resistor value. Set to 0 to disable termination. For DDR3, set to 1 for RZQ/4, set to 2 for RZQ/2, set to 3 for RZQ/6, set to 4 for RZQ/12, and set to 5 for RZQ/8. All other values are reserved. | RW | 0x0 |
23 | DDR2_DDQS | DDR2 differential DDQS enable. NOT SUPPORTED. Set to 1 for compatibility. | RW | 0 |
22:21 | DYN_ODT | DDR3 Dynamic ODT. NOT SUPPORTED. Set to 0 to turn off dynamic ODT. | RW | 0x0 |
20 | DDR_DISABLE_DLL | Disable DLL select. Set to 1 to disable DLL inside SDRAM. | RW | 0 |
19:18 | SDRAM_DRIVE | SDRAM drive strength.For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. All other values are reserved. | RW | 0x0 |
17:16 | CWL | DDR3 CAS Write latency. Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved. | RW | 0x0 |
15:14 | NARROW_MODE | SDRAM data bus width. Set to 0 for 32-bit data bus width. Set to 1 for 16-bit data bus width. All other values are reserved. | RW | 0x0 |
13:10 | CL | CAS Latency (referred to as read latency (RL) in some SDRAM specs). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Values of 2, 3, 4 and 5 (CAS latency of 2, 3, 4 and 5) are supported for DDR2. Values of 2, 4, 6, 8, 10, 12 and 14 (CAS latency of 5, 6, 7, 8, 9, 10 and 11) are supported for DDR3. All other values are reserved. | RW | 0x0 |
9:7 | ROWSIZE | Row Size. Defines the number of row address bits of connected SDRAM devices. Set to 0 for 9 row bits, Set to 1 for 10 row bits, Set to 2 for 11 row bits, Set to 3 for 12 row bits, Set to 4 for 13 row bits, Set to 5 for 14 row bits, Set to 6 for 15 row bits, Set to 7 for 16 row bits. This field is only used when EMIF_SDRAM_CONFIG[28:27] IBANK_POS field is set to 1, 2, or 3 or EBANK_POS field in EMIF_SDRAM_CONFIG_2 register is set to 1. | RW | 0x0 |
6:4 | IBANK | Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, Set to 1 for 2 banks, Set to 2 for 4 banks, Set to 3 for 8 banks. All other values are reserved. | RW | 0x0 |
3 | RESERVED | R | 0 | |
2:0 | PAGESIZE | Page Size. Defines the internal page size of connected SDRAM devices. Set to 0 for 256-word page (8 column bits), Set to 1 for 512-word page (9 column bits), Set to 2 for 1024-word page (10 column bits), Set to 3 for 2048-word page (11 column bits). All other values are reserved. | RW | 0x0 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4C00 000C 0x4D00 000C | Instance | EMIF1 EMIF2 |
Description | SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EBANK_POS | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27 | EBANK_POS | External bank position. Set to 0 to assign external bank address bits from lower OCP address. Set to 1 to assign external bank address bits from higher OCP address bits. See Section 17.3.4.12, SDRAM Address Mapping. | RW | 0 |
26:0 | RESERVED | R | 0x00 0000 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4C00 0010 0x4D00 0010 | Instance | EMIF1 EMIF2 |
Description | SDRAM Refresh Control Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITREF_DIS | RESERVED | SRT | ASR | RESERVED | PASR | RESERVED | REFRESH_RATE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INITREF_DIS | Initialization and Refresh disable. When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions. | RW | 1 |
30 | RESERVED | R | 0 | |
29 | SRT | DDR3 Self Refresh temperature range. Set to 0 for normal operating temperature range and set to 1 for extended operating temperature range when the ASR field is set to 0. This bit must be set to 0 if the ASR field is set to 1. A write to this field will cause the EMIF to start the SDRAM initialization sequence. | RW | 0 |
28 | ASR | DDR3 Auto Self Refresh enable. Set to 1 for auto Self Refresh enable. Set to 0 for manual Self Refresh reference indicated by the SRT field. A write to this field will cause the EMIF to start the SDRAM initialization sequence. | RW | 0 |
27 | RESERVED | R | 0 | |
26:24 | PASR | Partial Array Self Refresh. These bits get loaded into the Extended Mode Register of DDR3 during initialization. For DDR3, set to 0 for full array, set to 1 or 5 for 1/2 array, set to 2 or 6 for 1/4 array, set to 3 or 7 for 1/8 array, and set to 4 for 3/4 array to be refreshed. All other values are reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence. | RW | 0x0 |
23:16 | RESERVED | R | 0x00 | |
15:0 | REFRESH_RATE | Refresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = REFRESH_RATE / EMIF_PHY_FCLK. A 533-MHz DDR clock rate system that requires a 7.8 µs refresh rate would need 7.8 × 533 = 4157 or 0x103D value to be written. To avoid lock-up situations, the programmer must not program REFRESH_RATE < (6 × EMIF_SDRAM_TIMING_3[12:4] T_RFC). Note: NOTE: The SDRAM refresh rate can be changed on-the-fly by writing to this field. When changing the SDRAM refresh rate all timing parameters that use the refresh rate value have to be recalculated. For example, tRASmax specified in the EMIF_SDRAM_TIMING_3[3:0] T_RAS_MAX field must be recalculated. | RW | 0x0000 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4C00 0014 0x4D00 0014 | Instance | EMIF1 EMIF2 |
Description | SDRAM Refresh Control Shadow Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REFRESH_RATE_SHDW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | Reserved | R | 0x0000 |
15:0 | REFRESH_RATE_SHDW | Shadow field for REFRESH_RATE. This field is loaded into EMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE field when SIdleAck is asserted. | RW | 0x0000 |
EMIF Controller |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4C00 0018 0x4D00 0018 | Instance | EMIF1 EMIF2 |
Description | SDRAM Timing 1 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_RTW | T_RP | T_RCD | T_WR | T_RAS | T_RC | T_RRD | T_WTR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | T_RTW | Minimum number of DDR clock cycles between Read to Write data phases, minus one. | RW | 0x0 |
28:25 | T_RP | Minimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one. | RW | 0x0 |
24:21 | T_RCD | Minimum number of DDR clock cycles from Activate to Read or Write, minus one. | RW | 0x0 |
20:17 | T_WR | Minimum number of DDR clock cycles from last Write transfer to Precharge, minus one. | RW | 0x0 |
16:12 | T_RAS | Minimum number of DDR clock cycles from Activate to Precharge, minus one. T_RAS value needs to be bigger than or equal to T_RDC value. | RW | 0x00 |
11:6 | T_RC | Minimum number of DDR clock cycles from Activate to Activate, minus one. | RW | 0x00 |
5:3 | T_RRD | Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one. For an 8-bank, this field must be equal to ((tFAW / (4 × tCK)) - 1). | RW | 0x0 |
2:0 | T_WTR | Minimum number of DDR clock cycles from last Write to Read, minus one. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4C00 001C 0x4D00 001C | Instance | EMIF1 EMIF2 |
Description | SDRAM Timing 1 Shadow Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_RTW_SHDW | T_RP_SHDW | T_RCD_SHDW | T_WR_SHDW | T_RAS_SHDW | T_RC_SHDW | T_RRD_SHDW | T_WTR_SHDW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | T_RTW_SHDW | Shadow field for T_RTW. This field is loaded into EMIF_SDRAM_TIMING_1[31:29] T_RTW field when SIdleAck is asserted. | RW | 0x0 |
28:25 | T_RP_SHDW | Shadow field for T_RP. This field is loaded into EMIF_SDRAM_TIMING_1[28:25] T_RP field when SIdleAck is asserted. | RW | 0x0 |
24:21 | T_RCD_SHDW | Shadow field for T_RCD. This field is loaded into EMIF_SDRAM_TIMING_1[24:21] T_RCD field when SIdleAck is asserted. | RW | 0x0 |
20:17 | T_WR_SHDW | Shadow field for T_WR. This field is loaded into EMIF_SDRAM_TIMING_1[20:17] T_WR field when SIdleAck is asserted. | RW | 0x0 |
16:12 | T_RAS_SHDW | Shadow field for T_RAS. This field is loaded into EMIF_SDRAM_TIMING_1[16:12] T_RAS field when SIdleAck is asserted. | RW | 0x00 |
11:6 | T_RC_SHDW | Shadow field for T_RC. This field is loaded into EMIF_SDRAM_TIMING_1[11:6] T_RC field when SIdleAck is asserted. | RW | 0x00 |
5:3 | T_RRD_SHDW | Shadow field for T_RRD. This field is loaded into EMIF_SDRAM_TIMING_1[5:3] T_RRD field when SIdleAck is asserted. | RW | 0x0 |
2:0 | T_WTR_SHDW | Shadow field for T_WTR. This field is loaded into EMIF_SDRAM_TIMING_1[2:0] T_WTR field when SIdleAck is asserted. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4C00 0020 0x4D00 0020 | Instance | EMIF1 EMIF2 |
Description | SDRAM Timing 2 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | T_XP | RESERVED | T_XSNR | T_XSRD | T_RTP | T_CKE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | Reserved | R | 0 |
30:28 | T_XP | Minimum number of DDR clock cycles from power-down exit to any command other than a read command, minus one. | RW | 0x0 |
27:25 | RESERVED | Reserved | RW | 0x0 |
24:16 | T_XSNR | Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command, minus one. | RW | 0x000 |
15:6 | T_XSRD | Minimum number of DDR clock cycles from Self-Refresh exit to a Read command, minus one. | RW | 0x000 |
5:3 | T_RTP | Minimum number of DDR clock cycles for the last read command to a Precharge command, minus one. | RW | 0x0 |
2:0 | T_CKE | Minimum number of DDR clock cycles between CKE pin changes, minus one. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4C00 0024 0x4D00 0024 | Instance | EMIF1 EMIF2 |
Description | SDRAM Timing 2 Shadow Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | T_XP_SHDW | RESERVED | T_XSNR_SHDW | T_XSRD_SHDW | T_RTP_SHDW | T_CKE_SHDW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | Reserved | R | 0 |
30:28 | T_XP_SHDW | Shadow field for T_XP. This field is loaded into EMIF_SDRAM_TIMING_2[30:28] T_XP field when SIdleAck is asserted. | RW | 0x0 |
27:25 | RESERVED | Reserved | RW | 0x0 |
24:16 | T_XSNR_SHDW | Shadow field for T_XSNR. This field is loaded into EMIF_SDRAM_TIMING_2[24:16] T_XSNR field when SIdleAck is asserted. | RW | 0x000 |
15:6 | T_XSRD_SHDW | Shadow field for T_XSRD. This field is loaded into EMIF_SDRAM_TIMING_2[15:6] T_XSRD field when SIdleAck is asserted. | RW | 0x000 |
5:3 | T_RTP_SHDW | Shadow field for T_RTP. This field is loaded into EMIF_SDRAM_TIMING_2[5:3] T_RTP field when SIdleAck is asserted. | RW | 0x0 |
2:0 | T_CKE_SHDW | Shadow field for T_CKE. This field is loaded into EMIF_SDRAM_TIMING_2[2:0] T_CKE field when SIdleAck is asserted. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4C00 0028 0x4D00 0028 | Instance | EMIF1 EMIF2 |
Description | SDRAM Timing 3 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_PDLL_UL | RESERVED | T_CKESR | ZQ_ZQCS | RESERVED | T_RFC | T_RAS_MAX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | T_PDLL_UL | Minimum number of DDR clock cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks. | RW | 0x0 |
27:24 | RESERVED | R | 0x0 | |
23:21 | T_CKESR | Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh, minus one. | RW | 0x0 |
20:15 | ZQ_ZQCS | Number of DDR clock cycles for a ZQCS command, minus one. | RW | 0x00 |
14:13 | RESERVED | R | 0x0 | |
12:4 | T_RFC | Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one. | RW | 0x000 |
3:0 | T_RAS_MAX | Maximum number of REFRESH_RATE intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer. Value for T_RAS_MAX can be calculated as follows: If tRASmax = 120 us and tREFI = 15.7 us, then T_RAS_MAX = ((120/15.7)-1) = 6.64. Round down to the next lower integer. Therefore, the programmed value must be 6. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4C00 002C 0x4D00 002C | Instance | EMIF1 EMIF2 |
Description | SDRAM Timing 3 Shadow Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_PDLL_UL_SHDW | RESERVED | T_CKESR_SHDW | ZQ_ZQCS_SHDW | RESERVED | T_RFC_SHDW | T_RAS_MAX_SHDW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | T_PDLL_UL_SHDW | Shadow field for T_PDLL_UL. This field is loaded into T_PDLL_UL field in EMIF_SDRAM_TIMING_3 register when SIdleAck is asserted. | RW | 0x0 |
27:24 | RESERVED | R | 0x0 | |
23:21 | T_CKESR_SHDW | Shadow field for T_CKESR. This field is loaded into T_CKESR field in EMIF_SDRAM_TIMING_3 register when SIdleAck is asserted. | RW | 0x0 |
20:15 | ZQ_ZQCS_SHDW | Shadow field for ZQ_ZQCS. This field is loaded into ZQ_ZQCS field in EMIF_SDRAM_TIMING_3 register when SIdleAck is asserted. | RW | 0x00 |
14:13 | RESERVED | R | 0x0 | |
12:4 | T_RFC_SHDW | Shadow field for T_RFC. This field is loaded into EMIF_SDRAM_TIMING_3[12:4] T_RFC when SIdleAck is asserted. | RW | 0x000 |
3:0 | T_RAS_MAX_SHDW | Shadow field for T_RAS_MAX. This field is loaded into EMIF_SDRAM_TIMING_3[3:0] T_RAS_MAX field when SIdleAck is asserted. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4C00 0030 0x4D00 0030 | Instance | EMIF1 EMIF2 |
Description | NOTE: This register is not supported. It is kept only for code compatibility. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESERVED | Reserved | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4C00 0034 0x4D00 0034 | Instance | EMIF1 EMIF2 |
Description | NOTE: This register is not supported. It is kept only for code compatibility. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESERVED | Reserved | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4C00 0038 0x4D00 0038 | Instance | EMIF1 EMIF2 |
Description | Power Management Control Register. Updating the *_TIM fields must be followed by at least one access to SDRAM for the new value to take an effect. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PD_TIM | RESERVED | LP_MODE | SR_TIM | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0000 | |
15:12 | PD_TIM | Power Management timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 4. Set to 0 to immediately enter Power-Down mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks. | RW | 0x0 |
11 | RESERVED | R | 0 | |
10:8 | LP_MODE | Automatic Power Management enable. 0x0: Disable automatic power management 0x1: Reserved 0x2: Self Refresh mode 0x3: Disable automatic power management 0x4: Power-Down mode All other values disable automatic power management. | RW | 0x0 |
7:4 | SR_TIM | Power Management timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 2. Set to 0 to immediately enter Self Refresh mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks. | RW | 0x0 |
3:0 | RESERVED | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4C00 003C 0x4D00 003C | Instance | EMIF1 EMIF2 |
Description | Power Management Control Shadow Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PD_TIM_SHDW | RESERVED | SR_TIM_SHDW | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0000 | |
15:12 | PD_TIM_SHDW | Shadow field for PD_TIM. This field is loaded into PD_TIM field in EMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted. | RW | 0x0 |
11:8 | RESERVED | R | 0x0 | |
7:4 | SR_TIM_SHDW | Shadow field for SR_TIM. This field is loaded into SR_TIM field in EMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted. | RW | 0x0 |
3:0 | RESERVED | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4C00 0054 0x4D00 0054 | Instance | EMIF1 EMIF2 |
Description | OCP Config Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYS_THRESH_MAX | MPU_THRESH_MAX | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:24 | SYS_THRESH_MAX | System OCP Threshold Maximum. The number of commands the system interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1. | RW | 0x7 |
23:20 | MPU_THRESH_MAX | MPU Threshold Maximum. The number of commands the MPU interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1. | RW | 0x7 |
19:0 | RESERVED | R | 0x70000 |
EMIF Controller |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4C00 0058 0x4D00 0058 | Instance | EMIF1 EMIF2 |
Description | OCP Config Value 1 Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYS_BUS_WIDTH | RESERVED | WR_FIFO_DEPTH | CMD_FIFO_DEPTH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | SYS_BUS_WIDTH | System OCP data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved | R | 0x2 |
29:16 | RESERVED | R | 0x1000 | |
15:8 | WR_FIFO_DEPTH | Write Data FIFO depth | R | 0xA |
7:0 | CMD_FIFO_DEPTH | Command FIFO depth | R | 0x0A |
EMIF Controller |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4C00 005C 0x4D00 005C | Instance | EMIF1 EMIF2 |
Description | OCP Config Value 2 Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RREG_FIFO_DEPTH | RSD_FIFO_DEPTH | RCMD_FIFO_DEPTH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | Reserved | R | 0x00 |
23:16 | RREG_FIFO_DEPTH | Register Read Data FIFO depth | R | 0x04 |
15:8 | RSD_FIFO_DEPTH | SDRAM Read Data FIFO depth | R | 0x27 |
7:0 | RCMD_FIFO_DEPTH | Read Command FIFO depth | R | 0x27 |
EMIF Controller |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4C00 0060 0x4D00 0060Added registers pertaining to DDR configuration. | Instance | EMIF1 EMIF2 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESET_PHY | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | Reserved. This field must not be modified. | RW | 0x0 |
15 | RESERVED | Reserved | R | 0x0 |
14 | RESERVED | Reserved. This bit must not be modified. | RW | 0x0 |
13 | RESERVED | Reserved. This bit must not be modified. | RW | 0x1 |
12 | RESERVED | Reserved. This bit must not be modified. | RW | 0x0 |
11 | RESERVED | Reserved | R | 0x0 |
10 | RESET_PHY | Reset the DDR PHY. Writing 1 to this bit resets the DDR PHY. This bit will self clear to 0. | RW | 0x0 |
9 | RESERVED | Reserved | R | 0x0 |
8 | RESERVED | Reserved. This bit must not be modified. | RW | 0x0 |
7:6 | RESERVED | Reserved | R | 0x0 |
5:4 | RESERVED | Reserved. This field must not be modified. | RW | 0x1 |
3:1 | RESERVED | Reserved. This field must not be modified. | RW | 0x0 |
0 | RESERVED | Reserved. This bit must not be modified. | RW | 0x1 |
EMIF Controller |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4C00 0080 0x4D00 0080 | Instance | EMIF1 EMIF2 |
Description | Performance Counter 1 Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | COUNTER1 | 32-bit counter that can be configured as specified in the EMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register. | R | 0x0000 0000 |
EMIF Controller |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4C00 0084 0x4D00 0084 | Instance | EMIF1 EMIF2 |
Description | Performance Counter 2 Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | COUNTER2 | 32-bit counter that can be configured as specified in the EMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register. | R | 0x0000 0000 |
EMIF Controller |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4C00 0088 0x4D00 0088 | Instance | EMIF1 EMIF2 |
Description | Performance Counter Config Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNTR2_MCONNID_EN | CNTR2_REGION_EN | RESERVED | CNTR2_CFG | CNTR1_MCONNID_EN | CNTR1_REGION_EN | RESERVED | CNTR1_CFG |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | CNTR2_MCONNID_EN | MConnID filter enable for EMIF_PERFORMANCE_COUNTER_2 register. | RW | 0 |
30 | CNTR2_REGION_EN | Chip Select filter enable for EMIF_PERFORMANCE_COUNTER_2 register. | RW | 0 |
29:20 | RESERVED | Reserved for future use | R | 0x000 |
19:16 | CNTR2_CFG | Filter configuration for EMIF_PERFORMANCE_COUNTER_2. Refer to Table 17-93 for details. | RW | 0x1 |
15 | CNTR1_MCONNID_EN | MConnID filter enable for EMIF_PERFORMANCE_COUNTER_1 register. | RW | 0 |
14 | CNTR1_REGION_EN | Chip Select filter enable for EMIF_PERFORMANCE_COUNTER_1 register. | RW | 0 |
13:4 | RESERVED | Reserved for future use | R | 0x000 |
3:0 | CNTR1_CFG | Filter configuration for EMIF_PERFORMANCE_COUNTER_1. Refer to Table 17-93 for details. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4C00 008C 0x4D00 008C | Instance | EMIF1 EMIF2 |
Description | Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in the ConnID Values table in Chapter 16, Interconnect. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCONNID2 | RESERVED | REGION_SEL2 | MCONNID1 | RESERVED | REGION_SEL1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | MCONNID2 | MConnID for EMIF_PERFORMANCE_COUNTER_2 register. | RW | 0x00 |
23:18 | RESERVED | Reserved | R | 0x00 |
17:16 | REGION_SEL2 | MAddrSpace for EMIF_PERFORMANCE_COUNTER_2 register. | RW | 0x0 |
15:8 | MCONNID1 | MConnID for EMIF_PERFORMANCE_COUNTER_1 register. | RW | 0x00 |
7:2 | RESERVED | Reserved | R | 0x00 |
1:0 | REGION_SEL1 | MAddrSpace for EMIF_PERFORMANCE_COUNTER_1 register. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4C00 0090 0x4D00 0090 | Instance | EMIF1 EMIF2 |
Description | Performance Counter Time Register. This is a free running counter. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOTAL_TIME |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TOTAL_TIME | 32-bit counter that continuously counts number for EMIF_FICLK clock cycles elapsed after EMIF is brought out of reset. | R | 0x0000 0000 |
EMIF Controller |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4C00 0094 0x4D00 0094 | Instance | EMIF1 EMIF2 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DLL_CALIB_OS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | Reserved | R | 0x0 |
0 | DLL_CALIB_OS | Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse. Bit is self cleared when pll_calib gets generated and ack_wait has been satisfied. Software can poll to confirm completion. Uses the EMIF_DLL_CALIB_CTRL[19:16] ACK_WAIT bit field for time to wait after firing off the phy_dll_calib. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4C00 0098 0x4D00 0098 | Instance | EMIF1 EMIF2 |
Description | Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps. NOTE: Should always be loaded via the shadow register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACK_WAIT | RESERVED | DLL_CALIB_INTERVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x000 | |
19:16 | ACK_WAIT | The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent. Value program is in terms of EMIF_FICLK cycle count. CAUTION: 5 must be the minimum value ever programmed. | RW | 0x9 |
15:9 | RESERVED | R | 0x00 | |
8:0 | DLL_CALIB_INTERVAL | This field determines the interval between phy_dll_calib generation. This value is multiplied by a precounter of 16 EMIF_FICLK cycles. Program this field one less the value you are targeting; program 1 to achieve interval of 2 (minimum interval supported). Programming zero turns off function. Note the final intervals between dll_calib generation is also a function of ACK_WAIT. Final periodic interval is calculated by: ((DLL_CALIB_INTERVAL + 1) × 16) + ACK_WAIT | RW | 0x000 |
EMIF Controller |
Address Offset | 0x0000 009C | ||
Physical Address | 0x4C00 009C 0x4D00 009C | Instance | EMIF1 EMIF2 |
Description | Read Idle Control Shadow Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACK_WAIT_SHDW | RESERVED | DLL_CALIB_INTERVAL_SHDW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x000 | |
19:16 | ACK_WAIT_SHDW | Shadow field for ACK_WAIT. This field is loaded into ACK_WAIT field in EMIF_DLL_CALIB_CTRL register when SIdleAck is asserted | RW | 0x9 |
15:9 | RESERVED | R | 0x00 | |
8:0 | DLL_CALIB_INTERVAL_SHDW | Shadow field for DLL_CALIB_INTERVAL. This field is loaded into DLL_CALIB_INTERVAL field in the EMIF_DLL_CALIB_CTRL register when SIdleAck is asserted | RW | 0x000 |
EMIF Controller |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4C00 00A0 0x4D00 00A0 | Instance | EMIF1 EMIF2 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0 | |
0 | EOI | Software End Of Interrupt (EOI) control. Write 0x0 for system OCP interrupt. This field always reads 0 (no EOI memory). | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x4C00 00A4 0x4D00 00A4 | Instance | EMIF1 EMIF2 |
Description | System OCP Interrupt Raw Status Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ONEBIT_ECC_ERR_SYS | TWOBIT_ECC_ERR_SYS | WR_ECC_ERR_SYS | RESERVED | ERR_SYS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x000 0000 | |
5 | ONEBIT_ECC_ERR_SYS | Raw status of system ECC one bit error correction interrupt. | RW | 0x0 |
4 | TWOBIT_ECC_ERR_SYS | Raw status of system ECC two bit error detection interrupt. | RW | 0x0 |
3 | WR_ECC_ERR_SYS | Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled. | RW | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | ERR_SYS | Raw status of system OCP interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect. | RW | 0 |
EMIF Controller |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4C00 00AC 0x4D00 00AC | Instance | EMIF1 EMIF2 |
Description | System OCP Interrupt Status Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ONEBIT_ECC_ERR_SYS | TWOBIT_ECC_ERR_SYS | WR_ECC_ERR_SYS | RESERVED | ERR_SYS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x000 0000 | |
5 | ONEBIT_ECC_ERR_SYS | Enabled status of system ECC one bit error correction interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect | RW | 0x0 |
4 | TWOBIT_ECC_ERR_SYS | Enabled status of system ECC two bit error detection interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect. | RW | 0x0 |
3 | WR_ECC_ERR_SYS | Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect. | RW | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | ERR_SYS | Enabled status of system OCP interrupt interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has no effect. | RW | 0 |
EMIF Controller |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x4C00 00B4 0x4D00 00B4 | Instance | EMIF1 EMIF2 |
Description | System OCP Interrupt Enable Set Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ONEBIT_ECC_ERR_SYS | TWOBIT_ECC_ERR_SYS | WR_ECC_ERR_SYS | RESERVED | EN_ERR_SYS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x000 0000 | |
5 | ONEBIT_ECC_ERR_SYS | Enabled status of sysem ECC one bit error correction interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect. | RW W1toSet | 0x0 |
4 | TWOBIT_ECC_ERR_SYS | Enabled status of system ECC two bit error detection interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect. | RW W1toSet | 0x0 |
3 | WR_ECC_ERR_SYS | Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect. | RW W1toSet | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | EN_ERR_SYS | Enable set for system OCP interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect. | RW W1toSet | 0 |
EMIF Controller |
Address Offset | 0x0000 00BC | ||
Physical Address | 0x4C00 00BC 0x4D00 00BC | Instance | EMIF1 EMIF2 |
Description | System OCP Interrupt Enable Clear Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ONEBIT_ECC_ERR_SYS | TWOBIT_ECC_ERR_SYS | WR_ECC_ERR_SYS | RESERVED | EN_ERR_SYS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x000 0000 | |
5 | ONEBIT_ECC_ERR_SYS | Enabled status of system ECC one bit error correction interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect. | RW W1toClr | 0x0 |
4 | TWOBIT_ECC_ERR_SYS | Enabled status of system ECC two bit error detection interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect. | RW W1toClr | 0x0 |
3 | WR_ECC_ERR_SYS | Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect. | RW W1toClr | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | EN_ERR_SYS | Enable clear for system OCP interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect. | RW W1toClr | 0 |
EMIF Controller |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x4C00 00C8 0x4D00 00C8 | Instance | EMIF1 EMIF2 |
Description | SDRAM Output Impedance Calibration Config Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ZQ_CS0EN | RESERVED | ZQ_SFEXITEN | RESERVED | ZQ_ZQINIT_MULT | ZQ_ZQCL_MULT | ZQ_REFINTERVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | R | 0x0 | |
30 | ZQ_CS0EN | Writing a 1 enables ZQ calibration for CS0. | RW | 0x0 |
29 | RESERVED | R | 0x0 | |
28 | ZQ_SFEXITEN | Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit. | RW | 0x0 |
27:20 | RESERVED | R | 0x00 | |
19:18 | ZQ_ZQINIT_MULT | Indicates the number of ZQCL durations that make up a ZQINIT duration, minus one. | RW | 0x0 |
17:16 | ZQ_ZQCL_MULT | Indicates the number of ZQCS intervals that make up a ZQCL duration, minus one. ZQCS interval is defined by ZQ_ZQCS in EMIF_SDRAM_TIMING_3. | RW | 0x0 |
15:0 | ZQ_REFINTERVAL | Number of refresh periods between ZQCS commands. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. | RW | 0x0000 |
EMIF Controller |
Address Offset | 0x0000 00CC | ||
Physical Address | 0x4C00 00CC 0x4D00 00CC | Instance | EMIF1 EMIF2 |
Description | Temperature Alert Configuration Register. NOTE: This register is only applicable to LPDDR2 memories and cannot be used in this device. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TA_CS1EN | TA_CS0EN | RESERVED | TA_SFEXITEN | TA_DEVWDT | TA_DEVCNT | RESERVED | TA_REFINTERVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | TA_CS1EN | Writing 1 enables temperature alert polling for CS1. | RW | 0x0 |
30 | TA_CS0EN | Writing 1 enables temperature alert polling for CS0. | RW | 0x0 |
29 | RESERVED | Reserved | R | 0x0 |
28 | TA_SFEXITEN | Temperature Alert Poll on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing 1 enables the issuing of a temperature alert poll on Self-Refresh exit. | RW | 0x0 |
27:26 | TA_DEVWDT | This field indicates how wide a physical device is. It is used in conjunction with the TA_DEVCNT field to determine which byte lanes contain the temperature alert info. A value of 0: 8-bit wide, 1: 16-bit wide, 2: 32-bit wide. All others are reserved. If this field is set to 1 and the TA_DEVCNT field is set to 1 the byte mask for checking is 4'b0101. | RW | 0x0 |
25:24 | TA_DEVCNT | This field indicates which external byte lanes contain a device for temperature monitoring. A value of 0: one device, 1: two devices, 2: four devices. All other reserved. | RW | 0x0 |
23:22 | RESERVED | Reserved | R | 0x0 |
21:0 | TA_REFINTERVAL | Number of refresh periods between temperature alert polls. This field supports between one refresh period to 10 seconds between temperature alert polls. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 00D0 | ||
Physical Address | 0x4C00 00D0 0x4D00 00D0 | Instance | EMIF1 EMIF2 |
Description | OCP Error Log Register. This register is overwritten by any first error transaction once after the interrupt is serviced and cleared by writing 0x1 to the EMIF_SYSTEM_OCP_INTERRUPT_STATUS[0] ERR_SYS bit or EMIF_SYSTEM_OCP_INTERRUPT_STATUS[3] WR_ECC_ERR_SYS bit. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MADDRSPACE | MBURSTSEQ | MCMD | MCONNID |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | Reserved for future use. | R | 0x0000 |
15:14 | MADDRSPACE | Address space of the first errored transaction. 0x0: SDRAM 0x1: reserved 0x2: reserved 0x3: internal registers | R | 0x0 |
13:11 | MBURSTSEQ | Addressing mode of the first errored transaction. (see Section 16.2.1, L3_MAIN Interconnect for more information) | R | 0x0 |
10:8 | MCMD | Command type of the first errored transaction. (see Section 16.2.1, L3_MAIN Interconnect for more information) | R | 0x0 |
7:0 | MCONNID | Connection ID of the first errored transaction. | R | 0x00 |
EMIF Controller |
Address Offset | 0x0000 00D4 | ||
Physical Address | 0x4C00 00D4 0x4D00 00D4 | Instance | EMIF1 EMIF2 |
Description | Read/write leveling ramp window register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDWRLVLINC_RMP_WIN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:13 | RESERVED | R | 0x0 0000 | |
12:0 | RDWRLVLINC_RMP_WIN | Incremental leveling ramp window in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device. | RW | 0x0000 |
EMIF Controller |
Address Offset | 0x0000 00D8 | ||
Physical Address | 0x4C00 00D8 0x4D00 00D8 | Instance | EMIF1 EMIF2 |
Description | Read/write leveling ramp control register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDWRLVL_EN | RDWRLVLINC_RMP_PRE | RDLVLINC_RMP_INT | RDLVLGATEINC_RMP_INT | WRLVLINC_RMP_INT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RDWRLVL_EN | Read-Write Leveling enable. Set 1 to enable leveling. Set 0 to disable leveling. | RW | 0 |
30:24 | RDWRLVLINC_RMP_PRE | Incremental leveling pre-scalar in number of refresh periods during ramp window. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
23:16 | RDLVLINC_RMP_INT | Incremental read data eye training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read data eye training during ramp window. A value of 0 will disable incremental read data eye training.NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
15:8 | RDLVLGATEINC_RMP_INT | Incremental read DQS gate training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read DQS gate training during ramp window. A value of 0 will disable incremental read DQS gate training.NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
7:0 | WRLVLINC_RMP_INT | Incremental write leveling interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental write leveling during ramp window. A value of 0 will disable incremental write leveling.NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
EMIF Controller |
Address Offset | 0x0000 00DC | ||
Physical Address | 0x4C00 00DC 0x4D00 00DC | Instance | EMIF1 EMIF2 |
Description | Read/write leveling control register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDWRLVLFULL_START | RDWRLVLINC_PRE | RDLVLINC_INT | RDLVLGATEINC_INT | WRLVLINC_INT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RDWRLVLFULL_START | Full leveling trigger. Writing a 1 to this field triggers full read and write leveling. This bit will self clear to 0. | RW | 0 |
30:24 | RDWRLVLINC_PRE | Incremental leveling pre-scalar in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
23:16 | RDLVLINC_INT | Incremental read data eye training interval. Number of RDWRLVLINC_PRE intervals between incremental read data eye training. A value of 0 will disable incremental read data eye training. NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
15:8 | RDLVLGATEINC_INT | Incremental read DQS gate training interval. Number of RDWRLVLINC_PRE intervals between incremental read DQS gate training. A value of 0 will disable incremental read DQS gate training. NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
7:0 | WRLVLINC_INT | Incremental write leveling interval. Number of RDWRLVLINC_PRE intervals between incremental write leveling. A value of 0 will disable incremental write leveling. NOTE: Incremental leveling is not supported on this device. | RW | 0x00 |
EMIF Controller |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x4C00 00E0 | Instance | EMIF1 |
Description | [New DRA7xxP feature versus DRA75x/DRA74x] OCP Error Address Log Register. This register is overwritten by any successive first error transaction once the interrupt is serviced and cleared by writing 0x1 to the EMIF_SYSTEM_OCP_INTERRUPT_STATUS[0] ERR_SYS bit or EMIF_SYSTEM_OCP_INTERRUPT_STATUS[3] WR_ECC_ERR_SYS bit. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_OCP_ERR_ADDR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REG_OCP_ERR_ADDR | OCP error address. Most significant bits of the start address of the first SDRAM burst having OCP error. This register also logs most significant bits of the start address of the first SDRAM burst for a sub-quanta or quanta-misaligned write to the ECC enabled region with RMW disabled. | RW | 0x0 |
EMIF Controller |
Address Offset | 0x0000 00E4 | ||
Physical Address | 0x4C00 00E4 0x4D00 00E4 | Instance | EMIF1 EMIF2 |
Description | PHY control register 1 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDLVL_MASK | RDLVLGATE_MASK | WRLVL_MASK | RESERVED | PHY_HALF_DELAYS | PHY_CLK_STALL_LEVEL | PHY_DIS_CALIB_RST | PHY_INVERT_CLKOUT | PHY_DLL_LOCK_DIFF | PHY_FAST_DLL_LOCK | RESERVED | READ_LATENCY |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | Reserved | RW | 0x0 |
27 | RDLVL_MASK | Writing a 1 to this field will mask read data eye training during full leveling command, plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values. | RW | 0 |
26 | RDLVLGATE_MASK | Writing a 1 to this field will mask dqs gate training during full leveling command, plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values. | RW | 0 |
25 | WRLVL_MASK | Writing a 1 to this field will mask write leveling training during full leveling command, plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values. | RW | 0 |
24:22 | RESERVED | Reserved | RW | 0x0 |
21 | PHY_HALF_DELAYS | Adjust slave delay line delays to support 2× mode 1: 2× mode (MDLL clock is half the rate of PHY) 0: 1× mode (MDLL clock rate is same as PHY) | RW | 0 |
20 | PHY_CLK_STALL_LEVEL | Enable variable idle value for delay lines. Enable during normal operations to avoid differential aging in the delay lines. | RW | 0 |
19 | PHY_DIS_CALIB_RST | Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs. Debug only. Note: dll_calib is generated by 1. EMIF_MISC_REG[0] DLL_CALIB_OS set to 1,or 2. by the PHY when it detects that the clock frequency variation has exceeded the bounds set by PHY_DLL_LOCK_DIFF or 3. periodically throughout the leveling process. | RW | 0 |
18 | PHY_INVERT_CLKOUT | Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM | RW | 0 |
17:10 | PHY_DLL_LOCK_DIFF | The maximum number of delay line taps variation while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by this field, the lock signal is de-asserted and a dll_calib signal is generated. To prevent the dll_calib signal from being asserted in the middle of traffic when the clock jitter exceeds the variation, this register needs to be set to a value which will ensure that the lock will not be lost. Recommended value is 16. | RW | 0x02 |
9 | PHY_FAST_DLL_LOCK | Controls master DLL to lock fast or average logic must be part of locking process. Set to 1 before OPP transition commences, and set back to 0 after OPP transition completes. 1: MDLL lock is asserted based on single sample 0: MDLL lock is asserted based on average of 16 samples. | RW | 0 |
8:5 | RESERVED | Reserved | RW | 0x00 |
4:0 | READ_LATENCY | This field defines the read latency for the read data from SDRAM in number of DDR clock cycles. This field is used by the EMIF as well as the PHY. READ_LATENCY = RL + reg_phy_rdc_we_to_re -1. EMIF uses above equation to calculate reg_phy_rdc_we_to_re and forward it to the PHY. For DDR3, the true RL is used, not the decoded value. See JEDEC spec. | RW | 0x01E |
EMIF Controller |
Address Offset | 0x0000 00E8 | ||
Physical Address | 0x4C00 00E8 0x4D00 00E8 | Instance | EMIF1 EMIF2 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDLVL_MASK_SHDW | RDLVLGATE_MASK_SHDW | WRLVL_MASK_SHDW | RESERVED | PHY_HALF_DELAYS_SHDW | PHY_CLK_STALL_LEVEL_SHDW | PHY_DIS_CALIB_RST_SHDW | PHY_INVERT_CLKOUT_SHDW | PHY_DLL_LOCK_DIFF_SHDW | PHY_FAST_DLL_SHDW | RESERVED | READ_LATENCY_SHDW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | Reserved | RW | 0x0 |
27 | RDLVL_MASK_SHDW | Shadow field for RDLVL_MASK | RW | 0 |
26 | RDLVLGATE_MASK_SHDW | Shadow field for RDLVLGATE_MASK | RW | 0 |
25 | WRLVL_MASK_SHDW | Shadow field for WRLVL_MASK | RW | 0 |
24:22 | RESERVED | Reserved | RW | 0x0 |
21 | PHY_HALF_DELAYS_SHDW | Shadow field for PHY_HALF_DELAYS | RW | 0 |
20 | PHY_CLK_STALL_LEVEL_SHDW | Shadow field for PHY_CLK_STALL_LEVEL | RW | 0 |
19 | PHY_DIS_CALIB_RST_SHDW | Shadow field for PHY_DIS_CALIB_RST | RW | 0 |
18 | PHY_INVERT_CLKOUT_SHDW | Shadow field for PHY_INVERT_CLKOUT | RW | 0 |
17:10 | PHY_DLL_LOCK_DIFF_SHDW | Shadow field for PHY_DLL_LOCK_DIFF | RW | 0x00 |
9 | PHY_FAST_DLL_SHDW | Shadow field for PHY_FAST_DLL | RW | 0 |
8:5 | RESERVED | Reserved | RW | 0x00 |
4:0 | READ_LATENCY_SHDW | Shadow field for READ_LATENCY | RW | 0x000 |
EMIF Controller |
Address Offset | 0x0000 00EC | ||
Physical Address | 0x4C00 00EC 0x4D00 00EC | Instance | EMIF1 EMIF2 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESERVED | Reserved | RW | 0x0 |
EMIF Controller |
Address offset | 0x0000 0100 | ||||
Physical Address | 0x4C00 0100 0x4D00 0100 | Instance | EMIF1 EMIF2 | ||
Description | |||||
Type | RW |
31 | 30 | var tiPageName = 'Literature reader-SPRUIE9D-en_US'; var tiDocType = 'Technical Reference'; var tiLibraryStore = new com.TI.tiLibrary.tiLibraryStore(); var tiLibraryViewerStore = tiLibraryStore.viewer_store; RiotControl.addStore(tiLibraryStore); var subRoutes = riot.route.create(); subRoutes("/document-viewer/*/datasheet/*\\?*#*", function(gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*#*", function(gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*", function(gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*\\?*#*", function(locale, gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*#*", function(locale, gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*", function(locale, gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet#*/*", function(gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet#*/*", function(locale, gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*", function(litnum) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*\\?*#*", function(litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*#*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*#*/*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*#*/*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*", function(litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*\\?*#*", function(locale, litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*#*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*", function(locale, litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); var compose_url = function(q) { //URL format: scheme:[//[user[:password]@]host[:port]][/path][?query][#fragment] var tempUrl = q.url.replace("//www.ti.com/", ""); var url = tempUrl.replace("//www.ti.com/", ""); if (q.search != null) { var params = ""; var hash = ""; var url_parts = url.split('#'); if (url_parts.length == 2) { url = url_parts[0]; hash = url_parts[1]; } var param_parts = url.split('?'); if (param_parts.length == 2) { url = param_parts[0]; var parsed_params = param_parts[1].split('&'); var keyword_param_found = false; for (var i = 0; i < parsed_params.length; i++) { if (parsed_params[i].indexOf('search=') == 0) { keyword_param_found = true; parsed_params[i] = 'search=' + q.search; } } if (!keyword_param_found) { parsed_params.push('search=' + q.search); } params = parsed_params.join('&'); } else { params = 'search=' + q.search; } if (params > "") { url = url + '?' + params; } if (hash > "") { url = url + '#' + hash; } } return url; }; tiLibraryViewerStore.compose_url_route = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.compute_content_href = function(href, url) { return url; }; tiLibraryViewerStore.compose_topic_url = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.important_notice_url = "//www.ti.com/document-viewer/lit/html/SPRUIE9D/important_notice#ImpNotice001"; var ods_reader = riot.mount('ti-library-viewer', { store: tiLibraryStore.list_store, viewerstore: tiLibraryViewerStore }); riot.route.base('/'); riot.route.start(true); compute_document_locale = function(docName) { var locale = 'en_US'; if (docName) { if (docName.toLowerCase().indexOf('z')===0) { locale = 'zh_CN'; } else if (docName.toLowerCase().indexOf('j') == 0) { locale = 'ja_JP'; } } return locale; } open_reader = function() { var path = window.location.pathname.split('/'); var path_minus_filename = ''; for (var i = 0; i < path.length - 1; i++) { if (i == 0 && path[i] == '') { console.log("double slashes found in beginning of document path; treating document path as local machine path"); continue; } path_minus_filename += "/" + path[i]; } RiotControl.trigger("ti_library_open_viewer", { documentLocale: compute_document_locale( "SPRUIE9D"), document: { href: path_minus_filename, lit_num: "SPRUIE9D", doc_type: "Technical Reference", show_toc: "true", translated_doc_type: "User guide", gpn: "", title: "DRA75xP, DRA74xP, DRA77xP, DRA76xP SoC for Automotive Infotainment Silicon Revision 1.0 Texas Instruments Jacinto 6 Plus Infotainment Family of Products", disclaimer: "", product: "//www.ti.com/product/", email: 'mailto:?subject=SPRUIE9D DRA75xP, DRA74xP, DRA77xP, DRA76xP SoC for Automotive Infotainment Silicon Revision 1.0 Texas Instruments Jacinto 6 Plus Infotainment Family of Products&body=http://www.ti.com/document-viewer/lit/html/SPRUIE9', download: '//www.ti.com/lit/pdf/SPRUIE9D', tistore: '//store.ti.com/Search.aspx?k=&pt=-1', productstatusdescription: '' }, url: "/document-viewer//datasheet/GUID-5DAFE748-E0C5-43DC-9CAB-A671F2CAD378.html", prepopulated: true, modalOptions: { dismissible: false } }); } open_reader(); |