SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4AE3 C000 0x4848 0000 | Instance | DCAN1 DCAN2 |
Description | DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit. If the module goes Bus-Off, it will automatically set the INIT bit and stop all bus activities. When the INIT bit is cleared by the application again, the module will then wait for 129 occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation. At the end of the bus-off recovery sequence, the error counters will be reset. After the INIT bit is reset, each time when a sequence of 11 recessive bits is monitored, a Bit0 error code is written to DCAN_ES, enabling the software to check whether the CAN bus is stuck at dominant or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WUBA | PDR | RESERVED | DE3 | DE2 | DE1 | IE1 | INITDBG | SWR | RESERVED | PMD | ABO | IDS | TEST | CCE | DAR | RESERVED | EIE | SIE | IE0 | INIT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:26 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 |
25 | WUBA | Automatic wake up on bus activity when in local power-down mode. Note: The CAN message, which initiates the bus activity, cannot be received. This means that the first message received in power down and automatic wake-up mode, will be lost. | RW | 0 |
0: No detection of a dominant CAN bus level while in local power-down mode. | ||||
1: Detection of a dominant CAN bus level while in local power-down mode is enabled. On occurrence of a dominant CAN bus level, the wake up sequence is started (Additional information can be found in Local Power-Down Mode). | ||||
24 | PDR | Request for local low power-down mode | RW | 0 |
0: No application request for local low power-down mode. If the application has cleared this bit while DCAN in local power-down mode, also the INIT bit has to be cleared. | ||||
1: Local power-down mode has been requested by application. The DCAN will acknowledge the local power-down mode by setting bit PDA in the DCAN_ES register. The local clocks will be turned off by DCAN internal logic (Additional information can be found in Local Power-Down Mode). | ||||
23:21 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
20 | DE3 | Enable DMA request line for IF3. Note: A pending DMA request for IF3 remains active until first access to one of the IF3 registers. | RW | 0 |
0: Disabled | ||||
1: Enabled | ||||
19 | DE2 | Enable DMA request line for IF2. Note: A pending DMA request for IF2 remains active until first access to one of the IF2 registers. | RW | 0 |
0: Disabled | ||||
1: Enabled | ||||
18 | DE1 | Enable DMA request line for IF1. Note: A pending DMA request for IF1 remains active until first access to one of the IF1 registers. | RW | 0 |
0: Disabled | ||||
1: Enabled | ||||
17 | IE1 | Interrupt line 1 enable | RW | 0 |
0: Disabled - Module interrupt INT1 is always low. | ||||
1: Enabled - interrupts will assert line INT1 to one; line remains active until pending interrupts are processed. | ||||
16 | INITDBG | Internal init state while debug access | RW | 0 |
0: Not in debug mode, or debug mode requested but not entered. | ||||
1: Debug mode requested and internally entered; the DCAN is ready for debug accesses. | ||||
15 | SWR | Software reset enable. Note: To execute software reset, the following procedure is necessary:
| RW | 0 |
0: Normal Operation | ||||
1: Module is forced to reset state. This bit will automatically get cleared after execution of software reset after one OCP clock cycle. | ||||
14 | RESERVED | This bit is always read as 0. Writes have no effect. | R | 0 |
13:10 | PMD | Parityon/off | RW | 0x5 |
0x5: function disabled | ||||
Others: function enabled | ||||
9 | ABO | Auto-Bus-On enable | RW | 0 |
0: The Auto-Bus-On feature is disabled | ||||
1: The Auto-Bus-On feature is enabled | ||||
8 | IDS | Interruption debug support enable | RW | 0 |
0: When Debug/Suspend mode is requested, DCAN will wait for a started transmission or reception to be completed before entering Debug/Suspend mode | ||||
1: When Debug/Suspend mode is requested, DCAN will interrupt any transmission or reception, and enter Debug/Suspend mode immediately. | ||||
7 | TEST | Test mode enable | RW | 0 |
0: Normal Operation | ||||
1: Test Mode | ||||
6 | CCE | Configuration change enable | RW | 0 |
0: The software has no write access to the configuration registers. | ||||
1: The software has write access to the configuration registers (when INIT bit is set). | ||||
5 | DAR | Disable automatic retransmission | RW | 0 |
0: Automatic retransmission of not successful messages enabled. | ||||
1: Automatic retransmission disabled. | ||||
4 | RESERVED | This bit is always read as 0. Writes have no effect. | R | 0 |
3 | EIE | Error interrupt enable | RW | 0 |
0: Disabled - PER, BOFF and EWARN bits can not generate an interrupt. | ||||
1: Enabled - PER, BOFF and EWARN bits can generate an interrupt at INT0 line and affect the interrupt register. | ||||
2 | SIE | Status change interrupt enable | RW | 0 |
0: Disabled - WAKEUPPND, RXOK, TXOK and LEC bits can not generate an interrupt. | ||||
1: Enabled - WAKEUPPND, RXOK, TXOK and LEC can generate an interrupt at INT0 line and affect the interrupt register. | ||||
1 | IE0 | Interrupt line 0 enable | RW | 0 |
0: Disabled - Module interrupt INT0 is always low. | ||||
1: Enabled - interrupts will assert line INT0 to one; line remains active until pending interrupts are processed. | ||||
0 | INIT | Initialization | RW | 1 |
0: Normal operation | ||||
1: Initialization mode is entered |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4AE3 C004 0x4848 0004 | Instance | DCAN1 DCAN2 |
Description | Error and Status Register Interrupts are generated by bits PER, BOFF and EWARN (if EIE bit in DCAN_CTL is 1) and by bits WAKEUPPND, RXOK, TXOK, and LEC (if SIE bit in DCAN_CTL is 1). A change of bit EPASS will not generate an interrupt. Reading the DCAN_ES clears the WAKEUPPND, PER, RXOK and TXOK bits and set the LEC to value '7.' Additionally, the status interrupt value (0x8000) in the DCAN_INT will be replaced by the next lower priority interrupt value. For debug support, the auto clear functionality of DCAN_ES (clear of status flags by read) is disabled when in debug/suspend mode. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PDA | WAKEUPPND | PER | BOFF | EWARN | EPASS | RXOK | TXOK | LEC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:11 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 0000 |
10 | PDA | Local power-down mode acknowledge | R | 0 |
0: DCAN is not in local power-down mode. | ||||
1: Application request for setting DCAN to local power-down mode was successful. DCAN is in local power-down mode. | ||||
9 | WAKEUPPND | Wake up pending. This bit can be used by the software to identify the DCAN as the source to wake up the system. This bit will be reset if DCAN_ES is read. | R | 0 |
0: No Wake Up is requested by DCAN. | ||||
1: DCAN has initiated a wake up of the system due to dominant CAN bus while module power down. | ||||
8 | PER | Parity error detected. This bit will be reset if DCAN_ES register is read. | RW | 0 |
Read 0: No parity error has been detected since last read access. | ||||
Read 1: The parity check mechanism has detected a parity error in the Message RAM. | ||||
Write 0: No effect | ||||
Write 1: End of interrupt (EOI) for parity error on DCAN_PARITY interrupt line | ||||
7 | BOFF | Bus-Off state | R | 0 |
0: The CAN module is not bus-off state. | ||||
1: The CAN module is in bus-off state. | ||||
6 | EWARN | Warning state | R | 0 |
0: Both error counters are below the error warning limit of 96. | ||||
1: At least one of the error counters has reached the error warning limit of 96. | ||||
5 | EPASS | Error passive state | R | 0 |
0: On CAN Bus error, the DCAN could send active error frames. | ||||
1: The CAN core is in the error passive state as defined in the CAN Specification. | ||||
4 | RXOK | Received a message successfully. This bit will be reset if DCAN_ES register is read. | R | 0 |
0: No message has been successfully received since the last time when this bit was read by the software. This bit is never reset by DCAN internal events. | ||||
1: A message has been successfully received since the last time when this bit was reset by a read access of the software (independent of the result of acceptance filtering). | ||||
3 | TXOK | Transmitted a message successfully. This bit will be reset if DCAN_ES register is read. | R | 0 |
0: No message has been successfully transmitted since the last time when this bit was read by the software. This bit is never reset by DCAN internal events. | ||||
1: A message has been successfully transmitted (error free and acknowledged by at least one other node) since the last time when this bit was reset by a read access of the software. | ||||
2:0 | LEC | Last error code. The LEC field indicates the type of the last error on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. | R | 0x7 |
0x0: No error | ||||
0x1: Stuff error: More than five equal bits in a row have been detected in a part of a received message where this is not allowed. | ||||
0x2: Form error: A fixed format part of a received frame has the wrong format. | ||||
0x3: Ack error: The message this CAN core transmitted was not acknowledged by another node. | ||||
0x4: Bit1 error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. | ||||
0x5: Bit0 error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (logical value '0'), but the monitored bus level was recessive. During Bus-Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the software to monitor the proceeding of the Bus-Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). | ||||
0x6: CRC error: In a received message, the CRC check sum was incorrect. (CRC received for an incoming message does not match the calculated CRC for the received data). | ||||
0x7: No CAN bus event was detected since the last time the software read DCAN_ES. Any read access to DCAN_ES re-initializes the LEC to value '7.' |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4AE3 C008 0x4848 0008 | Instance | DCAN1 DCAN2 |
Description | Error Counter Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RP | REC | TEC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
15 | RP | Receive error passive | R | 0 |
0: The receive error counter is below the error passive level. | ||||
1: The receive error counter has reached the error passive level as defined in the CAN specification. | ||||
14:8 | REC | Receive error counter. Actual state of the receive error counter | R | 0x00 |
7:0 | TEC | Transmit error counter. Actual state of the transmit error counter | R | 0x00 |
DCAN |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4AE3 C00C 0x4848 000C | Instance | DCAN1 DCAN2 |
Description | Bit timing register This register is only writable if CCE and INIT bits in the DCAN_CTL are set. The CAN bit time may be programmed in the range of 8 to 25 time quanta The CAN time quantum may be programmed in the range of 1 to 1024 CAN_CLK periods. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BRPE | RESERVED | TSEG2 | TSEG1 | SJW | BRP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x000 |
19:16 | BRPE | Baud rate prescaler extension. | RW | 0x0 |
Valid programmed values are 0 to 15. | ||||
By programming BRPE the baud rate prescaler can be extended to values up to 1024. | ||||
15 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0 |
14:12 | TSEG2 | Time segment after the sample point | RW | 0x2 |
Valid programmed values are 0 to 7. | ||||
The actual TSeg2 value which is interpreted for the bit timing will be the programmed TSeg2 value + 1. | ||||
11:8 | TSEG1 | Time segment before the sample point | RW | 0x3 |
Valid programmed values are 1 to15. | ||||
The actual TSeg1 value interpreted for the bit timing will be the programmed TSeg1 value + 1. | ||||
7:6 | SJW | Synchronization Jump Width | RW | 0x0 |
Valid programmed values are 0 to 3. | ||||
The actual SJW value interpreted for the synchronization will be the programmed SJW value + 1. | ||||
5:0 | BRP | Baud rate prescaler | RW | 0x1 |
Value by which the CAN_CLK frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. | ||||
Valid programmed values are 0 to 63. | ||||
The actual BRP value interpreted for the bit timing will be the programmed BRP value + 1. |
DCAN |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4AE3 C010 0x4848 0010 | Instance | DCAN1 DCAN2 |
Description | Interrupt register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT1ID | INT0ID |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 |
23:16 | INT1ID | Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) | R | 0x00 |
0x00: No interrupt is pending | ||||
0x01-0x80: Number of message object which caused the interrupt. | ||||
0x81-0xFF: Unused | ||||
If several interrupts are pending, DCAN_INT will point to the pending interrupt with the highest priority. The INT1 interrupt line remains active until INT1ID reaches value 0 (the cause of the interrupt is reset) or until IE1 is cleared. | ||||
A message interrupt is cleared by clearing the message object's IntPnd bit. | ||||
Among the message interrupts, the message object's interrupt priority decreases with increasing message number. | ||||
15:0 | INT0ID | Interrupt Identifier (the number here indicates the source of the interrupt) | R | 0x0000 |
0x0000: No interrupt is pending | ||||
0x0001-0x0080: Number of message object which caused the interrupt. | ||||
0x0081-0x7FFF: Unused | ||||
0x8000: DCAN_ES value is not 0x07. | ||||
0x8001-0xFFFF: Unused | ||||
If several interrupts are pending,DCAN_INTwill point to the pending interrupt with the highest priority. The INT0 interrupt line remains active until INT0ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. | ||||
The Status interrupt has the highest priority. Among the message interrupts, the message object's interrupt priority decreases with increasing message number. |
DCAN |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4AE3 C014 0x4848 0014 | Instance | DCAN1 DCAN2 |
Description | Test Register For all test modes, the TEST bit in DCAN_CTL control register needs to be set to 1. If TEST bit is set, the RDA, EXL, TX1, TX0, LBACK and SILENT bits are writable. Bit RX monitors the state of pin CAN_RX and therefore is only readable. All test register functions are disabled when TEST bit is cleared. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDA | EXL | RX | TX | LBACK | SILENT | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 0000 |
9 | RDA | RAM direct access enable | RW | 0 |
0: Normal operation | ||||
1: Direct access to the RAM is enabled while in test mode | ||||
8 | EXL | External loopback mode. When the internal loop-back mode is active (bit LBACK is set), bit EXL will be ignored. | RW | 0 |
0: Disabled | ||||
1: Enabled | ||||
7 | RX | Receive pin. Monitors the actual value of the CAN_RX pin | R | - |
0: The CAN bus is dominant | ||||
1: The CAN bus is recessive | ||||
6:5 | TX | Control of CAN_TX pin. Setting Tx[1:0] other than '00' will disturb message transfer. | RW | 0x0 |
0x0: Normal operation, CAN_TX is controlled by the CAN core. | ||||
0x1: Sample point can be monitored at CAN_TX pin. | ||||
0x2: CAN_TX pin drives a dominant value. | ||||
0x3: CAN_TX pin drives a recessive value. | ||||
4 | LBACK | Loopback mode. When the internal loop-back mode is active (bit LBACK is set), bit EXL will be ignored. | RW | 0 |
0: Disabled | ||||
1: Enabled | ||||
3 | SILENT | Silent mode | RW | 0 |
0: Disabled | ||||
1: Enabled | ||||
2:0 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
DCAN |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4AE3 C01C 0x4848 001C | Instance | DCAN1 DCAN2 |
Description | Parity Error Code Register If a parity error is detected, the PER flag will be set in the DCAN_ES. This bit is not reset by the parity check mechanism; it must be reset by reading DCAN_ES. In addition to the PER flag, the parity error code register will indicate the memory area where the parity error has been detected (message number and word number). If more than one word with a parity error was detected, the highest word number with a parity error will be displayed. After a parity error has been detected, the register will hold the last error code until power is removed. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WORD_NUMBER | MESSAGE_NUMBER |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:11 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 0000 |
10:8 | WORD_NUMBER | Word number where parity error has been detected | R | 0x- |
RDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode). | ||||
7:0 | MESSAGE_NUMBER | Message object number where parity error has been detected (0x01-0x80) | R | 0x- |
DCAN |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4AE3 C020 0x4848 0020 | Instance | DCAN1 DCAN2 |
Description | Core revision register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | DCAN core revision number | R | 0x- |
DCAN |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4AE3 C080 0x4848 0080 | Instance | DCAN1 DCAN2 |
Description | Auto-Bus-On Time Register On write access to the DCAN_CTL while Auto-Bus-On timer is running, the Auto-Bus-On procedure will be aborted. During Debug/Suspend mode, running Auto-Bus-On timer will be paused. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABO_TIME |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ABO_TIME | Number of OCP clock cycles before a Bus-Off recovery sequence is started by clearing the INIT bit. This function has to be enabled by setting bit ABO in DCAN_CTL. The Auto-Bus-On timer is realized by a 32-bit counter which starts to count down to zero when the module goes Bus-Off. The counter will be reloaded with the preload value of the DCAN_ABOTR after this phase. | RW | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4AE3 C084 0x4848 0084 | Instance | DCAN1 DCAN2 |
Description | Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set. Each register bit represents a group of eight message objects. If at least one of the TxRqst bits of these message objects are set, the corresponding bit in the transmission request X register will be set. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXRQSTREG8 | TXRQSTREG7 | TXRQSTREG6 | TXRQSTREG5 | TXRQSTREG4 | TXRQSTREG3 | TXRQSTREG2 | TXRQSTREG1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | RESERVED | R | 0x0000 |
15:14 | TXRQSTREG8 | Transmission request bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
13:12 | TXRQSTREG7 | Transmission request bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
11:10 | TXRQSTREG6 | Transmission request bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
9:8 | TXRQSTREG5 | Transmission request bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
7:6 | TXRQSTREG4 | Transmission request bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
5:4 | TXRQSTREG3 | Transmission request bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
3:2 | TXRQSTREG2 | Transmission request bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
1:0 | TXRQSTREG1 | Transmission request bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
DCAN |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4AE3 C088 0x4848 0088 | Instance | DCAN1 DCAN2 |
Description | Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXRQS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TXRQS | Transmission request bits (for 1-32 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4AE3 C08C 0x4848 008C | Instance | DCAN1 DCAN2 |
Description | Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXRQS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TXRQS | Transmission request bits (for 33-64 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4AE3 C090 0x4848 0090 | Instance | DCAN1 DCAN2 |
Description | Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXRQS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TXRQS | Transmission request bits (for 65-96 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4AE3 C094 0x4848 0094 | Instance | DCAN1 DCAN2 |
Description | Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXRQS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TXRQS | Transmission request bits (for 97-128 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4AE3 C098 0x4848 0098 | Instance | DCAN1 DCAN2 |
Description | New Data X Register With the new data X register, the software can detect if one or more bits in the different new data registers are set. Each register bit represents a group of eight message objects. If at least on of the NewDat bits of these message objects are set, the corresponding bit in the new data X register will be set | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NEWDATREG8 | NEWDATREG7 | NEWDATREG6 | NEWDATREG5 | NEWDATREG4 | NEWDATREG3 | NEWDATREG2 | NEWDATREG1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | Reserved | R | 0x0000 |
15:14 | NEWDATREG8 | New data bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
13:12 | NEWDATREG7 | New data bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
11:10 | NEWDATREG6 | New data bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
9:8 | NEWDATREG5 | New data bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
7:6 | NEWDATREG4 | New data bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
5:4 | NEWDATREG3 | New data bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
3:2 | NEWDATREG2 | New data bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
1:0 | NEWDATREG1 | New data bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
DCAN |
Address Offset | 0x0000 009C | ||
Physical Address | 0x4AE3 C09C 0x4848 009C | Instance | DCAN1 DCAN2 |
Description | New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NEWDAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | NEWDAT | New Data Bits (for 1-32 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4AE3 C0A0 0x4848 00A0 | Instance | DCAN1 DCAN2 |
Description | New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NEWDAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | NEWDAT | New Data Bits (for 33-64 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x4AE3 C0A4 0x4848 00A4 | Instance | DCAN1 DCAN2 |
Description | New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NEWDAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | NEWDAT | New Data Bits (for 65-96 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4AE3 C0A8 0x4848 00A8 | Instance | DCAN1 DCAN2 |
Description | New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NEWDAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | NEWDAT | New Data Bits (for 97-128 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object. | R | 0x0000 0000 |
DCAN |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4AE3 C0AC 0x4848 00AC | Instance | DCAN1 DCAN2 |
Description | Interrupt Pending X Register With the interrupt pending X register, the software can detect if one or more bits in the different interrupt pending registers are set. Each bit of this register represents a group of eight message objects. If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the interrupt pending X register will be set. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTPNDREG8 | INTPNDREG7 | INTPNDREG6 | INTPNDREG5 | INTPNDREG4 | INTPNDREG3 | INTPNDREG2 | INTPNDREG1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | Reserved | R | 0x0000 |
15:14 | INTPNDREG8 | Interrupt Pending bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
13:12 | INTPNDREG7 | Interrupt Pending bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
11:10 | INTPNDREG6 | Interrupt Pendingbits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
9:8 | INTPNDREG5 | Interrupt Pending bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
7:6 | INTPNDREG4 | Interrupt Pending bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
5:4 | INTPNDREG3 | Interrupt Pending bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
3:2 | INTPNDREG2 | Interrupt Pending bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
1:0 | INTPNDREG1 | Interrupt Pending bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
DCAN |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x4AE3 C0B0 0x4848 00B0 | Instance | DCAN1 DCAN2 |
Description | Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTPND | Interrupt Pending Bits (for 1-32 message objects) | R | 0x0000 0000 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. |
DCAN |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x4AE3 C0B4 0x4848 00B4 | Instance | DCAN1 DCAN2 |
Description | Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTPND | Interrupt Pending Bits (for 33-64 message objects) | R | 0x0000 0000 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. |
DCAN |
Address Offset | 0x0000 00B8 | ||
Physical Address | 0x4AE3 C0B8 0x4848 00B8 | Instance | DCAN1 DCAN2 |
Description | Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTPND | Interrupt Pending Bits (for 65-96 message objects) | R | 0x0000 0000 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. |
DCAN |
Address Offset | 0x0000 00BC | ||
Physical Address | 0x4AE3 C0BC 0x4848 00BC | Instance | DCAN1 DCAN2 |
Description | Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTPND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTPND | Interrupt Pending Bits (for 97-128 message objects) | R | 0x0000 0000 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. |
DCAN |
Address Offset | 0x0000 00C0 | ||
Physical Address | 0x4AE3 C0C0 0x4848 00C0 | Instance | DCAN1 DCAN2 |
Description | Message Valid X Register With the message valid X register, the software can detect if one or more bits in the different message valid registers are set. Each bit of this register represents a group of eight message objects. If at least one of the MsgVal bits of these message objects are set, the corresponding bit in the message valid X register will be set. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSGVALREG8 | MSGVALREG7 | MSGVALREG6 | MSGVALREG5 | MSGVALREG4 | MSGVALREG3 | MSGVALREG2 | MSGVALREG1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | Reserved | R | 0x0000 |
15:14 | MSGVALREG8 | Message valid bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
13:12 | MSGVALREG7 | Message valid bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
11:10 | MSGVALREG6 | Message valid bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
9:8 | MSGVALREG5 | Message valid bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
7:6 | MSGVALREG4 | Message valid bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
5:4 | MSGVALREG3 | Message valid bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
3:2 | MSGVALREG2 | Message valid bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
1:0 | MSGVALREG1 | Message valid bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects. | R | 0x0 |
DCAN |
Address Offset | 0x0000 00C4 | ||
Physical Address | 0x4AE3 C0C4 0x4848 00C4 | Instance | DCAN1 DCAN2 |
Description | Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | MSGVAL | Message valid Bits (for 1-32 message objects) | R | 0x0000 0000 |
0: This message object is ignored by the message handler. | ||||
1: This message object is configured and will be considered by the message handler. |
DCAN |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x4AE3 C0C8 0x4848 00C8 | Instance | DCAN1 DCAN2 |
Description | Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | MSGVAL | Message valid Bits (for 33-64 message objects) | R | 0x0000 0000 |
0: This message object is ignored by the message handler. | ||||
1: This message object is configured and will be considered by the message handler. |
DCAN |
Address Offset | 0x0000 00CC | ||
Physical Address | 0x4AE3 C0CC 0x4848 00CC | Instance | DCAN1 DCAN2 |
Description | Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | MSGVAL | Message valid Bits (for 65-96 message objects) | R | 0x0000 0000 |
0: This message object is ignored by the message handler. | ||||
1: This message object is configured and will be considered by the message handler. |
DCAN |
Address Offset | 0x0000 00D0 | ||
Physical Address | 0x4AE3 C0D0 0x4848 00D0 | Instance | DCAN1 DCAN2 |
Description | Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | MSGVAL | Message valid Bits (for 97-128 message objects) | R | 0x0000 0000 |
0: This message object is ignored by the message handler. | ||||
1: This message object is configured and will be considered by the message handler. |
DCAN |
Address Offset | 0x0000 00D8 | ||
Physical Address | 0x4AE3 C0D8 0x4848 00D8 | Instance | DCAN1 DCAN2 |
Description | Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in DCAN_CTL. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp. INT1ID flags in the DCAN_INT register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTMUX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTMUX | Multiplexes IntPnd value to either INT0 or INT1 interrupt lines (bit 0 -> last implemented message object) ( bits 1:31 -> 1-31 message objects) | RW | 0x0000 0000 |
0: INT0 line is active if corresponding IntPnd flag is one. | ||||
1: INT1 line is active if corresponding IntPnd flag is one. |
DCAN |
Address Offset | 0x0000 00DC | ||
Physical Address | 0x4AE3 C0DC 0x4848 00DC | Instance | DCAN1 DCAN2 |
Description | Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the DCAN_INT register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTMUX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTMUX | Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 32-63 message objects) | RW | 0x0000 0000 |
0: INT0 line is active if corresponding IntPnd flag is one. | ||||
1: INT1 line is active if corresponding IntPnd flag is one. |
DCAN |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x4AE3 C0E0 0x4848 00E0 | Instance | DCAN1 DCAN2 |
Description | Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the DCAN_INT register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTMUX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTMUX | Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 64-95 message objects) | RW | 0x0000 0000 |
0: INT0 line is active if corresponding IntPnd flag is one. | ||||
1: INT1 line is active if corresponding IntPnd flag is one. |
DCAN |
Address Offset | 0x0000 00E4 | ||
Physical Address | 0x4AE3 C0E4 0x4848 00E4 | Instance | DCAN1 DCAN2 |
Description | Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the DCAN_INT register. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTMUX |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | INTMUX | Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 96-127 message objects) | RW | 0x0000 0000 |
0: INT0 line is active if corresponding IntPnd flag is one. | ||||
1: INT1 line is active if corresponding IntPnd flag is one. |
DCAN |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4AE3 C100 0x4848 0100 | Instance | DCAN1 DCAN2 |
Description | IF1 Command Register The IF1 Command Register (DCAN_IF1CMD) configure and initiate the transfer between the IF1 register set and the message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the software writes the message number to bits [7:0] MESSAGE_NUMBER. With this write operation, the BUSY bit is automatically set to 1 to indicate that a transfer is in progress. After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be completed and the BUSY bit is cleared. The maximum number of cycles is needed when the message transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the software writes to both DCAN_IF1CMD/DCAN_IF2CMD consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. While BUSY bit is one, IF1/IF2 register sets are write protected. For debug support, the auto clear functionality of the IF1/IF2 command registers (clear of DMAACTIVE flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message Number is written to bits [7:0] MESSAGE_NUMBER, the message handler may access an implemented (valid) message object instead. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WR_RD | MASK | ARB | CONTROL | CLRINTPND | TXRQST_NEWDAT | DATA_A | DATA_B | BUSY | DMAACTIVE | RESERVED | MESSAGE_NUMBER |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 |
23 | WR_RD | Write/Read | RW | 0 |
0: Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF1 register set. | ||||
1: Direction = Write: Transfer direction is from the IF1 register set to the message object addressed by MESSAGE_NUMBER. | ||||
22 | MASK | Access mask bits | RW | 0 |
0: Mask bits will not be changed | ||||
1: Direction = Read: The mask bits (identifier mask + MDir + MXtd) will be transferred from the message object addressed by MESSAGE_NUMBER to the IF1 register set. | ||||
1: Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF1 register set to the message object addressed by MESSAGE_NUMBER. | ||||
21 | ARB | Access arbitration bits | RW | 0 |
0: Arbitration bits will not be changed | ||||
1: Direction = Read: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the message object addressed by MESSAGE_NUMBER to the corresponding IF1 register set. | ||||
1: Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1 register set to the message object addressed by MESSAGE_NUMBER. | ||||
20 | CONTROL | Access control bits | RW | 0 |
0: Control bits will not be changed | ||||
1: Direction = Read: The message control bits will be transferred from the message object addressed by MESSAGE_NUMBER to the IF1 register set. | ||||
1: Direction = Write: The message control bits will be transferred from the IF1 registerset to the message object addressed by MESSAGE_NUMBER. | ||||
If the TXRQST_NEWDAT bit in this register(Bit [18]) is set, the TXRQST/ NEWDAT bits in the DCAN_IF1MCTL will be ignored. | ||||
19 | CLRINTPND | Clear interrupt pending bit | RW | 0 |
0: IntPnd bit will not be changed | ||||
1: Direction = Read: Clears IntPnd bit in the message object. | ||||
1: Direction = Write: This bit is ignored. Copying of IntPnd flag from IF1 Registers to message RAM can only be controlled by the CONTROL flag (Bit [20]). | ||||
18 | TXRQST_NEWDAT | Access transmission request bit | RW | 0 |
0: Direction = Read: NewDat bit will not be changed. Direction = Write: TxRqst/NewDat bit will be handled according to the CONTROL bit. | ||||
1: Direction = Read: Clears NewDat bit in the message object. 1: Direction = Write: Sets TxRqst/NewDat in message object. | ||||
Note: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in DCAN_IF1MCTL. | ||||
Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the DCAN_IF1MCTL always reflect the status before resetting them. | ||||
17 | DATA_A | Access Data Bytes 0-3 | RW | 0 |
0: Data Bytes 0-3 will not be changed. | ||||
1: Direction = Read: The data bytes 0-3 will be transferred from the message object addressed by the MESSAGE_NUMBER to the corresponding IF1 registerset. | ||||
1: Direction = Write: The data bytes 0-3 will be transferred from the IF1 registerset to the message object addressed by the MESSAGE_NUMBER. | ||||
Note: The duration of the message transfer is independent of the number of bytes to be transferred. | ||||
16 | DATA_B | Access Data Bytes 4-7 | RW | 0 |
0: Data Bytes 4-7 will not be changed. | ||||
1: Direction = Read: The data bytes 4-7 will be transferred from the message object addressed by MESSAGE_NUMBER to the corresponding IF1 registerset. | ||||
1: Direction = Write: The data bytes 4-7 will be transferred from the IF1 registerset to the message object addressed by MESSAGE_NUMBER. | ||||
Note: The duration of the message transfer is independent of the number of bytes to be transferred. | ||||
15 | BUSY | Busy flag | RW | 0 |
0: No transfer between IF1 register set and message RAM is in progress. | ||||
1: Transfer between IF1 register set and message RAM is in progress. | ||||
This bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER. IF1 register set will be write protected. The bit is cleared after read/write action has been finished. | ||||
14 | DMAACTIVE | Activation of DMA feature for subsequent internal IF1 update | RW | 0 |
0: DMA request line is independent of IF1 activities. | ||||
1: DMA is requested after completed transfer between IF1 register set and message RAM. | ||||
The DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one. | ||||
Note: Due to the auto reset feature of the DMAACTIVE bit, this bit has to be set for each subsequent DMA cycle separately. | ||||
13:8 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 |
7:0 | MESSAGE_NUMBER | Number of message object in message RAM which is used for data transfer | RW | 0x1 |
0x00: Invalid message number | ||||
0x01-0x80: Valid message numbers | ||||
0x81-0xFF: Invalid message numbers |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4AE3 C104 0x4848 0104 | Instance | DCAN1 DCAN2 |
Description | IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Section 26.10.4.11.1 Structure of Message Objects. While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MXTD | MDIR | RESERVED | MSK |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MXTD | Mask Extended Identifier | RW | 1 |
0: The extended identifier bit (IDE) has no effect on the acceptance filtering. | ||||
1: The extended identifier bit (IDE) is used for acceptance filtering. | ||||
When 11-bit (“standard”) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. | ||||
30 | MDIR | Mask Message Direction | RW | 1 |
0: The message direction bit (Dir) has no effect on the acceptance filtering. | ||||
1: The message direction bit (Dir) is used for acceptance filtering. | ||||
29 | RESERVED | This bit is always read as 1. Writes have no effect. | R | 1 |
28:0 | MSK | Identifier Mask | RW | 0x1FFF FFFF |
0: The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care). | ||||
1: The corresponding bit in the identifier of the message object is used for acceptance filtering. |
DCAN |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4AE3 C108 0x4848 0108 | Instance | DCAN1 DCAN2 |
Description | IF1 arbitration register The Arbitration bits ID[28:0], XTD, and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0], MXTD, and MDIR) for acceptance filtering of incoming messages. A received message is stored into the valid message object with matching identifier and Direction = receive (data frame) or Direction = transmit (remote frame). Extended frames can be stored only in message objects with XTD = 1, standard frames in message objects with XTD = 0. If a received message (data frame or remote frame) matches more than one valid message objects, it is stored into the one with the lowest message number. The bits of the IF1/IF2 arbitration registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Section 26.10.4.11.1 Structure of Message Objects While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL | XTD | DIR | ID |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MSGVAL | Message valid | RW | 0 |
0: The message object is ignored by the message handler. | ||||
1: The message object is to be used by the message handler. | ||||
The software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the DCAN_CTL. This bit must also be reset if the messages object is no longer required. | ||||
30 | XTD | Extended identifier | RW | 0 |
0: The 11-bit (“standard”) Identifier is used for this message object. | ||||
1: The 29-bit (“extended”) Identifier is used for this message object. | ||||
29 | DIR | Message direction | RW | 0 |
0: Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, this message is stored in this message object. | ||||
1: Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = 1). | ||||
28:0 | ID | Message identifier | RW | 0x0000 0000 |
ID[28:0]: 29-bit identifier (extended frame) | ||||
ID[28:18]: 11-bit identifier (standard frame) |
DCAN |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4AE3 C10C 0x4848 010C | Instance | DCAN1 DCAN2 |
Description | IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Section 26.10.4.11.1 Structure of Message Objects While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NEWDAT | MSGLST | INTPND | UMASK | TXIE | RXIE | RMTEN | TXRQST | EOB | RESERVED | DLC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
15 | NEWDAT | New data | RW | 0 |
0: No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software. | ||||
1: The message handler or the software has written new data into the data portion of this message object. | ||||
14 | MSGLST | Message lost (only valid for message objects with direction = receive) | RW | 0 |
0: No message lost since the last time when this bit was reset by the software. | ||||
1: The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten. | ||||
13 | INTPND | Interrupt pending | RW | 0 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. The Interrupt Identifier in DCAN_INT will point to this message object if there is no other interrupt source with higher priority. | ||||
12 | UMASK | Use acceptance mask | RW | 0 |
0: Mask ignored | ||||
1: Use mask (Msk[28:0], MXtd, and MDir) for acceptance filtering | ||||
If the UMASK bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. | ||||
11 | TXIE | Transmit interrupt enable | RW | 0 |
0: IntPnd will not be triggered after the successful transmission of a frame. | ||||
1: IntPnd will be triggered after the successful transmission of a frame. | ||||
10 | RXIE | Receive interrupt enable | RW | 0 |
0: IntPnd will not be triggered after the successful reception of a frame. | ||||
1: IntPnd will be triggered after the successful reception of a frame. | ||||
9 | RMTEN | Remote enable | RW | 0 |
0: At the reception of a remote frame, TxRqst is not changed. | ||||
1: At the reception of a remote frame, TxRqst is set. | ||||
8 | TXRQST | Transmit request | RW | 0 |
0: This message object is not waiting for a transmission. | ||||
1: The transmission of this message object is requested and is not yet done. | ||||
7 | EOB | End of Block | RW | 0 |
0: The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block. | ||||
1: The message object is a single message object or the last message object in a FIFO Buffer Block. | ||||
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to 1. | ||||
6:4 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
3:0 | DLC | Data length code | RW | 0x0 |
0-8: Data frame has 0-8 data bytes. | ||||
9-15 Data frame has 8 data bytes. | ||||
Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. |
DCAN |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4AE3 C110 0x4848 0110 | Instance | DCAN1 DCAN2 |
Description | IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_3 | DATA_2 | DATA_1 | DATA_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | DATA_3 | Data byte 3 | RW | 0x0 |
23:16 | DATA_2 | Data byte 2 | RW | 0x0 |
15:8 | DATA_1 | Data byte 1 | RW | 0x0 |
7:0 | DATA_0 | Data byte 0 | RW | 0x0 |
DCAN |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4AE3 C114 0x4848 0114 | Instance | DCAN1 DCAN2 |
Description | IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_7 | DATA_6 | DATA_5 | DATA_4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | DATA_7 | Data byte 7 | RW | 0x0 |
23:16 | DATA_6 | Data byte 6 | RW | 0x0 |
15:8 | DATA_5 | Data byte 5 | RW | 0x0 |
7:0 | DATA_4 | Data byte 4 | RW | 0x0 |
DCAN |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4AE3 C120 0x4848 0120 | Instance | DCAN1 DCAN2 |
Description | IF2 Command Register The IF2 Command Register (DCAN_IF2CMD) configure and initiate the transfer between the IF2 register set and the message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the software writes the message number to bits [7:0] MESSAGE_NUMBER. With this write operation, the BUSY bit is automatically set to 1 to indicate that a transfer is in progress. After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be completed and the BUSY bit is cleared. The maximum number of cycles is needed when the message transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the software writes to both DCAN_IF1CMD/DCAN_IF2CMD consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. While BUSY bit is one, IF1/IF2 register sets are write protected. For debug support, the auto clear functionality of the IF1/IF2 command registers (clear of DMAACTIVE flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message Number is written to bits [7:0] MESSAGE_NUMBER, the message handler may access an implemented (valid) message object instead. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WR_RD | MASK | ARB | CONTROL | CLRINTPND | TXRQST_NEWDAT | DATA_A | DATA_B | BUSY | DMAACTIVE | RESERVED | MESSAGE_NUMBER |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 |
23 | WR_RD | Write/Read | RW | 0 |
0: Direction = Read: Transfer direction is from the message object addressed by MESSAGE_NUMBER to the IF2 register set. | ||||
1: Direction = Write: Transfer direction is from the IF2 register set to the message object addressed by MESSAGE_NUMBER. | ||||
22 | MASK | Access mask bits | RW | 0 |
0: Mask bits will not be changed | ||||
1: Direction = Read: The mask bits (identifier mask + MDir + MXtd) will be transferred from the message object addressed by MESSAGE_NUMBER to the IF2 register set. | ||||
1: Direction = Write: The mask bits (identifier mask + MDir + MXtd) will be transferred from the IF2 register set to the message object addressed by MESSAGE_NUMBER. | ||||
21 | ARB | Access arbitration bits | RW | 0 |
0: Arbitration bits will not be changed | ||||
1: Direction = Read: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the message object addressed by MESSAGE_NUMBER to the corresponding IF2 register set. | ||||
1: Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF2 register set to the message object addressed by MESSAGE_NUMBER. | ||||
20 | CONTROL | Access control bits | RW | 0 |
0: Control bits will not be changed | ||||
1: Direction = Read: The message control bits will be transferred from the message object addressed by MESSAGE_NUMBER to the IF2 register set. | ||||
1: Direction = Write: The message control bits will be transferred from the IF2 registerset to the message object addressed by MESSAGE_NUMBER. | ||||
If the TXRQST_NEWDAT bit in this register(Bit [18]) is set, the TXRQST/ NEWDAT bits in the DCAN_IF1MCTL/DCAN_IF2MCTL will be ignored. | ||||
19 | CLRINTPND | Clear interrupt pending bit | RW | 0 |
0: IntPnd bit will not be changed | ||||
1: Direction = Read: Clears IntPnd bit in the message object. | ||||
1: Direction = Write: This bit is ignored. Copying of IntPnd flag from IF2 Registers to message RAM can only be controlled by the CONTROL flag (Bit [20]). | ||||
18 | TXRQST_NEWDAT | Access transmission request bit | RW | 0 |
0: Direction = Read: NewDat bit will not be changed. Direction = Write: TxRqst/NewDat bit will be handled according to the CONTROL bit. | ||||
1: Direction = Read: Clears NewDat bit in the message object. 1: Direction = Write: Sets TxRqst/NewDat in message object. | ||||
Note: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in DCAN_IF1MCTL/DCAN_IF2MCTL. | ||||
Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the DCAN_IF1MCTL/DCAN_IF2MCTL always reflect the status before resetting them. | ||||
17 | DATA_A | Access Data Bytes 0-3 | RW | 0 |
0: Data Bytes 0-3 will not be changed. | ||||
1: Direction = Read: The data bytes 0-3 will be transferred from the message object addressed by the MESSAGE_NUMBER to the corresponding IF2 registerset. | ||||
1: Direction = Write: The data bytes 0-3 will be transferred from the IF2 registerset to the message object addressed by the MESSAGE_NUMBER. | ||||
Note: The duration of the message transfer is independent of the number of bytes to be transferred. | ||||
16 | DATA_B | Access Data Bytes 4-7 | RW | 0 |
0: Data Bytes 4-7 will not be changed. | ||||
1: Direction = Read: The data bytes 4-7 will be transferred from the message object addressed by MESSAGE_NUMBER to the corresponding IF2 registerset. | ||||
1: Direction = Write: The data bytes 4-7 will be transferred from the IF2 registerset to the message object addressed by MESSAGE_NUMBER. | ||||
Note: The duration of the message transfer is independent of the number of bytes to be transferred. | ||||
15 | BUSY | Busy flag | RW | 0 |
0: No transfer between IF2 register set and message RAM is in progress. | ||||
1: Transfer between IF2 register set and message RAM is in progress. | ||||
This bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER. IF2 register set will be write protected. The bit is cleared after read/write action has been finished. | ||||
14 | DMAACTIVE | Activation of DMA feature for subsequent internal IF2 update | RW | 0 |
0: DMA request line is independent of IF2 activities. | ||||
1: DMA is requested after completed transfer between IF2 register set and message RAM. | ||||
The DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one. | ||||
Note: Due to the auto reset feature of the DMAACTIVE bit, this bit has to be set for each subsequent DMA cycle separately. | ||||
13:8 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x00 |
7:0 | MESSAGE_NUMBER | Number of message object in message RAM which is used for data transfer | RW | 0x1 |
0x00: Invalid message number | ||||
0x01-0x80: Valid message numbers | ||||
0x81-0xFF: Invalid message numbers |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4AE3 C124 0x4848 0124 | Instance | DCAN1 DCAN2 |
Description | IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Section 26.10.4.11.1 Structure of Message Objects. While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MXTD | MDIR | RESERVED | MSK |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MXTD | Mask Extended Identifier | RW | 1 |
0: The extended identifier bit (IDE) has no effect on the acceptance filtering. | ||||
1: The extended identifier bit (IDE) is used for acceptance filtering. | ||||
When 11-bit (“standard”) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. | ||||
30 | MDIR | Mask Message Direction | RW | 1 |
0: The message direction bit (Dir) has no effect on the acceptance filtering. | ||||
1: The message direction bit (Dir) is used for acceptance filtering. | ||||
29 | RESERVED | This bit is always read as 1. Writes have no effect. | R | 1 |
28:0 | MSK | Identifier Mask | RW | 0x1FFF FFFF |
0: The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care). | ||||
1: The corresponding bit in the identifier of the message object is used for acceptance filtering. |
DCAN |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4AE3 C128 0x4848 0128 | Instance | DCAN1 DCAN2 |
Description | IF2 arbitration register The Arbitration bits ID[28:0], XTD, and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0], MXTD, and MDIR) for acceptance filtering of incoming messages. A received message is stored into the valid message object with matching identifier and Direction = receive (data frame) or Direction = transmit (remote frame). Extended frames can be stored only in message objects with Xtd = 1, standard frames in message objects with Xtd = 0. If a received message (data frame or remote frame) matches more than one valid message objects, it is stored into the one with the lowest message number. The bits of the IF1/IF2 arbitration registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Section 26.10.4.11.1 Structure of Message Objects While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL | XTD | DIR | ID |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MSGVAL | Message valid | RW | 0 |
0: The message object is ignored by the message handler. | ||||
1: The message object is to be used by the message handler. | ||||
The software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the DCAN_CTL. This bit must also be reset if the messages object is no longer required. | ||||
30 | XTD | Extended identifier | RW | 0 |
0: The 11-bit (“standard”) Identifier is used for this message object. | ||||
1: The 29-bit (“extended”) Identifier is used for this message object. | ||||
29 | DIR | Message direction | RW | 0 |
0: Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, this message is stored in this message object. | ||||
1: Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = 1). | ||||
28:0 | ID | Message identifier | RW | 0x000 0000 |
ID[28:0]: 29-bit identifier (extended frame) | ||||
ID[28:18]: 11-bit identifier (standard frame) |
DCAN |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4AE3 C12C 0x4848 012C | Instance | DCAN1 DCAN2 |
Description | IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Section 26.10.4.11.1 Structure of Message Objects While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NEWDAT | MSGLST | INTPND | UMASK | TXIE | RXIE | RMTEN | TXRQST | EOB | RESERVED | DLC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
15 | NEWDAT | New data | RW | 0 |
0: No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software. | ||||
1: The message handler or the software has written new data into the data portion of this message object. | ||||
14 | MSGLST | Message lost (only valid for message objects with direction = receive) | RW | 0 |
0: No message lost since the last time when this bit was reset by the software. | ||||
1: The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten. | ||||
13 | INTPND | Interrupt pending | RW | 0 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. The Interrupt Identifier in DCAN_INT will point to this message object if there is no other interrupt source with higher priority. | ||||
12 | UMASK | Use acceptance mask | RW | 0 |
0: Mask ignored | ||||
1: Use mask (Msk[28:0], MXtd, and MDir) for acceptance filtering | ||||
If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. | ||||
11 | TXIE | Transmit interrupt enable | RW | 0 |
0: IntPnd will not be triggered after the successful transmission of a frame. | ||||
1: IntPnd will be triggered after the successful transmission of a frame. | ||||
10 | RXIE | Receive interrupt enable | RW | 0 |
0: IntPnd will not be triggered after the successful reception of a frame. | ||||
1: IntPnd will be triggered after the successful reception of a frame. | ||||
9 | RMTEN | Remote enable | RW | 0 |
0: At the reception of a remote frame, TxRqst is not changed. | ||||
1: At the reception of a remote frame, TxRqst is set. | ||||
8 | TXRQST | Transmit request | RW | 0 |
0: This message object is not waiting for a transmission. | ||||
1: The transmission of this message object is requested and is not yet done. | ||||
7 | EOB | End of Block | RW | 0 |
0: The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block. | ||||
1: The message object is a single message object or the last message object in a FIFO Buffer Block. | ||||
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one. | ||||
6:4 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
3:0 | DLC | Data length code | RW | 0x0 |
0-8: Data frame has 0-8 data bytes. | ||||
9-15 Data frame has 8 data bytes. | ||||
Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. |
DCAN |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4AE3 C130 0x4848 0130 | Instance | DCAN1 DCAN2 |
Description | IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_3 | DATA_2 | DATA_1 | DATA_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | DATA_3 | Data byte 3 | RW | 0x0 |
23:16 | DATA_2 | Data byte 2 | RW | 0x0 |
15:8 | DATA_1 | Data byte 1 | RW | 0x0 |
7:0 | DATA_0 | Data byte 0 | RW | 0x0 |
DCAN |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x4AE3 C134 0x4848 0134 | Instance | DCAN1 DCAN2 |
Description | IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of DCAN_IF1CMD/DCAN_IF2CMD register is one, IF1/IF2 register set is write protected. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_7 | DATA_6 | DATA_5 | DATA_4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | DATA_7 | Data byte 7 | RW | 0x0 |
23:16 | DATA_6 | Data byte 6 | RW | 0x0 |
15:8 | DATA_5 | Data byte 5 | RW | 0x0 |
7:0 | DATA_4 | Data byte 4 | RW | 0x0 |
DCAN |
Address Offset | 0x0000 0140 | ||
Physical Address | 0x4AE3 C140 0x4848 0140 | Instance | DCAN1 DCAN2 |
Description | IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in Section 26.10.4.11.1 Structure of Message Objects). The observation flags (Bits [4:0]) are used to determine, which data sections of the IF3 interface register set have to be read in order to complete a DMA read cycle. After all marked data sections are read, the DCAN is enabled to update the IF3 interface register set with new data. Any access order of single bytes or half-words is supported. When using byte or half-word accesses, a data section is marked as completed, if all bytes are read. NOTE: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses. A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables updating of IF3 interface register set with new data. To avoid data inconsistency, the DMA controller should be disabled before reconfiguring IF3 observation register. The status of the current read-cycle can be observed via status flags (Bits [12:8]). | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IF3_UPD | RESERVED | IF3_SDB | IF3_SDA | IF3_SC | IF3_SA | IF3_SM | RESERVED | DATAB | DATAA | CTRL | ARB | MASK |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
15 | IF3_UPD | IF3 Update Data | R | 0 |
0: No new data has been loaded since last IF3 read. | ||||
1: New data has been loaded since last IF3 read. | ||||
14:13 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
12 | IF3_SDB | IF3 Status of Data B read access | R | 0 |
0: All Data B bytes are already read out, or are not marked to be read. | ||||
1: Data B section has still data to be read out. | ||||
11 | IF3_SDA | IF3 Status of Data A read access | R | 0 |
0: All Data A bytes are already read out, or are not marked to be read. | ||||
1: Data A section has still data to be read out. | ||||
10 | IF3_SC | IF3 Status of control bits read access | R | 0 |
0: All control section bytes are already read out, or are not marked to be read. | ||||
1: Control section has still data to be read out. | ||||
9 | IF3_SA | IF3 Status of Arbitration data read access | R | 0 |
0: All Arbitration data bytes are already read out, or are not marked to be read. | ||||
1: Arbitration section has still data to be read out. | ||||
8 | IF3_SM | IF3 Status of Mask data read access | R | 0 |
0: All mask data bytes are already read out, or are not marked to be read. | ||||
1: Mask section has still data to be read out. | ||||
7:5 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
4 | DATAB | Data B read observation | RW | 0 |
0: Data B section has not to be read. | ||||
1: Data B section has to be read to enable next IF3 update. | ||||
3 | DATAA | Data A read observation | RW | 0 |
0: Data A section has not to be read. | ||||
1: Data A section has to be read to enable next IF3 update. | ||||
2 | CTRL | Ctrl read observation | RW | 0 |
0: Ctrl section has not to be read. | ||||
1: Ctrl section has to be read to enable next IF3 update. | ||||
1 | ARB | Arbitration data read observation | RW | 0 |
0: Arbitration data has not to be read. | ||||
1: Arbitration data has to be read to enable next IF3 update. | ||||
0 | MASK | Mask data read observation | RW | 0 |
0: Mask data has not to be read. | ||||
1: Mask data has to be read to enable next IF3 update. |
DCAN |
Address Offset | 0x0000 0144 | ||
Physical Address | 0x4AE3 C144 0x4848 0144 | Instance | DCAN1 DCAN2 |
Description | IF3 Mask Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MXTD | MDIR | RESERVED | MSK |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MXTD | Mask Extended Identifier | R | 1 |
0: The extended identifier bit (IDE) has no effect on the acceptance filtering. | ||||
1: The extended identifier bit (IDE) is used for acceptance filtering. | ||||
When 11-bit (“standard”) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. | ||||
30 | MDIR | Mask Message Direction | R | 1 |
0: The message direction bit (Dir) has no effect on the acceptance filtering. | ||||
1: The message direction bit (Dir) is used for acceptance filtering. | ||||
29 | RESERVED | These bits are always read as 1. Writes have no effect. | R | 1 |
28:0 | MSK | Identifier Mask | RW | 0x1FFF FFFF |
0: The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care). | ||||
1: The corresponding bit in the identifier of the message object is used for acceptance filtering. |
DCAN |
Address Offset | 0x0000 0148 | ||
Physical Address | 0x4AE3 C148 0x4848 0148 | Instance | DCAN1 DCAN2 |
Description | IF3 Arbitration Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSGVAL | XTD | DIR | ID |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MSGVAL | Message Valid | R | 0 |
0: The message object is ignored by the message handler. | ||||
1: The message object is to be used by the message handler. | ||||
The software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the DCAN_CTL. This bit must also be reset before the identifier ID[28:0], the control bits Xtd, Dir or DLC[3:0] are modified, or if the messages object is no longer required. | ||||
30 | XTD | Extended Identifier | R | 0 |
0: The 11-bit (“standard”) Identifier is used for this message object. | ||||
1: The 29-bit (“extended”) Identifier is used for this message object. | ||||
29 | DIR | Message Direction | R | 0 |
0: Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, this message is stored in this message object. | ||||
1: Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = 1). | ||||
28:0 | ID | Message Identifier | R | 0x0000 0000 |
ID[28:0]: 29-bit Identifier (“extended frame”) | ||||
ID[28:18]: 11-bit Identifier (“standard frame”) |
DCAN |
Address Offset | 0x0000 014C | ||
Physical Address | 0x4AE3 C14C 0x4848 014C | Instance | DCAN1 DCAN2 |
Description | IF3 Message Control Register | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NEWDAT | MSGLST | INTPND | UMASK | TXIE | RXIE | RMTEN | TXRQST | EOB | RESERVED | DLC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
15 | NEWDAT | New Data | R | 0 |
0: No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the software. | ||||
1: The message handler or the software has written new data into the data portion of this message object. | ||||
14 | MSGLST | Message Lost (only valid for message objects with direction = receive) | R | 0 |
0: No message lost since the last time when this bit was reset by the software. | ||||
1: The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten. | ||||
13 | INTPND | Interrupt Pending | R | 0 |
0: This message object is not the source of an interrupt. | ||||
1: This message object is the source of an interrupt. The Interrupt Identifier in DCAN_INT will point to this message object if there is no other interrupt source with higher priority. | ||||
12 | UMASK | Use Acceptance Mask | R | 0 |
0: Mask ignored | ||||
1: Use mask (Msk[28:0], MXtd, and MDir) for acceptance filtering | ||||
If the UMASK bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. | ||||
11 | TXIE | Transmit Interrupt enable | R | 0 |
0: IntPnd will not be triggered after the successful transmission of a frame. | ||||
1: IntPnd will be triggered after the successful transmission of a frame. | ||||
10 | RXIE | Receive Interrupt enable | R | 0 |
0: IntPnd will not be triggered after the successful reception of a frame. | ||||
1: IntPnd will be triggered after the successful reception of a frame. | ||||
9 | RMTEN | Remote enable | R | 0 |
0: At the reception of a remote frame, TxRqst is not changed. | ||||
1: At the reception of a remote frame, TxRqst is set. | ||||
8 | TXRQST | Transmit Request | R | 0 |
0: This message object is not waiting for a transmission. | ||||
1: The transmission of this message object is requested and is not yet done. | ||||
7 | EOB | End of Block | R | 0 |
0: The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block. | ||||
1: The message object is a single message object or the last message object in a FIFO Buffer Block. | ||||
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one. | ||||
6:4 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0 |
3:0 | DLC | Data Length Code | R | 0x0 |
0-8: Data frame has 0-8 data bits. | ||||
9-15: Data frame has 8 data bytes. | ||||
Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. |
DCAN |
Address Offset | 0x0000 0150 | ||
Physical Address | 0x4AE3 C150 0x4848 0150 | Instance | DCAN1 DCAN2 |
Description | IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_3 | DATA_2 | DATA_1 | DATA_0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31: 24 | DATA_3 | Data byte 3 | R | 0x0 |
23:16 | DATA_2 | Data byte 2 | R | 0x0 |
15:8 | DATA_1 | Data byte 1 | R | 0x0 |
7:0 | DATA_0 | Data byte 0 | R | 0x0 |
DCAN |
Address Offset | 0x0000 0154 | ||
Physical Address | 0x4AE3 C154 0x4848 0154 | Instance | DCAN1 DCAN2 |
Description | IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_7 | DATA_6 | DATA_5 | DATA_4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | DATA_7 | Data byte 7 | R | 0x0 |
23:16 | DATA_6 | Data byte 6 | R | 0x0 |
15:8 | DATA_5 | Data byte 5 | R | 0x0 |
7:0 | DATA_4 | Data byte 4 | R | 0x0 |
DCAN |
Address Offset | 0x0000 0160 | ||
Physical Address | 0x4AE3 C160 0x4848 0160 | Instance | DCAN1 DCAN2 |
Description | Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IF3UPDEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | IF3UPDEN | IF3 Update Enabled (for 1-32 message objects) | RW | 0x0000 0000 |
0: Automatic IF3 update is disabled for this message object. | ||||
1: Automatic IF3 update is enabled for this message object. A message object is scheduled to be copied to IF3 register set, if NewDat flag of the message object is active. |
DCAN |
Address Offset | 0x0000 0164 | ||
Physical Address | 0x4AE3 C164 0x4848 0164 | Instance | DCAN1 DCAN2 |
Description | Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IF3UPDEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | IF3UPDEN | IF3 Update Enabled (for 33-64 message objects) | RW | 0x0000 0000 |
0: Automatic IF3 update is disabled for this message object. | ||||
1: Automatic IF3 update is enabled for this message object. A message object is scheduled to be copied to IF3 register set, if NewDat flag of the message object is active. |
DCAN |
Address Offset | 0x0000 0168 | ||
Physical Address | 0x4AE3 C168 0x4848 0168 | Instance | DCAN1 DCAN2 |
Description | Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IF3UPDEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | IF3UPDEN | IF3 Update Enabled (for 65-96 message objects) | RW | 0x0000 0000 |
0: Automatic IF3 update is disabled for this message object. | ||||
1: Automatic IF3 update is enabled for this message object. A message object is scheduled to be copied to IF3 register set, if NewDat flag of the message object is active. |
DCAN |
Address Offset | 0x0000 016C | ||
Physical Address | 0x4AE3 C16C 0x4848 016C | Instance | DCAN1 DCAN2 |
Description | Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IF3UPDEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | IF3UPDEN | IF3 Update Enabled (for 97-128 message objects) | RW | 0x0000 0000 |
0: Automatic IF3 update is disabled for this message object. | ||||
1: Automatic IF3 update is enabled for this message object. A message object is scheduled to be copied to IF3 register set, if NewDat flag of the message object is active. |
DCAN |
Address Offset | 0x0000 01E0 | ||
Physical Address | 0x4AE3 C1E0 0x4848 01E0 | Instance | DCAN1 DCAN2 |
Description | TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed. The values of the IO control registers are only writable if INIT bit of the DCAN_CTL is set to 1. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PU | PD | OD | RESERVED | FUNC | DIR | OUT | IN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:19 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
18 | PU | CAN_TX pull up/pull down select. This bit is only active when CAN_TX is configured to be an input. | RW | 0 |
0: CAN_TX pull down is selected, when pull logic is active (PD = 0). | ||||
1: CAN_TX pull up is selected, when pull logic is active(PD = 0). | ||||
17 | PD | CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. | RW | 0 |
0: CAN_TX pull is active | ||||
1: CAN_TX pull is disabled | ||||
16 | OD | CAN_TX open drain enable. This bit is only active when CAN_TX is configured to be in GIO mode (FUNC=0). | RW | 0 |
0: The CAN_TX pin is configured in push/pull mode. | ||||
1: The CAN_TX pin is configured in open drain mode. | ||||
Forced to '0' if INIT bit of DCAN_CTL is reset. | ||||
15:4 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x000 |
3 | FUNC | CAN_TX function. This bit changes the function of the CAN_TX pin | RW | 0 |
0: CAN_TX pin is in GIO mode. | ||||
1: CAN_TX pin is in functional mode (as an output to transmit CAN data). | ||||
Forced to Tx output of the CAN core, if INIT bit of DCAN_CTL is reset. | ||||
2 | DIR | CAN_TX data direction. This bit controls the direction of the CAN_TX pin when it is configured to be in GIO mode only (FUNC=0) | RW | 0 |
0: The CAN_TX pin is an input. | ||||
1: The CAN_TX pin is an output | ||||
Forced to '1' if INIT bit of DCAN_CTL is reset. | ||||
1 | OUT | CAN_TX data out write. This bit is only active when CAN_TX pin is configured to be in GIO mode (FUNC = 0) and configured to be an output pin (DIR = 1). The value of this bit indicates the value to be output to the CAN_TX pin. | RW | 0 |
0: The CAN_TX pin is driven to logic low | ||||
1: The CAN_TX pin is driven to logic high | ||||
Forced to 1 if INIT bit of DCAN_CTL is reset. | ||||
0 | IN | CAN_TX data in | RW | - |
0: The CAN_TX pin is at logic low | ||||
1: The CAN_TX pin is at logic high | ||||
Note: When CAN_TX pin is connected to a CAN transceiver, an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed (e.g. while reset of the DCAN module). |
DCAN |
Address Offset | 0x0000 01E4 | ||
Physical Address | 0x4AE3 C1E4 0x4848 01E4 | Instance | DCAN1 DCAN2 |
Description | RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed. The values of the IO control registers are only writable if INIT bit of the DCAN_CTL is set to 1. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PU | PD | OD | RESERVED | FUNC | DIR | OUT | IN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:19 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x0000 |
18 | PU | CAN_RX pull up/pull down select. This bit is only active when CAN_RX is configured to be an input. | RW | 0 |
0: CAN_RX pull down is selected, when pull logic is active (PD = 0). | ||||
1: CAN_RX pull up is selected, when pull logic is active(PD = 0). | ||||
17 | PD | CAN_RX pull disable. This bit is only active when CAN_TX is configured to be an input. | RW | 0 |
0: CAN_RX pull is active | ||||
1: CAN_RX pull is disabled | ||||
16 | OD | CAN_RX open drain enable. This bit is only active when CAN_RX is configured to be in GIO mode (FUNC=0). | RW | 0 |
0: The CAN_RX pin is configured in push/pull mode. | ||||
1: The CAN_RX pin is configured in open drain mode. | ||||
Forced to '0' if INIT bit of DCAN_CTL is reset. | ||||
15:4 | RESERVED | These bits are always read as 0. Writes have no effect. | R | 0x000 |
3 | FUNC | CAN_RX function. This bit changes the function of the CAN_RX pin | RW | 0 |
0: CAN_RX pin is in GIO mode. | ||||
1: CAN_RX pin is in functional mode (as an input to receive CAN data). | ||||
Forced to '1' if INIT bit of DCAN_CTL is reset. | ||||
2 | DIR | CAN_RX data direction. This bit controls the direction of the CAN_RX pin when it is configured to be in GIO mode only (FUNC=0) | RW | 0 |
0: The CAN_RX pin is an input. | ||||
1: The CAN_RX pin is an output | ||||
Forced to '0' if INIT bit DCAN_CTL is reset. | ||||
1 | OUT | CAN_RX data out write. This bit is only active when CAN_RX pin is configured to be in GIO mode (FUNC = 0) and configured to be an output pin (DIR = 1). The value of this bit indicates the value to be output to the CAN_RX pin. | RW | 0 |
0: The CAN_RX pin is driven to logic low | ||||
1: The CAN_RX pin is driven to logic high | ||||
0 | IN | CAN_RX data in | RW | - |
0: The CAN_RX pin is at logic low | ||||
1: The CAN_RX pin is at logic high | ||||
DCAN |