SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4224 1200 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Enable. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYNCOFF | ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:2 | RESERVED | R | 0x0 | |
1 | SYNCOFF | VD output mask This register masks the VD output to the IPIPE module. This can be useful when one wants to read data from SDRAM which are stored in a double buffer. If the VD is not masked each time we start the module an new VD will be generated to the IPIPEIF module. Let's consider two buffers A and B of N lines each. *This bit field is latched by VD. | RW | 0x0 |
0x0: VD output mask is disabled. | ||||
0x1: VD output mask is enabled. | ||||
0 | ENABLE | IPIPE I/F Enable This register is used to start the operation of SDRAM buffer memory read and generates SYNC signals. This register is available when INPSRC1 or INPSCR2 = 1, 2 or 3. | RW | 0x0 |
0x0: IPIPE SDRAM I/F Disabled | ||||
0x1: IPIPE SDRAM I/F Enabled |
ISS ISP |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4224 1204 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Configuration #1 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INPSRC1 | DATASFT | CLKSEL | UNPACK | AVGFILT | RESERVED | RAW16_SDRAM | INPSRC2 | DECIM | ONESHOT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:14 | INPSRC1 | Selects the source for the mux (VPORT / ISIF / SDRAM) as well as the data format type. | RW | 0x0 |
0x0: RAW data from VPORT | ||||
0x1: RAW data from SDRAM | ||||
0x3: YUV data from SDRAM | ||||
0x2: ISIF_DARKFM Dark frame subtration or WDR merge is selected. Input ports to DFS/WDR submodule are VPORT and SDRAM. | ||||
13:11 | DATASFT | SDRAM read data shift This register is available when INPSRC1 or INPSRC2 = 1 or 2, i.e., when data are read from SDRAM. If UNPACK = 1 or 2, this value must be 0, 1, 2, 3, or 4. | RW | 0x0 |
0x6: If UNPACK=1 or 2, this value is invalid. If UNPACK=3 or (UNPACK=0 and RAW16=0) Output data[15:0] = '0000' read data[15:4] If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[9:0]) '000000' | ||||
0x1: If UNPACK 0 or RAW16=0 Output data[15:12] = '0000' Output data[11:0] = read data[10:0] '0'; If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[14:0]) '0' | ||||
0x7: If UNPACK=1 or 2, this value is invalid. If UNPACK=3 or (UNPACK=0 and RAW16=0) Output data[15:0] = '0000' read data[15:4] If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[8:0]) '0000000' | ||||
0x0: If UNPACK 0, or RAW16_SDRAM=0 Output data[15:12] = '0000' Output data[11:0] = read data[11:0] If UNPACK=0 and RAW16=1 Output data[15:0] = read data[15:0] | ||||
0x2: If UNPACK 0 or RAW16=0 Output data[15:12] = '0000' Output data[11:0] = read data[9:0] '00' If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[13:0]) '00' | ||||
0x4: If UNPACK 0 or RAW16=0 Output data[15:12] = '0000' Output data[11:0] = read data[7:0] '0000' If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[11:0]) '0000' | ||||
0x5: If UNPACK=1 or 2, this value is invalid. If UNPACK=3 or (UNPACK=0 and RAW16=0) Output data[15:0] = '0000' read data[15:4] If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[10:0]) '00000' | ||||
0x3: If UNPACK 0 or RAW16=0 Output data[15:12] = '0000' Output data[11:0] = read data[8:0] '000' If UNPACK=0 and RAW16=1 Output data[15:0] = (read data[12:0]) '000' | ||||
10 | CLKSEL | IPIPEIF IPIPE module pixel clock selection. This register shall be set to '1' when INPSRC1 or INPSRC2 = 1 or 3, i.e., data are solely read from SDRAM (VPORT inactive). | RW | 0x0 |
0x0: Selects the pixel clock from the VPORT. | ||||
0x1: Selects the pixel clock from the fractional clock divider. The fractional clock divider value is setup with the IPIPEIF_CLKDIV register. | ||||
9:8 | UNPACK | 8-Bit, 12-bit Packed Mode When sensor raw data are stored in 8-bit packed mode or 12-bit packed mode, this register should code 1 or 3. This register is effective when INPSRC = 1 or 2. | RW | 0x0 |
0x0: 16 bits / pixel | ||||
0x1: 8 bits / pixel | ||||
0x3: 12 bits / pixel | ||||
0x2: 8 bits / pixel + inverse A law (8 bits to 10 bits) | ||||
7 | AVGFILT | Averaging Filter It applies (1,2,1) filter for the RGB/YCbCr data. *This bit field is latched by VD. | RW | 0x0 |
0x0: off | ||||
0x1: on | ||||
6:5 | RESERVED | R | 0x0 | |
4 | RAW16_SDRAM | RAW16/12 format of SDRAM This affect how DATASFT works. This bit is valid if UNPCK=0. | RW | 0x0 |
3:2 | INPSRC2 | Selects the source for the mux (ISIF / SDRAM) as well as the data format type. | RW | 0x0 |
0x0: ISIF | ||||
0x1: from SDRAM (raw data) | ||||
0x3: from SDRAM (YUV data) | ||||
0x2: Dark frame subtration or WDR merge is selected. from ISIF SDRAM (Darkframe Subtraction : DFS, or WDR merge) | ||||
1 | DECIM | Pixel Decimation The decimation rate defined by RSZ register. *This bit field is latched by VD. | RW | 0x0 |
0x0: No decimation | ||||
0x1: Decimation | ||||
0 | ONESHOT | One Shot Mode This register is available when INPSRC = 1 or 3. | RW | 0x0 |
0x0: Continuous mode | ||||
0x1: One shot mode |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4224 1208 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Interval of HD / Start pixel in HD | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PPLN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:13 | RESERVED | R | 0x0 | |
12:0 | PPLN | Case-1: Interval of Horizontal Sync (HD) Specifies the interval of horizontal sync. This register is available when INPSRC = 1 or 3. Case-2: Start Pixel in Horizontal Sync (HD) Specifies the start pixel in horizontal sync. This register is available when INPSRC = 2 *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4224 120C | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Interval of VD / Start line in VD | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | LPFR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:13 | RESERVED | R | 0x0 | |
12:0 | LPFR | Case-1: Interval of Vertical Sync (VD) Specifies the interval of vertical sync. This register is available when INPSRC = 1 or 3. Case-2: Start Pixel in Vertical Sync (VD) Specifies the start line in vertical sync. This register is available when INPSRC = 2 *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4224 1210 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Number of valid pixels per line | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | HNUM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:13 | RESERVED | R | 0x0 | |
12:0 | HNUM | The Number of Valid Pixels in a Line Specifies the number of valid pixels in a horizontal line. This register is available when INPSRC = 1, 2 or 3 *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4224 1214 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Number of valid lines per frame | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VNUM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:13 | RESERVED | R | 0x0 | |
12:0 | VNUM | The Number of Valid Line in a Vertical Specifies the number of valid line in a vertical. This register is available when INPSRC = 1, 2 or 3 *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4224 1218 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Memory Address (Upper) | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDRU |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:11 | RESERVED | R | 0x0 | |
10:0 | ADDRU | Memory Address - Upper Memory address upper 11-bits are specified in units of 32-bytes This register is available when INPSRC = 1, 2 or 3. *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4224 121C | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Memory Address (Lower) | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDRL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | ADDRL | Memory Address - Lower Memory address lower 16-bits are specified in units of 32-bytes. This register is available when INPSRC = 1, 2 or 3. *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4224 1220 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Address offset | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADOFS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | ADOFS | Specifies the SDRAM stride for each line in units of 32-bytes. This register is available when reading data from SDRAM: INPSRC1 or INPSRC2 = 1, 2 or 3. Assuming that the first line is at position ADDR, the second line is at address ADDR+ ADOFS, etc. *This bit field is latched by VD. | RW | 0x0 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4224 1224 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Horizontal Resizing Parameter on IPIPE datapath | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RSZ |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x0 | |
6:0 | RSZ | Horizontal Resizing Parameter for IPIPE datapath Specifies the horizontal resizing parameter. The RSZ register can be configured within 16 to 112 range. This resizing ratio is determined by 16/RSZ (= 1/1 to 1/7) *This bit field is latched by VD. | RW | 0x10 |
ISS ISP |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4224 1228 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Gain Parameter | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAIN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9:0 | GAIN | Gain Parameter Specifies the gain applied to RAW data before it is forwarded to the IPIPE module. The gain value is expressed using the U10Q9 fractional format. The range is from 0.00195 (1/512) to 1.99805(1023/512). By default the unity gain is applied, i.e., IPIPEIF_GAIN.GAIN = 0x200. The gain is applied to RAW data only (IPIPEIF_CFG1.INPSRC2 != 3): the gain is not applied if the input data is YCbCr. *This bit field is latched by VD. | RW | 0x200 |
ISS ISP |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4224 122C | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF DPCM configuration This register applies only if IPIPEIF_CFG1.UNPACK = 1, i.e., RAW8 data is read from SDRAM. This register access is enabled by the Nokia Custom key | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BITS | PRED | ENA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:3 | RESERVED | R | 0x0 | |
2 | BITS | DPCM bit mode for SDRAM data This register access is enabled by the Nokia Custom key | RW | 0x0 |
0x0: 8bit to 10bit DPCM decompression | ||||
0x1: 8bit to 12bit DPCM decompression | ||||
1 | PRED | DPCM prediction mode for SDRAM data This register access is enabled by the Nokia Custom key | RW | 0x0 |
0x0: Simple predictor | ||||
0x1: Advanced predictor | ||||
0 | ENA | DPCM decompression enable for SDRAM data. | RW | 0x0 |
0x0: DPCM off (no decompression) | ||||
0x1: DPCM on |
ISS ISP |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4224 1230 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF Configuration #2 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YUV8P | YUV8 | DFSDIR | WENE | YUV16 | VDPOL | HDPOL | INTSW |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0x0 | |
7 | YUV8P | 8-bit YUV data unpacking to 16 bits When IPIPEIF_CFG1.INPSRC2 = 0 and IPIPEIF_CFG2.YUV16 = 1, the 8-bit YUV data are transformed into 16-bit YUV data. The way the data are unpacked from 8 bits to 16 bits is controlled by the IPIPEIF_CFG2.YUV8P register. The upper 8 bits of the 16-bit output are set to 0. | RW | 0x0 |
0x0: Y output on even pixels C output on odd pixels | ||||
0x1: C output on even pixels Y output on odd pixels | ||||
6 | YUV8 | YUV 8bit mode When ISIF_CFG1.INPSRC2 = 0 and YUV16 = 1, setting this bit to 1 enables the conversion from 8bit YUV input to 16bit YUV. This register is used when the input data from the ISIF module is 8-bit YUV data. | RW | 0x0 |
0x0: YUV16 input | ||||
0x1: YUV 8bit input This value is not allowed if IPIPEIF_CFG1.INPSRC1=1 and IPIPEIF_CFG1.INPSRC2=0 | ||||
5 | DFSDIR | DFS direction Selects the direction of dark frame subtraction. | RW | 0x0 |
0x0: In DFS mode VPORT IF(capture frame) - SDRAM (dark frame) In WDR mode Long Exposure: VPORT, Short Exposure: SDRAM | ||||
0x1: In DFS mode SDRAM (capture frame) - VPORT IF(dark frame) In WDR mode Long Exposure: SDRAM, Short Exposure: VPORT | ||||
4 | WENE | External WEN signal selection Do not use for OMAP4 and MONICA since there is not parallel interface at chip level. This register shall always be set to 0. | RW | 0x0 |
0x0: do not use external WEN | ||||
0x1: use external WEN | ||||
3 | YUV16 | Data type selection. The behavior of this bitfield depends upon other register settings. The functionality is best explained with the following pseudo code: if ((CFG1.INPSRC2==0 CFG2.YUV16) || CFG1.INPSRC2==3) { data_out[15:0] = yuv[15:0] } else if (CFG1.INPSRC2==1 CFG2.YUV16 CFG1.UNPACK=1) { data_out[15:8] = gain_clip[7:0]; data_out[ 7:0] = 0; } else { data_out[15: 0] = gain_clip[15:0]; } where: o data_out[15:0] = 16bit yuv or 16bit raw data to ipipe o yuv[15:0] = 16bit yuv data from 'horizontal pixel decimator' block. o gain_clip[15:0] = 16bit raw data from 'gain' block. | RW | 0x0 |
0x0: 12-bit RAW data | ||||
0x1: 16-bit YUV data | ||||
2 | VDPOL | VD Sync Polarity When input VD is active low SYNC pulse, this bit needs to be set to 1. | RW | 0x0 |
0x0: Positive | ||||
0x1: Negative | ||||
1 | HDPOL | HD Sync Polarity When input HD is active low SYNC pulse, this bit needs to be set to 1. | RW | 0x0 |
0x0: Positive | ||||
0x1: Negative | ||||
0 | INTSW | IPIPEIF interrupt source selection. This register select the interrupt source. | RW | 0x0 |
0x0: Start position of VD from VPORT interface | ||||
0x1: Start position of VD from ISIF module |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4224 1234 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF resize initial position - IPIPE data path. This value is not used in the c-model, as C-model expects the first pixel postion is the same as the first input pixel. To match HW with C-model, INIRSZ must be equal to the cycles between HD and the first cycle. In FDS/WDR mode, INIRSZ=PPLN | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ALNSYNC | INIRSZ |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:14 | RESERVED | R | 0x0 | |
13 | ALNSYNC | Align the HSYNC,VSYNC to initial position defined by INIRSZ. | RW | 0x0 |
0x0: Disable | ||||
0x1: Enable | ||||
12:0 | INIRSZ | Offset used to re-initialize the HD/VD position after resizer. From 0 to 8191 PCLK cycles. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4224 1238 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF output clipping value | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCLIP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | OCLIP | Output clipping value after gain control on IPIPE data path. This value is in U16Q0 data format. For nomarl mode, this value should be 0 OCLIP 4096 For WDR mode, this value should be 0 OCLIP 65536 | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4224 123C | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF data underflow detection | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | FIFOWMRKLVL | ENM2MSTALL | DTUDF |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:6 | RESERVED | R | 0x0 | |
5:2 | FIFOWMRKLVL | To guarantee that the FIFO does not overflow, the stall request is deasserted only when a certain number of locations in the FIFO are free. The number of free locations is configurable. A safe number of mandatory free locations can be configured by taking into consideration the pixel clock frequency (PCLK) with respect to that of the functional clock (FUNC CLK). The worst case occurs when PCLK = FUNC CLK. In that case, value should be configured to 0 (i.e. 16 free locations) so that the stall will be deasserted only when the 16-deep FIFO is completely empty. | RW | 0x8 |
0xD: Stall deassertion when FIFO has not more than 13 valid entry and SDRAM data available | ||||
0x1: Stall deassertion when FIFO has not more than 1 valid entry and SDRAM data available | ||||
0x7: Stall deassertion when FIFO has not more than 7 valid entry and SDRAM data available | ||||
0x6: Stall deassertion when FIFO has not more than 6 valid entry and SDRAM data available | ||||
0x0: Stall deassertion when FIFO is empty (16 free locations) and SDRAM data available | ||||
0x5: Stall deassertion when FIFO has not more than 5 valid entry and SDRAM data available | ||||
0xA: Stall deassertion when FIFO has not more than 10 valid entry and SDRAM data available | ||||
0x9: Stall deassertion when FIFO has not more than 9 valid entry and SDRAM data available | ||||
0xB: Stall deassertion when FIFO has not more than 11 valid entry and SDRAM data available | ||||
0x4: Stall deassertion when FIFO has not more than 4 valid entry and SDRAM data available | ||||
0x2: Stall deassertion when FIFO has not more than 2 valid entry and SDRAM data available | ||||
0xF: Stall deassertion when FIFO has not more than 15 valid entry and SDRAM data available | ||||
0xC: Stall deassertion when FIFO has not more than 12 valid entry and SDRAM data available | ||||
0x3: Stall deassertion when FIFO has not more than 3 valid entry and SDRAM data available | ||||
0x8: Stall deassertion when FIFO has not more than 8 valid entry and SDRAM data available | ||||
0xE: Stall deassertion when FIFO has not more than 14 valid entry and SDRAM data available | ||||
1 | ENM2MSTALL | Enable memory-to-memory stall mechanism | RW | 0x0 |
0x0: disable (no special stall mechanism for memory-to-memory use cases) | ||||
0x1: enable (stall mechanism for memory-to-memory use cases) | ||||
0 | DTUDF | Data under flow error status register. Reading 1 shows there is data under flow and at least one data is corrupted while reading from SDRAM. Writing 1 to this register clears (=0) the error (=1) status. Underflow errors are non recoverable at ISP5 level, need to do a soft reset at ISS level. The IPIPEIF_UDF interrupt is generated when an underflow happens. The interrupt avoids polling this register for errors. If ENM2MSTALL is enabled, then programmers need to ensure that the SW does not clear DTUDF[0] as this would reset the MTC read interface. DTUDF[0] can be cleared only in the on-the-fly operation where the stall mechanism will not work. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4224 1240 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF CLOCK DIVIDER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKDIV |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | CLKDIV | IPIPEIF clock rate configuration IPIPE/IPIPEIF clock frequency = M/N x clk_vpss clock frequency. We have M = CLKDIV[15:8] + 1 and N = CLKDIV[7:0] + 1 This register is available when IPIPEIF_CFG1.CLKSEL = 1. | RW | 0x1 |
ISS ISP |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4224 1244 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF defect pixel correction #1 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ENA | TH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:13 | RESERVED | R | 0x0 | |
12 | ENA | DPC enable. Applies DPC for video port data, ISIF input path. | RW | 0x0 |
0x0: Disable | ||||
0x1: Enable | ||||
11:0 | TH | DPC threshold value | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4224 1248 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF defect pixel correction #2 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENA | TH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:13 | RESERVED | R | 0x0 | |
12 | ENA | DPC enable. Applies DPC for SDRAM input path. | RW | 0x0 |
0x0: Disable | ||||
0x1: Enable | ||||
11:0 | TH | DPC threshold value | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4224 124C | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF DARK FRAME GAIN CONTROL - GAIN VALUE | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DFSGEN | DFSGVL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:11 | RESERVED | R | 0x0 | |
10 | DFSGEN | DFS gain control enable. This functionality is protected by an eFuse. Not available when ISP5_EFUSE4_EN = '0'. | RW | 0x0 |
9:0 | DFSGVL | DFS gain value. This functionality is protected by an eFuse. Not available when ISP5_EFUSE4_EN = '0'. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4224 1250 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF DARK FRAME GAIN CONTROL - THRESHOLD VALUE | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DFSGTH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:12 | RESERVED | R | 0x0 | |
11:0 | DFSGTH | DFS gain threshold value. This functionality is protected by an eFuse. Not available when ISP5_EFUSE4_EN = '0'. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4224 1254 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF HORIZONTAL RESIZING PARAMETER FOR H3A | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | DECIM | AVGFILT | RESERVED | RSZ |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:10 | RESERVED | R | 0x0 | |
9 | DECIM | Pixel Decimation Enable The decimation rate defined by the RSZ bitfield. *This bit field is latched by VD. | RW | 0x0 |
0x0: No Decimation | ||||
0x1: Decimate | ||||
8 | AVGFILT | Averaging Filter It applies a (1, 2, 1) filter for the RGB/YCbCr data. *This bit field is latched by VD. | RW | 0x0 |
0x0: Disable | ||||
0x1: Enable | ||||
7 | RESERVED | R | 0x0 | |
6:0 | RSZ | Horizontal Resizing Parameter for H3A datapath Specifies the horizontal resizing parameter. The RSZ register can be configured within 16 to 112 range. This resizing ratio is determined by 16/RSZ (= 1/1 to 1/7) *This bit field is latched by VD. | RW | 0x10 |
ISS ISP |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4224 1258 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF resize initial position - H3A data path. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ALNSYNC | INIRSZ |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:14 | RESERVED | R | 0x0 | |
13 | ALNSYNC | Align the HD, VD to initial position defined by the INIRSZ bit field. It means that HD and VD are effectivly shifted by INIRSZ pixel clock cycles. | RW | 0x0 |
0x0: Disable | ||||
0x1: Enable | ||||
12:0 | INIRSZ | Offset used to re-initialize the HD/VD position after resizer. From 0 to 8191 PCLK cycles. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4224 125C | Instance | ISP6P5_IPIPEIF |
Description | Parameters for Circular buffering | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSK_EOF | HSK_EN | CYN | RESERVED | CIR_EN | CBN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29 | HSK_EOF | Issue C_DONE at the end of frame. If this function is on, C_DONE is issued at the end of frame even if the last line not N-th line in ICM handshake sequence. If the last line is N-th line, C_DONE is issued regardless of this bit. *This bit field is latched by VD. | RW | 0x0 |
0x0: Disable C_DONE at the end of frame, unless it is the Nth line of ICM handshake proess. | ||||
0x1: Enalble output of C_DONE at the enf of frame. | ||||
28 | HSK_EN | Handshake with ICM is enabled Note: If ICM handshake is on in DFS/WDR mode (INPSRC1=2 or INPSRC2=2), memory-to-memory stall mechanism must be on (IPIPEIF_DTUDF.ENM2MSTALL=1) *This bit field is latched by VD. | RW | 0x0 |
0x0: Handshake with ICM is disabled | ||||
0x1: Handshake with ICM is enabled | ||||
27:16 | CYN | ICM Handshake cycle U12 *This bit field is latched by VD. | RW | 0x0 |
15:13 | RESERVED | R | 0x0 | |
12 | CIR_EN | Enable circular buffering *This bit field is latched by VD. | RW | 0x0 |
0x0: Circular buffering disabled | ||||
0x1: Circular buffer enabled | ||||
11:0 | CBN | Circular buffer cycle U12 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4224 1260 | Instance | ISP6P5_IPIPEIF |
Description | IPIPEIF WDR configuration for WDR merging | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DST | RESERVED | SBIT | LBIT | RESERVED | WGT_SEL | WDR_EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:21 | RESERVED | R | 0x0 | |
20:16 | DST | Down shift value after WDR merge *This bit field is latched by VD. | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:8 | SBIT | Shift up value for short exposure pixel Usually set (16- (bit width of long exposure pixels)). For example, if the input is 12 bit, set 4 here. *This bit field is latched by VD. | RW | 0x0 |
7:4 | LBIT | Shift up value for long exposure pixel Usually set (16- (bit width of long exposure pixels)). For example, if the input is 12 bit, set 4 here. *This bit field is latched by VD. | RW | 0x0 |
3:2 | RESERVED | R | 0x0 | |
1 | WGT_SEL | Select the source for weight calculation in WDR merge *This bit field is latched by VD. | RW | 0x0 |
0x0: Use long_exposure pixel for weight calculation | ||||
0x1: Use short exposure value for weight calculation. | ||||
0 | WDR_EN | Enable WDR merge (Two frame/single frame) When this function is enabled, WDR is used instead of DFS. *This bit field is latched by VD. | RW | 0x0 |
0x0: DISABLE WDR merging function. | ||||
0x1: ENABLE WDR function. WDR overtake DFS function. |
ISS ISP |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4224 1264 | Instance | ISP6P5_IPIPEIF |
Description | WDR Merge parameter AF_M | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AFE | RESERVED | AFM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:25 | RESERVED | R | 0x0 | |
24:20 | AFE | WDR Merge parameter AFE Exponential part of a value in weight calculation Unsigned 5bit *This bit field is latched by VD. | RW | 0x0 |
19:16 | RESERVED | R | 0x0 | |
15:0 | AFM | WDR Merge parameter AF_M Coefficient (mantissa) part of a value in weight calculation Signed 16bit *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4224 1268 | Instance | ISP6P5_IPIPEIF |
Description | WDR Merge parameter BF | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BF |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | BF | WDR Merge parameter BF Q0.15) The actual value is BF x 2^-16 x 2^-5 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4224 126C | Instance | ISP6P5_IPIPEIF |
Description | Gain difference between long exposure and short exposure | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GSHORT | GLONG |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | GSHORT | The gain applied to short exposure pixels. (U1.15) Usually, this value is 32768 *This bit field is latched by VD. For example, if the gain difference is x4, GDIFF = 8192 | RW | 0x0 |
15:0 | GLONG | The gain applied to long exposure pixels. (U1.15) Usually, this value is GLONG = 32768 * (short exposure gain in camera)/(long exposure gain in camera) *This bit field is latched by VD. For example, if the gain difference is x4, GDIFF = 8192 | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x4224 1270 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in WDR merging | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | THR | T (Threshold value) U16 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x4224 1274 | Instance | ISP6P5_IPIPEIF |
Description | White Balance used in weight calculation | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESERVED | R | 0x0 |
ISS ISP |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x4224 1278 | Instance | ISP6P5_IPIPEIF |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | RESERVED | R | 0x0 |
ISS ISP |
Address Offset | 0x0000 007C | ||
Physical Address | 0x4224 127C | Instance | ISP6P5_IPIPEIF |
Description | Black level for Long exposure input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LBK01 | RESERVED | LBK00 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:16 | LBK01 | Black level for long exposure pixel at [0, 1] (Odd pixel at even line) U12 *This bit field is latched by VD. | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:0 | LBK00 | Black level for long exposure pixel at [0, 0] (Even pixel at even line) U12 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4224 1280 | Instance | ISP6P5_IPIPEIF |
Description | Black level for Long exposure input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LBK11 | RESERVED | LBK10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:16 | LBK11 | Black level for long exposure pixel at [1, 1] (Odd pixel at odd line) U12 *This bit field is latched by VD. | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:0 | LBK10 | 1lack level for long exposure pixel at [1, 0 ] (Even pixel at odd line) U12 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4224 1284 | Instance | ISP6P5_IPIPEIF |
Description | Black level for short exposure input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SBK01 | RESERVED | SBK00 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:16 | SBK01 | Black level for short exposure pixel at [0, 1] (Odd pixel at even line) U12 *This bit field is latched by VD. | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:0 | SBK00 | Black level for short exposure pixel at [0, 0] (Even pixel at even line) U12 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4224 1288 | Instance | ISP6P5_IPIPEIF |
Description | Black level for short exposure input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SBK11 | RESERVED | SBK10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27:16 | SBK11 | Black level for short exposure pixel at [1, 1] (Odd pixel at odd line) U12 *This bit field is latched by VD. | RW | 0x0 |
15:12 | RESERVED | R | 0x0 | |
11:0 | SBK10 | 1lack level for short exposure pixel at [1, 0 ] (Even pixel at odd line) U12 *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 008C | ||
Physical Address | 0x4224 128C | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in motion adaptive filter | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAS | MAD |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | MAS | Slope in motion adaptive filter MAS = 32768/(D2-D1) U16 *This bit field is latched by VD. | RW | 0x0 |
15:0 | MAD | Threshold (D1) in motion adaptive filter U16 To disable MA filtering, put the maximum value (65535: default) *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4224 1290 | Instance | ISP6P5_IPIPEIF |
Description | Saturation parameters for VPORT input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VP_SAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | VP_SAT | Saturation value for VPORT input used in WDR split function for pseudo-long-exposure image Do disable, set maximum value (1048575: default) *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x4224 1294 | Instance | ISP6P5_IPIPEIF |
Description | Saturation parameters for VPORT input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VP_DCCLMP | VP_DSF | RESERVED | VP_SATEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | - | R | 0x0 |
15:8 | VP_DCCLMP | DC Clamp addition value for VPORT input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD. | RW | 0x0 |
7:3 | VP_DSF | Down shift value for VPORT input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD. | RW | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | VP_SATEN | Enable saturation function on VPort *This bit field is latched by VD. | RW | 0x0 |
0x0: Saturation/Down shift on VPORT input is disabled | ||||
0x1: Saturation/Down shift on VPORT input is enabled |
ISS ISP |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4224 1298 | Instance | ISP6P5_IPIPEIF |
Description | Saturation parameters for ISIF input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ISIF_SAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | ISIF_SAT | Saturation value for ISIF input used in WDR split function for pseudo-long-exposure image Do disable, set maximum value (1048575: default) *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 009C | ||
Physical Address | 0x4224 129C | Instance | ISP6P5_IPIPEIF |
Description | Saturation value for ISIF input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ISIF_DCCLMP | ISIF_DSF | RESERVED | ISIF_SATEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | - | R | 0x0 |
15:8 | ISIF_DCCLMP | DC Clamp addition value for ISIF input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD. | RW | 0x0 |
7:3 | ISIF_DSF | Down shift value for ISIF input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD. | RW | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | ISIF_SATEN | Enable saturation function on ISIF port *This bit field is latched by VD. | RW | 0x0 |
0x0: Saturation/Down shift on ISIF input is disabled | ||||
0x1: Saturation/Down shift on ISIF input is enabled |
ISS ISP |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4224 12A0 | Instance | ISP6P5_IPIPEIF |
Description | Saturation parameters for SDRAM input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SD_SAT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | SD_SAT | Saturation value for SDRAM input used in WDR split function for pseudo-long-exposure image Do disable, set maximum value (1048575: default) *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x4224 12A4 | Instance | ISP6P5_IPIPEIF |
Description | Saturation params for SDRAM input | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SD_DCCLMP | SD_DSF | RESERVED | SD_SATEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | - | R | 0x0 |
15:8 | SD_DCCLMP | DC Clamp addition value for SD Port input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD. | RW | 0x0 |
7:3 | SD_DSF | Down shift value for SDRAM input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD. | RW | 0x0 |
2:1 | RESERVED | R | 0x0 | |
0 | SD_SATEN | Enable saturation function on SDRAM *This bit field is latched by VD. | RW | 0x0 |
0x0: Saturation/Down shift on SDRAM input is disabled | ||||
0x1: Saturation/Down shift on SDRAM input is enabled |
ISS ISP |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4224 12A8 | Instance | ISP6P5_IPIPEIF |
Description | White Balance used in weight calculation | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LWB01 | RESERVED | LWB00 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:16 | LWB01 | White balance for pixels at [0, 1] (Odd pixel at even line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
15:13 | RESERVED | R | 0x0 | |
12:0 | LWB00 | White balance for pixels at [0, 0] (Even pixel at even line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
ISS ISP |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x4224 12AC | Instance | ISP6P5_IPIPEIF |
Description | White Balance used in weight calculation | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LWB11 | RESERVED | LWB10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:16 | LWB11 | White balance for pixels at [0, 1] (Odd pixel at odd line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
15:13 | RESERVED | R | 0x0 | |
12:0 | LWB10 | White balance for pixels at [1, 0] (Even pixel at odd line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
ISS ISP |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x4224 12B0 | Instance | ISP6P5_IPIPEIF |
Description | White Balance used in weight calculation | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SWB01 | RESERVED | SWB00 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:16 | SWB01 | White balance for pixels at [0, 1] (Odd pixel at even line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
15:13 | RESERVED | R | 0x0 | |
12:0 | SWB00 | White balance for pixels at [0, 0] (Even pixel at even line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
ISS ISP |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x4224 12B4 | Instance | ISP6P5_IPIPEIF |
Description | White Balance used in weight calculation | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SWB11 | RESERVED | SWB10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:16 | SWB11 | White balance for pixels at [0, 1] (Odd pixel at odd line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
15:13 | RESERVED | R | 0x0 | |
12:0 | SWB10 | White balance for pixels at [1, 0] (Even pixel at odd line) U4.9 (for gain=1.0, set 512) *This bit field is latched by VD. | RW | 0x200 |
ISS ISP |
Address Offset | 0x0000 00B8 | ||
Physical Address | 0x4224 12B8 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | XTHR1 | X_THR_1 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 00BC | ||
Physical Address | 0x4224 12BC | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in VP Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | XTHR2 | X_THR_2 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 00C0 | ||
Physical Address | 0x4224 12C0 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in VP Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | XTHR3 | X_THR_2 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 00C4 | ||
Physical Address | 0x4224 12C4 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | YTHR1 | Y_THR_1 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x4224 12C8 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | YTHR2 | Y_THR_2 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 00CC | ||
Physical Address | 0x4224 12CC | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | YTHR3 | Y_THR_3 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 00D0 | ||
Physical Address | 0x4224 12D0 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE1 | SLOPE_1 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 00D4 | ||
Physical Address | 0x4224 12D4 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE2 | SLOPE_2 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 00D8 | ||
Physical Address | 0x4224 12D8 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE3 | SLOPE_3 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 00DC | ||
Physical Address | 0x4224 12DC | Instance | ISP6P5_IPIPEIF |
Description | Slope value in VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE4 | SLOPE_4 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x4224 12E0 | Instance | ISP6P5_IPIPEIF |
Description | Configuration register for VP Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHIFT | RESERVED | LUTBITSEL | RESERVED | LUTSET | ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:24 | SHIFT | Shift value for PWL U5 *This bit field is latched by VD. | RW | 0x7 |
23:20 | RESERVED | R | 0x0 | |
19:16 | LUTBITSEL | LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD. | RW | 0x0 |
15:2 | RESERVED | R | 0x0 | |
1 | LUTSET | Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD. | RW | 0x0 |
0 | ENABLE | Enable for VP Decompanding *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 00E4 | ||
Physical Address | 0x4224 12E4 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | XTHR1 | X_THR_1 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 00E8 | ||
Physical Address | 0x4224 12E8 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | XTHR2 | X_THR_2 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 00EC | ||
Physical Address | 0x4224 12EC | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | XTHR3 | X_THR_2 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 00F0 | ||
Physical Address | 0x4224 12F0 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | YTHR1 | Y_THR_1 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 00F4 | ||
Physical Address | 0x4224 12F4 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | YTHR2 | Y_THR_2 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 00F8 | ||
Physical Address | 0x4224 12F8 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | YTHR3 | Y_THR_3 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x4224 12FC | Instance | ISP6P5_IPIPEIF |
Description | Slope value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE1 | SLOPE_1 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4224 1300 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE2 | SLOPE_2 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4224 1304 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE3 | SLOPE_3 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4224 1308 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE4 | SLOPE_4 (Slope value) U16 *This bit field is latched by VD. | RW | 0x80 |
ISS ISP |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4224 130C | Instance | ISP6P5_IPIPEIF |
Description | Configuration register for SD Decomanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHIFT | RESERVED | LUTBITSEL | RESERVED | LUTSET | ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:24 | SHIFT | Shift value for PWL U5 *This bit field is latched by VD. | RW | 0x7 |
23:20 | RESERVED | R | 0x0 | |
19:16 | LUTBITSEL | LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD. | RW | 0x0 |
15:2 | RESERVED | R | 0x0 | |
1 | LUTSET | Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD. | RW | 0x0 |
0 | ENABLE | Enable for VP Decompanding *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4224 1310 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in SD WDR Companding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | XTHR1 | X_THR_1 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4224 1314 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in WDR Companding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | XTHR2 | X_THR_2 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4224 1318 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XTHR3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:20 | RESERVED | R | 0x0 | |
19:0 | XTHR3 | X_THR_2 (Threshold value) U16 *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4224 131C | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in WDR Companding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | YTHR1 | Y_THR_1 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xfff |
ISS ISP |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4224 1320 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | YTHR2 | Y_THR_2 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4224 1324 | Instance | ISP6P5_IPIPEIF |
Description | Threshold value in WDR Companding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | YTHR3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | YTHR3 | Y_THR_3 (Threshold value) U20 *This bit field is latched by VD. | RW | 0xffff |
ISS ISP |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4224 1328 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE1 | SLOPE_1 (Slope value) U16 *This bit field is latched by VD. | RW | 0x8000 |
ISS ISP |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4224 132C | Instance | ISP6P5_IPIPEIF |
Description | Slope value in WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE1 | SLOPE_1 (Slope value) U16 *This bit field is latched by VD. | RW | 0x8000 |
ISS ISP |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4224 1330 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE1 | SLOPE_1 (Slope value) U16 *This bit field is latched by VD. | RW | 0x8000 |
ISS ISP |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x4224 1334 | Instance | ISP6P5_IPIPEIF |
Description | Slope value in WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOPE1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0 | |
15:0 | SLOPE1 | SLOPE_1 (Slope value) U16 *This bit field is latched by VD. | RW | 0x8000 |
ISS ISP |
Address Offset | 0x0000 0138 | ||
Physical Address | 0x4224 1338 | Instance | ISP6P5_IPIPEIF |
Description | Configuration register for WDR Decompanding | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHIFT | RESERVED | LUTBITSEL | RESERVED | LUTSET | ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:29 | RESERVED | R | 0x0 | |
28:24 | SHIFT | Shift value for PWL U5 *This bit field is latched by VD. | RW | 0xf |
23:20 | RESERVED | R | 0x0 | |
19:16 | LUTBITSEL | LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD. | RW | 0x0 |
15:2 | RESERVED | R | 0x0 | |
1 | LUTSET | Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD. | RW | 0x0 |
0 | ENABLE | Enable for VP Decompanding *This bit field is latched by VD. | RW | 0x0 |
ISS ISP |
Address Offset | 0x0000 013C | ||
Physical Address | 0x4224 133C | Instance | ISP6P5_IPIPEIF |
Description | Configuration register for WDR Merge | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MRGWTSFT | RESERVED | WDRCLIP |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:27 | RESERVED | R | 0x0 | |
26:24 | MRGWTSFT | Shift value for Weight black U3 *This bit field is latched by VD. | RW | 0x4 |
23:20 | RESERVED | R | 0x0 | |
19:0 | WDRCLIP | Clip value after WDR Merge *This bit field is latched by VD. | RW | 0xfffff |
ISS ISP |