SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The USB3_PHY PIPE i/f logic is software reset from USB1 over PIPE port by software assertion of the USBOTGSS_GUSB3PIPECTL[31] PHYSOFTRST bit to 0x1. The user must set USBOTGSS_GUSB3PIPECTL[31] PHYSOFTRST to 0x1 before triggering the serializer and deserializer power-up sequence in the CTRL_CORE_PHY_POWER_USB register. For more information on power-up sequence, see Section 28.2.4.2.3.1, USB3_PHY Power-Up/Down Sequences.
The user should deassert USBOTGSS_GUSB3PIPECTL[31] PHYSOFTRST to 0x0, after the serializer and deserializer power-up sequence completes. For more information, see Section 28.2.4.2.3.1, USB3_PHY Power-Up/Down Sequences.