SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Master receiver mode can be entered only from master transmitter mode. With any of the address formats (a), (b), or (c) (see Figure 26-7), if R/W_ is high, the module enters master receiver mode after the slave address byte and bit R/W_ are transmitted. Serial data bits received on bus line SDAl are shifted in synchronization with the self-generated clock pulses on SCLl.