SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0000 | ||
Physical Address | 0x489D D000 | Instance | VPE_VPDMA |
Description | This register follows the format described in PDR3.5 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCHEME | FUNC | RTL | MAJOR | VPDMA_LOAD_COMPLETE | VPDMA_ACCESS_TYPE | MINOR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | SCHEME | The scheme of the register used. Currently this is PDR 3.5 Scheme | R | 0x0 |
29:16 | FUNC | The funcition of the module being used. The value is for vpe0_vayu_vpdma. | R | 0x0 |
15:11 | RTL | RTL Release Version The PDR release number of this IP. After Bootup this value becomes the firmware Revision ID | R | 0x0 |
10:8 | MAJOR | Major Release Number | R | 0x0 |
7 | VPDMA_LOAD_COMPLETE | This bit will be 1 when the VPDMA state machines image and data image have successfuly been fetched and loaded. | R | 0x0 |
6 | VPDMA_ACCESS_TYPE | After bootup this bit states how DMA transaction are setup by lists or through register access. | R | 0x0 |
0x0 : Lists | ||||
0x1 : Register Access | ||||
5:0 | MINOR | Minor Release Number | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x489D D004 | Instance | VPE_VPDMA |
Description | The location of a new list to begin processing. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LIST_ADDR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | LIST_ADDR | Location of a new list of descriptors. This register must be written with the VPDMA Configuration Location after reset. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x489D D008 | Instance | VPE_VPDMA |
Description | The attributes of a new list. This register should always be written after list_addr. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LIST_NUM | RESERVED | STOP | RDY | LIST_TYPE | LIST_SIZE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:27 | RESERVED | R | 0x0 | |
26:24 | LIST_NUM | The list number that should be assigned to the list located at LIST_ADDR. If the list is still active this will block all future list writes until the list is available. | RW | 0x0 |
23:21 | RESERVED | R | 0x0 | |
20 | STOP | This bit is written with the LIST_NUMBER field to stop a self-modifying list. When this bit is written a one the list specified by the LIST_NUMBER is sent a stop signal and will finish the current frame of transfers and then free the list resources. | RW | 0x0 |
19 | RDY | This bit is low when a new list cannot be written to the VPE_LIST_ADDR register. The reasons this bit would be low are at initial startup if the LIST_MANAGER State Machine image has not completed loading. It also would be low if the last write to the LIST_ATTR attempted to start a list that is currently active. When this bit is low any writes to the list address register will cause access to not be accepted until this bit has set by the previous list having completed. | R | 0x0 |
18:16 | LIST_TYPE | The type of list that has been generated. | RW | 0x0 |
0x0 : Normal List | ||||
0x1 : Self-Modifying List | ||||
0x2 : List Doorbell Others Reserved for future use | ||||
15:0 | LIST_SIZE | Number of 128 bit word in the new list of descriptors. Writes to this register will activate the list in the list stack of the list manager and begin transfer of the list into VPDMA. This size can not be 0. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 000C | ||
Physical Address | 0x489D D00C | Instance | VPE_VPDMA |
Description | The register is used for processor to List Manager syncronization and status registers for the list. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LIST7_BUSY | LIST6_BUSY | LIST5_BUSY | LIST4_BUSY | LIST3_BUSY | LIST2_BUSY | LIST1_BUSY | LIST0_BUSY | RESERVED | SYNC_LISTS7 | SYNC_LISTS6 | SYNC_LISTS5 | SYNC_LISTS4 | SYNC_LISTS3 | SYNC_LISTS2 | SYNC_LISTS1 | SYNC_LISTS0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x0 | |
23 | LIST7_BUSY | The list 7 is currently running. Any attempt to load a new list to list 7 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
22 | LIST6_BUSY | The list 6 is currently running. Any attempt to load a new list to list 6 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
21 | LIST5_BUSY | The list 5 is currently running. Any attempt to load a new list to list 5 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
20 | LIST4_BUSY | The list 4 is currently running. Any attempt to load a new list to list 4 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
19 | LIST3_BUSY | The list 3 is currently running. Any attempt to load a new list to list 3 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
18 | LIST2_BUSY | The list 2 is currently running. Any attempt to load a new list to list 2 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
17 | LIST1_BUSY | The list 1 is currently running. Any attempt to load a new list to list 1 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
16 | LIST0_BUSY | The list 0 is currently running. Any attempt to load a new list to list 0 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0. | R | 0x0 |
15:8 | RESERVED | R | 0x0 | |
7 | SYNC_LISTS7 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it. | RW | 0x0 |
6 | SYNC_LISTS6 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it. | RW | 0x0 |
5 | SYNC_LISTS5 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it. | RW | 0x0 |
4 | SYNC_LISTS4 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it. | RW | 0x0 |
3 | SYNC_LISTS3 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it. | RW | 0x0 |
2 | SYNC_LISTS2 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it. | RW | 0x0 |
1 | SYNC_LISTS1 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it. | RW | 0x0 |
0 | SYNC_LISTS0 | Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x489D D018 | Instance | VPE_VPDMA |
Description | The registers used to set the background color for RGB | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RED | GREEN | BLUE | BLEND |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RED | The red value to give on an RGB data port for a blank pixel when using virtual video buffering | RW | 0x0 |
23:16 | GREEN | The green value to give on an RGB data port for a blank pixel when using virtual video buffering | RW | 0x0 |
15:8 | BLUE | The blue value to give on an RGB data port for a blank pixel when using virtual video buffering | RW | 0x0 |
7:0 | BLEND | The blend value to give on an RGB data port for a blank pixel when using virtual video buffering | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 001C | ||
Physical Address | 0x489D D01C | Instance | VPE_VPDMA |
Description | The registers used to set the background color for YUV | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | Y | CR | CB |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x0 | |
23:16 | Y | The Y value to give on a YUV data port for a blank pixel when using virtual video buffering | RW | 0x0 |
15:8 | CR | The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering | RW | 0x0 |
7:0 | CB | The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x489D D030 | Instance | VPE_VPDMA |
Description | Configures global parameters that are shared by all clients. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEC_BASE_CH |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0 | |
0 | SEC_BASE_CH | Use Secondary Channels for Mosaic mode | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x489D D034 | Instance | VPE_VPDMA |
Description | Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAX_WIDTH | MAX_HEIGHT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | MAX_WIDTH | The maximum width to use for setting of max_width 1 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023. | RW | 0x0 |
15:0 | MAX_HEIGHT | The maximum height to use for setting of max_height 1 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x489D D038 | Instance | VPE_VPDMA |
Description | Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAX_WIDTH | MAX_HEIGHT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | MAX_WIDTH | The maximum width to use for setting of max_width 2 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023. | RW | 0x0 |
15:0 | MAX_HEIGHT | The maximum height to use for setting of max_height 2 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 003C | ||
Physical Address | 0x489D D03C | Instance | VPE_VPDMA |
Description | Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAX_WIDTH | MAX_HEIGHT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | MAX_WIDTH | The maximum width to use for setting of max_width 3 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023. | RW | 0x0 |
15:0 | MAX_HEIGHT | The maximum height to use for setting of max_height 3 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x489D D040 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_GRPX3 | INT_STAT_GRPX2 | INT_STAT_GRPX1 | INT_STAT_SCALER_OUT | RESERVED | INT_STAT_SCALER_CHROMA | INT_STAT_SCALER_LUMA | INT_STAT_HQ_SCALER | RESERVED | INT_STAT_HQ_MV_OUT | RESERVED | INT_STAT_HQ_MV | RESERVED | INT_STAT_HQ_VID3_CHROMA | INT_STAT_HQ_VID3_LUMA | INT_STAT_HQ_VID2_CHROMA | INT_STAT_HQ_VID2_LUMA | INT_STAT_HQ_VID1_CHROMA | INT_STAT_HQ_VID1_LUMA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_GRPX3 | The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx3_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_GRPX2 | The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx2_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_GRPX1 | The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx1_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_SCALER_OUT | The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value | RW | 0x0 |
27:20 | RESERVED | Reserved | R | 0x00 |
19 | INT_STAT_SCALER_CHROMA | The last write DMA transaction has completed for channel scaler_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_SCALER_LUMA | The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_HQ_SCALER | The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | RESERVED | Reserved | R | 0x0 |
15 | INT_STAT_HQ_MV_OUT | The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14:13 | RESERVED | Reserved | R | 0x0 |
12 | INT_STAT_HQ_MV | The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11:6 | RESERVED | Reserved | R | 0x00 |
5 | INT_STAT_HQ_VID3_CHROMA | The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_HQ_VID3_LUMA | The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_HQ_VID2_CHROMA | The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_HQ_VID2_LUMA | The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_HQ_VID1_CHROMA | The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_HQ_VID1_LUMA | The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x489D D044 | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_GRPX3 | INT_MASK_GRPX2 | INT_MASK_GRPX1 | INT_MASK_SCALER_OUT | RESERVED | INT_MASK_SCALER_CHROMA | INT_MASK_SCALER_LUMA | INT_MASK_HQ_SCALER | RESERVED | INT_MASK_HQ_MV_OUT | RESERVED | INT_MASK_HQ_MV | RESERVED | INT_MASK_HQ_VID3_CHROMA | INT_MASK_HQ_VID3_LUMA | INT_MASK_HQ_VID2_CHROMA | INT_MASK_HQ_VID2_LUMA | INT_MASK_HQ_VID1_CHROMA | INT_MASK_HQ_VID1_LUMA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_GRPX3 | The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_GRPX2 | The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_GRPX1 | The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_SCALER_OUT | The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27:20 | RESERVED | Reserved | R | 0x00 |
19 | INT_MASK_SCALER_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_SCALER_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_HQ_SCALER | The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | RESERVED | Reserved | R | 0x0 |
15 | INT_MASK_HQ_MV_OUT | The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14:13 | RESERVED | Reserved | R | 0x0 |
12 | INT_MASK_HQ_MV | The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11:6 | RESERVED | Reserved | R | 0x00 |
5 | INT_MASK_HQ_VID3_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_HQ_VID3_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_HQ_VID2_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_HQ_VID2_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_HQ_VID1_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_HQ_VID1_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x489D D048 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_VIP1_MULT_PORTB_SRC9 | INT_STAT_VIP1_MULT_PORTB_SRC8 | INT_STAT_VIP1_MULT_PORTB_SRC7 | INT_STAT_VIP1_MULT_PORTB_SRC6 | INT_STAT_VIP1_MULT_PORTB_SRC5 | INT_STAT_VIP1_MULT_PORTB_SRC4 | INT_STAT_VIP1_MULT_PORTB_SRC3 | INT_STAT_VIP1_MULT_PORTB_SRC2 | INT_STAT_VIP1_MULT_PORTB_SRC1 | INT_STAT_VIP1_MULT_PORTB_SRC0 | INT_STAT_VIP1_MULT_PORTA_SRC15 | INT_STAT_VIP1_MULT_PORTA_SRC14 | INT_STAT_VIP1_MULT_PORTA_SRC13 | INT_STAT_VIP1_MULT_PORTA_SRC12 | INT_STAT_VIP1_MULT_PORTA_SRC11 | INT_STAT_VIP1_MULT_PORTA_SRC10 | INT_STAT_VIP1_MULT_PORTA_SRC9 | INT_STAT_VIP1_MULT_PORTA_SRC8 | INT_STAT_VIP1_MULT_PORTA_SRC7 | INT_STAT_VIP1_MULT_PORTA_SRC6 | INT_STAT_VIP1_MULT_PORTA_SRC5 | INT_STAT_VIP1_MULT_PORTA_SRC4 | INT_STAT_VIP1_MULT_PORTA_SRC3 | INT_STAT_VIP1_MULT_PORTA_SRC2 | INT_STAT_VIP1_MULT_PORTA_SRC1 | INT_STAT_VIP1_MULT_PORTA_SRC0 | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_VIP1_MULT_PORTB_SRC9 | The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_VIP1_MULT_PORTB_SRC8 | The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_VIP1_MULT_PORTB_SRC7 | The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_VIP1_MULT_PORTB_SRC6 | The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
27 | INT_STAT_VIP1_MULT_PORTB_SRC5 | The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
26 | INT_STAT_VIP1_MULT_PORTB_SRC4 | The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
25 | INT_STAT_VIP1_MULT_PORTB_SRC3 | The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
24 | INT_STAT_VIP1_MULT_PORTB_SRC2 | The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
23 | INT_STAT_VIP1_MULT_PORTB_SRC1 | The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
22 | INT_STAT_VIP1_MULT_PORTB_SRC0 | The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
21 | INT_STAT_VIP1_MULT_PORTA_SRC15 | The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
20 | INT_STAT_VIP1_MULT_PORTA_SRC14 | The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_VIP1_MULT_PORTA_SRC13 | The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_VIP1_MULT_PORTA_SRC12 | The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_VIP1_MULT_PORTA_SRC11 | The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | INT_STAT_VIP1_MULT_PORTA_SRC10 | The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
15 | INT_STAT_VIP1_MULT_PORTA_SRC9 | The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14 | INT_STAT_VIP1_MULT_PORTA_SRC8 | The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
13 | INT_STAT_VIP1_MULT_PORTA_SRC7 | The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
12 | INT_STAT_VIP1_MULT_PORTA_SRC6 | The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11 | INT_STAT_VIP1_MULT_PORTA_SRC5 | The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
10 | INT_STAT_VIP1_MULT_PORTA_SRC4 | The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
9 | INT_STAT_VIP1_MULT_PORTA_SRC3 | The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
8 | INT_STAT_VIP1_MULT_PORTA_SRC2 | The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
7 | INT_STAT_VIP1_MULT_PORTA_SRC1 | The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
6 | INT_STAT_VIP1_MULT_PORTA_SRC0 | The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
5:0 | RESERVED | Reserved | R | 0x00 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 004C | ||
Physical Address | 0x489D D04C | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_VIP1_MULT_PORTB_SRC9 | INT_MASK_VIP1_MULT_PORTB_SRC8 | INT_MASK_VIP1_MULT_PORTB_SRC7 | INT_MASK_VIP1_MULT_PORTB_SRC6 | INT_MASK_VIP1_MULT_PORTB_SRC5 | INT_MASK_VIP1_MULT_PORTB_SRC4 | INT_MASK_VIP1_MULT_PORTB_SRC3 | INT_MASK_VIP1_MULT_PORTB_SRC2 | INT_MASK_VIP1_MULT_PORTB_SRC1 | INT_MASK_VIP1_MULT_PORTB_SRC0 | INT_MASK_VIP1_MULT_PORTA_SRC15 | INT_MASK_VIP1_MULT_PORTA_SRC14 | INT_MASK_VIP1_MULT_PORTA_SRC13 | INT_MASK_VIP1_MULT_PORTA_SRC12 | INT_MASK_VIP1_MULT_PORTA_SRC11 | INT_MASK_VIP1_MULT_PORTA_SRC10 | INT_MASK_VIP1_MULT_PORTA_SRC9 | INT_MASK_VIP1_MULT_PORTA_SRC8 | INT_MASK_VIP1_MULT_PORTA_SRC7 | INT_MASK_VIP1_MULT_PORTA_SRC6 | INT_MASK_VIP1_MULT_PORTA_SRC5 | INT_MASK_VIP1_MULT_PORTA_SRC4 | INT_MASK_VIP1_MULT_PORTA_SRC3 | INT_MASK_VIP1_MULT_PORTA_SRC2 | INT_MASK_VIP1_MULT_PORTA_SRC1 | INT_MASK_VIP1_MULT_PORTA_SRC0 | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_VIP1_MULT_PORTB_SRC9 | The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_VIP1_MULT_PORTB_SRC8 | The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_VIP1_MULT_PORTB_SRC7 | The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_VIP1_MULT_PORTB_SRC6 | The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27 | INT_MASK_VIP1_MULT_PORTB_SRC5 | The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
26 | INT_MASK_VIP1_MULT_PORTB_SRC4 | The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
25 | INT_MASK_VIP1_MULT_PORTB_SRC3 | The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
24 | INT_MASK_VIP1_MULT_PORTB_SRC2 | The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
23 | INT_MASK_VIP1_MULT_PORTB_SRC1 | The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
22 | INT_MASK_VIP1_MULT_PORTB_SRC0 | The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
21 | INT_MASK_VIP1_MULT_PORTA_SRC15 | The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
20 | INT_MASK_VIP1_MULT_PORTA_SRC14 | The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_VIP1_MULT_PORTA_SRC13 | The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_VIP1_MULT_PORTA_SRC12 | The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_VIP1_MULT_PORTA_SRC11 | The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | INT_MASK_VIP1_MULT_PORTA_SRC10 | The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
15 | INT_MASK_VIP1_MULT_PORTA_SRC9 | The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14 | INT_MASK_VIP1_MULT_PORTA_SRC8 | The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
13 | INT_MASK_VIP1_MULT_PORTA_SRC7 | The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
12 | INT_MASK_VIP1_MULT_PORTA_SRC6 | The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11 | INT_MASK_VIP1_MULT_PORTA_SRC5 | The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
10 | INT_MASK_VIP1_MULT_PORTA_SRC4 | The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
9 | INT_MASK_VIP1_MULT_PORTA_SRC3 | The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
8 | INT_MASK_VIP1_MULT_PORTA_SRC2 | The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
7 | INT_MASK_VIP1_MULT_PORTA_SRC1 | The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
6 | INT_MASK_VIP1_MULT_PORTA_SRC0 | The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
5:0 | RESERVED | Reserved | R | 0x00 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x489D D050 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_VIP1_MULT_ANCB_SRC9 | INT_STAT_VIP1_MULT_ANCB_SRC8 | INT_STAT_VIP1_MULT_ANCB_SRC7 | INT_STAT_VIP1_MULT_ANCB_SRC6 | INT_STAT_VIP1_MULT_ANCB_SRC5 | INT_STAT_VIP1_MULT_ANCB_SRC4 | INT_STAT_VIP1_MULT_ANCB_SRC3 | INT_STAT_VIP1_MULT_ANCB_SRC2 | INT_STAT_VIP1_MULT_ANCB_SRC1 | INT_STAT_VIP1_MULT_ANCB_SRC0 | INT_STAT_VIP1_MULT_ANCA_SRC15 | INT_STAT_VIP1_MULT_ANCA_SRC14 | INT_STAT_VIP1_MULT_ANCA_SRC13 | INT_STAT_VIP1_MULT_ANCA_SRC12 | INT_STAT_VIP1_MULT_ANCA_SRC11 | INT_STAT_VIP1_MULT_ANCA_SRC10 | INT_STAT_VIP1_MULT_ANCA_SRC9 | INT_STAT_VIP1_MULT_ANCA_SRC8 | INT_STAT_VIP1_MULT_ANCA_SRC7 | INT_STAT_VIP1_MULT_ANCA_SRC6 | INT_STAT_VIP1_MULT_ANCA_SRC5 | INT_STAT_VIP1_MULT_ANCA_SRC4 | INT_STAT_VIP1_MULT_ANCA_SRC3 | INT_STAT_VIP1_MULT_ANCA_SRC2 | INT_STAT_VIP1_MULT_ANCA_SRC1 | INT_STAT_VIP1_MULT_ANCA_SRC0 | INT_STAT_VIP1_MULT_PORTB_SRC15 | INT_STAT_VIP1_MULT_PORTB_SRC14 | INT_STAT_VIP1_MULT_PORTB_SRC13 | INT_STAT_VIP1_MULT_PORTB_SRC12 | INT_STAT_VIP1_MULT_PORTB_SRC11 | INT_STAT_VIP1_MULT_PORTB_SRC10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_VIP1_MULT_ANCB_SRC9 | The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_VIP1_MULT_ANCB_SRC8 | The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_VIP1_MULT_ANCB_SRC7 | The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_VIP1_MULT_ANCB_SRC6 | The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
27 | INT_STAT_VIP1_MULT_ANCB_SRC5 | The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
26 | INT_STAT_VIP1_MULT_ANCB_SRC4 | The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
25 | INT_STAT_VIP1_MULT_ANCB_SRC3 | The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
24 | INT_STAT_VIP1_MULT_ANCB_SRC2 | The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
23 | INT_STAT_VIP1_MULT_ANCB_SRC1 | The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
22 | INT_STAT_VIP1_MULT_ANCB_SRC0 | The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
21 | INT_STAT_VIP1_MULT_ANCA_SRC15 | The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
20 | INT_STAT_VIP1_MULT_ANCA_SRC14 | The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_VIP1_MULT_ANCA_SRC13 | The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_VIP1_MULT_ANCA_SRC12 | The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_VIP1_MULT_ANCA_SRC11 | The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | INT_STAT_VIP1_MULT_ANCA_SRC10 | The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
15 | INT_STAT_VIP1_MULT_ANCA_SRC9 | The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14 | INT_STAT_VIP1_MULT_ANCA_SRC8 | The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
13 | INT_STAT_VIP1_MULT_ANCA_SRC7 | The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
12 | INT_STAT_VIP1_MULT_ANCA_SRC6 | The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11 | INT_STAT_VIP1_MULT_ANCA_SRC5 | The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
10 | INT_STAT_VIP1_MULT_ANCA_SRC4 | The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
9 | INT_STAT_VIP1_MULT_ANCA_SRC3 | The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
8 | INT_STAT_VIP1_MULT_ANCA_SRC2 | The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
7 | INT_STAT_VIP1_MULT_ANCA_SRC1 | The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
6 | INT_STAT_VIP1_MULT_ANCA_SRC0 | The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
5 | INT_STAT_VIP1_MULT_PORTB_SRC15 | The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_VIP1_MULT_PORTB_SRC14 | The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_VIP1_MULT_PORTB_SRC13 | The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_VIP1_MULT_PORTB_SRC12 | The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_VIP1_MULT_PORTB_SRC11 | The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_VIP1_MULT_PORTB_SRC10 | The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x489D D054 | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_VIP1_MULT_ANCB_SRC9 | INT_MASK_VIP1_MULT_ANCB_SRC8 | INT_MASK_VIP1_MULT_ANCB_SRC7 | INT_MASK_VIP1_MULT_ANCB_SRC6 | INT_MASK_VIP1_MULT_ANCB_SRC5 | INT_MASK_VIP1_MULT_ANCB_SRC4 | INT_MASK_VIP1_MULT_ANCB_SRC3 | INT_MASK_VIP1_MULT_ANCB_SRC2 | INT_MASK_VIP1_MULT_ANCB_SRC1 | INT_MASK_VIP1_MULT_ANCB_SRC0 | INT_MASK_VIP1_MULT_ANCA_SRC15 | INT_MASK_VIP1_MULT_ANCA_SRC14 | INT_MASK_VIP1_MULT_ANCA_SRC13 | INT_MASK_VIP1_MULT_ANCA_SRC12 | INT_MASK_VIP1_MULT_ANCA_SRC11 | INT_MASK_VIP1_MULT_ANCA_SRC10 | INT_MASK_VIP1_MULT_ANCA_SRC9 | INT_MASK_VIP1_MULT_ANCA_SRC8 | INT_MASK_VIP1_MULT_ANCA_SRC7 | INT_MASK_VIP1_MULT_ANCA_SRC6 | INT_MASK_VIP1_MULT_ANCA_SRC5 | INT_MASK_VIP1_MULT_ANCA_SRC4 | INT_MASK_VIP1_MULT_ANCA_SRC3 | INT_MASK_VIP1_MULT_ANCA_SRC2 | INT_MASK_VIP1_MULT_ANCA_SRC1 | INT_MASK_VIP1_MULT_ANCA_SRC0 | INT_MASK_VIP1_MULT_PORTB_SRC15 | INT_MASK_VIP1_MULT_PORTB_SRC14 | INT_MASK_VIP1_MULT_PORTB_SRC13 | INT_MASK_VIP1_MULT_PORTB_SRC12 | INT_MASK_VIP1_MULT_PORTB_SRC11 | INT_MASK_VIP1_MULT_PORTB_SRC10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_VIP1_MULT_ANCB_SRC9 | The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_VIP1_MULT_ANCB_SRC8 | The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_VIP1_MULT_ANCB_SRC7 | The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_VIP1_MULT_ANCB_SRC6 | The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27 | INT_MASK_VIP1_MULT_ANCB_SRC5 | The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
26 | INT_MASK_VIP1_MULT_ANCB_SRC4 | The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
25 | INT_MASK_VIP1_MULT_ANCB_SRC3 | The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
24 | INT_MASK_VIP1_MULT_ANCB_SRC2 | The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
23 | INT_MASK_VIP1_MULT_ANCB_SRC1 | The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
22 | INT_MASK_VIP1_MULT_ANCB_SRC0 | The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
21 | INT_MASK_VIP1_MULT_ANCA_SRC15 | The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
20 | INT_MASK_VIP1_MULT_ANCA_SRC14 | The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_VIP1_MULT_ANCA_SRC13 | The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_VIP1_MULT_ANCA_SRC12 | The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_VIP1_MULT_ANCA_SRC11 | The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | INT_MASK_VIP1_MULT_ANCA_SRC10 | The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
15 | INT_MASK_VIP1_MULT_ANCA_SRC9 | The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14 | INT_MASK_VIP1_MULT_ANCA_SRC8 | The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
13 | INT_MASK_VIP1_MULT_ANCA_SRC7 | The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
12 | INT_MASK_VIP1_MULT_ANCA_SRC6 | The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11 | INT_MASK_VIP1_MULT_ANCA_SRC5 | The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
10 | INT_MASK_VIP1_MULT_ANCA_SRC4 | The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
9 | INT_MASK_VIP1_MULT_ANCA_SRC3 | The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
8 | INT_MASK_VIP1_MULT_ANCA_SRC2 | The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
7 | INT_MASK_VIP1_MULT_ANCA_SRC1 | The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
6 | INT_MASK_VIP1_MULT_ANCA_SRC0 | The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
5 | INT_MASK_VIP1_MULT_PORTB_SRC15 | The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_VIP1_MULT_PORTB_SRC14 | The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_VIP1_MULT_PORTB_SRC13 | The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_VIP1_MULT_PORTB_SRC12 | The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_VIP1_MULT_PORTB_SRC11 | The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_VIP1_MULT_PORTB_SRC10 | The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x489D D058 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_VIP2_MULT_PORTB_SRC3 | INT_STAT_VIP2_MULT_PORTB_SRC2 | INT_STAT_VIP2_MULT_PORTB_SRC1 | INT_STAT_VIP2_MULT_PORTB_SRC0 | INT_STAT_VIP2_MULT_PORTA_SRC15 | INT_STAT_VIP2_MULT_PORTA_SRC14 | INT_STAT_VIP2_MULT_PORTA_SRC13 | INT_STAT_VIP2_MULT_PORTA_SRC12 | INT_STAT_VIP2_MULT_PORTA_SRC11 | INT_STAT_VIP2_MULT_PORTA_SRC10 | INT_STAT_VIP2_MULT_PORTA_SRC9 | INT_STAT_VIP2_MULT_PORTA_SRC8 | INT_STAT_VIP2_MULT_PORTA_SRC7 | INT_STAT_VIP2_MULT_PORTA_SRC6 | INT_STAT_VIP2_MULT_PORTA_SRC5 | INT_STAT_VIP2_MULT_PORTA_SRC4 | INT_STAT_VIP2_MULT_PORTA_SRC3 | INT_STAT_VIP2_MULT_PORTA_SRC2 | INT_STAT_VIP2_MULT_PORTA_SRC1 | INT_STAT_VIP2_MULT_PORTA_SRC0 | INT_STAT_VIP1_PORTB_RGB | INT_STAT_VIP1_PORTA_RGB | INT_STAT_VIP1_PORTB_CHROMA | INT_STAT_VIP1_PORTB_LUMA | INT_STAT_VIP1_PORTA_CHROMA | INT_STAT_VIP1_PORTA_LUMA | INT_STAT_VIP1_MULT_ANCB_SRC15 | INT_STAT_VIP1_MULT_ANCB_SRC14 | INT_STAT_VIP1_MULT_ANCB_SRC13 | INT_STAT_VIP1_MULT_ANCB_SRC12 | INT_STAT_VIP1_MULT_ANCB_SRC11 | INT_STAT_VIP1_MULT_ANCB_SRC10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_VIP2_MULT_PORTB_SRC3 | The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_VIP2_MULT_PORTB_SRC2 | The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_VIP2_MULT_PORTB_SRC1 | The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_VIP2_MULT_PORTB_SRC0 | The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
27 | INT_STAT_VIP2_MULT_PORTA_SRC15 | The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
26 | INT_STAT_VIP2_MULT_PORTA_SRC14 | The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
25 | INT_STAT_VIP2_MULT_PORTA_SRC13 | The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
24 | INT_STAT_VIP2_MULT_PORTA_SRC12 | The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
23 | INT_STAT_VIP2_MULT_PORTA_SRC11 | The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
22 | INT_STAT_VIP2_MULT_PORTA_SRC10 | The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
21 | INT_STAT_VIP2_MULT_PORTA_SRC9 | The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
20 | INT_STAT_VIP2_MULT_PORTA_SRC8 | The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_VIP2_MULT_PORTA_SRC7 | The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_VIP2_MULT_PORTA_SRC6 | The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_VIP2_MULT_PORTA_SRC5 | The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | INT_STAT_VIP2_MULT_PORTA_SRC4 | The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
15 | INT_STAT_VIP2_MULT_PORTA_SRC3 | The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14 | INT_STAT_VIP2_MULT_PORTA_SRC2 | The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
13 | INT_STAT_VIP2_MULT_PORTA_SRC1 | The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
12 | INT_STAT_VIP2_MULT_PORTA_SRC0 | The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11 | INT_STAT_VIP1_PORTB_RGB | The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
10 | INT_STAT_VIP1_PORTA_RGB | The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
9 | INT_STAT_VIP1_PORTB_CHROMA | The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
8 | INT_STAT_VIP1_PORTB_LUMA | The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
7 | INT_STAT_VIP1_PORTA_CHROMA | The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
6 | INT_STAT_VIP1_PORTA_LUMA | The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
5 | INT_STAT_VIP1_MULT_ANCB_SRC15 | The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_VIP1_MULT_ANCB_SRC14 | The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_VIP1_MULT_ANCB_SRC13 | The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_VIP1_MULT_ANCB_SRC12 | The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_VIP1_MULT_ANCB_SRC11 | The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_VIP1_MULT_ANCB_SRC10 | The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 005C | ||
Physical Address | 0x489D D05C | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_VIP2_MULT_PORTB_SRC3 | INT_MASK_VIP2_MULT_PORTB_SRC2 | INT_MASK_VIP2_MULT_PORTB_SRC1 | INT_MASK_VIP2_MULT_PORTB_SRC0 | INT_MASK_VIP2_MULT_PORTA_SRC15 | INT_MASK_VIP2_MULT_PORTA_SRC14 | INT_MASK_VIP2_MULT_PORTA_SRC13 | INT_MASK_VIP2_MULT_PORTA_SRC12 | INT_MASK_VIP2_MULT_PORTA_SRC11 | INT_MASK_VIP2_MULT_PORTA_SRC10 | INT_MASK_VIP2_MULT_PORTA_SRC9 | INT_MASK_VIP2_MULT_PORTA_SRC8 | INT_MASK_VIP2_MULT_PORTA_SRC7 | INT_MASK_VIP2_MULT_PORTA_SRC6 | INT_MASK_VIP2_MULT_PORTA_SRC5 | INT_MASK_VIP2_MULT_PORTA_SRC4 | INT_MASK_VIP2_MULT_PORTA_SRC3 | INT_MASK_VIP2_MULT_PORTA_SRC2 | INT_MASK_VIP2_MULT_PORTA_SRC1 | INT_MASK_VIP2_MULT_PORTA_SRC0 | INT_MASK_VIP1_PORTB_RGB | INT_MASK_VIP1_PORTA_RGB | INT_MASK_VIP1_PORTB_CHROMA | INT_MASK_VIP1_PORTB_LUMA | INT_MASK_VIP1_PORTA_CHROMA | INT_MASK_VIP1_PORTA_LUMA | INT_MASK_VIP1_MULT_ANCB_SRC15 | INT_MASK_VIP1_MULT_ANCB_SRC14 | INT_MASK_VIP1_MULT_ANCB_SRC13 | INT_MASK_VIP1_MULT_ANCB_SRC12 | INT_MASK_VIP1_MULT_ANCB_SRC11 | INT_MASK_VIP1_MULT_ANCB_SRC10 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_VIP2_MULT_PORTB_SRC3 | The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_VIP2_MULT_PORTB_SRC2 | The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_VIP2_MULT_PORTB_SRC1 | The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_VIP2_MULT_PORTB_SRC0 | The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27 | INT_MASK_VIP2_MULT_PORTA_SRC15 | The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
26 | INT_MASK_VIP2_MULT_PORTA_SRC14 | The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
25 | INT_MASK_VIP2_MULT_PORTA_SRC13 | The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
24 | INT_MASK_VIP2_MULT_PORTA_SRC12 | The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
23 | INT_MASK_VIP2_MULT_PORTA_SRC11 | The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
22 | INT_MASK_VIP2_MULT_PORTA_SRC10 | The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
21 | INT_MASK_VIP2_MULT_PORTA_SRC9 | The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
20 | INT_MASK_VIP2_MULT_PORTA_SRC8 | The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_VIP2_MULT_PORTA_SRC7 | The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_VIP2_MULT_PORTA_SRC6 | The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_VIP2_MULT_PORTA_SRC5 | The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | INT_MASK_VIP2_MULT_PORTA_SRC4 | The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
15 | INT_MASK_VIP2_MULT_PORTA_SRC3 | The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14 | INT_MASK_VIP2_MULT_PORTA_SRC2 | The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
13 | INT_MASK_VIP2_MULT_PORTA_SRC1 | The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
12 | INT_MASK_VIP2_MULT_PORTA_SRC0 | The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11 | INT_MASK_VIP1_PORTB_RGB | The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
10 | INT_MASK_VIP1_PORTA_RGB | The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
9 | INT_MASK_VIP1_PORTB_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
8 | INT_MASK_VIP1_PORTB_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
7 | INT_MASK_VIP1_PORTA_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
6 | INT_MASK_VIP1_PORTA_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
5 | INT_MASK_VIP1_MULT_ANCB_SRC15 | The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_VIP1_MULT_ANCB_SRC14 | The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_VIP1_MULT_ANCB_SRC13 | The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_VIP1_MULT_ANCB_SRC12 | The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_VIP1_MULT_ANCB_SRC11 | The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_VIP1_MULT_ANCB_SRC10 | The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x489D D060 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_VIP2_MULT_ANCB_SRC3 | INT_STAT_VIP2_MULT_ANCB_SRC2 | INT_STAT_VIP2_MULT_ANCB_SRC1 | INT_STAT_VIP2_MULT_ANCB_SRC0 | INT_STAT_VIP2_MULT_ANCA_SRC15 | INT_STAT_VIP2_MULT_ANCA_SRC14 | INT_STAT_VIP2_MULT_ANCA_SRC13 | INT_STAT_VIP2_MULT_ANCA_SRC12 | INT_STAT_VIP2_MULT_ANCA_SRC11 | INT_STAT_VIP2_MULT_ANCA_SRC10 | INT_STAT_VIP2_MULT_ANCA_SRC9 | INT_STAT_VIP2_MULT_ANCA_SRC8 | INT_STAT_VIP2_MULT_ANCA_SRC7 | INT_STAT_VIP2_MULT_ANCA_SRC6 | INT_STAT_VIP2_MULT_ANCA_SRC5 | INT_STAT_VIP2_MULT_ANCA_SRC4 | INT_STAT_VIP2_MULT_ANCA_SRC3 | INT_STAT_VIP2_MULT_ANCA_SRC2 | INT_STAT_VIP2_MULT_ANCA_SRC1 | INT_STAT_VIP2_MULT_ANCA_SRC0 | INT_STAT_VIP2_MULT_PORTB_SRC15 | INT_STAT_VIP2_MULT_PORTB_SRC14 | INT_STAT_VIP2_MULT_PORTB_SRC13 | INT_STAT_VIP2_MULT_PORTB_SRC12 | INT_STAT_VIP2_MULT_PORTB_SRC11 | INT_STAT_VIP2_MULT_PORTB_SRC10 | INT_STAT_VIP2_MULT_PORTB_SRC9 | INT_STAT_VIP2_MULT_PORTB_SRC8 | INT_STAT_VIP2_MULT_PORTB_SRC7 | INT_STAT_VIP2_MULT_PORTB_SRC6 | INT_STAT_VIP2_MULT_PORTB_SRC5 | INT_STAT_VIP2_MULT_PORTB_SRC4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_VIP2_MULT_ANCB_SRC3 | The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_VIP2_MULT_ANCB_SRC2 | The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_VIP2_MULT_ANCB_SRC1 | The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_VIP2_MULT_ANCB_SRC0 | The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
27 | INT_STAT_VIP2_MULT_ANCA_SRC15 | The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
26 | INT_STAT_VIP2_MULT_ANCA_SRC14 | The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
25 | INT_STAT_VIP2_MULT_ANCA_SRC13 | The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
24 | INT_STAT_VIP2_MULT_ANCA_SRC12 | The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
23 | INT_STAT_VIP2_MULT_ANCA_SRC11 | The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
22 | INT_STAT_VIP2_MULT_ANCA_SRC10 | The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
21 | INT_STAT_VIP2_MULT_ANCA_SRC9 | The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
20 | INT_STAT_VIP2_MULT_ANCA_SRC8 | The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_VIP2_MULT_ANCA_SRC7 | The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_VIP2_MULT_ANCA_SRC6 | The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_VIP2_MULT_ANCA_SRC5 | The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | INT_STAT_VIP2_MULT_ANCA_SRC4 | The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
15 | INT_STAT_VIP2_MULT_ANCA_SRC3 | The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14 | INT_STAT_VIP2_MULT_ANCA_SRC2 | The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
13 | INT_STAT_VIP2_MULT_ANCA_SRC1 | The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
12 | INT_STAT_VIP2_MULT_ANCA_SRC0 | The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11 | INT_STAT_VIP2_MULT_PORTB_SRC15 | The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
10 | INT_STAT_VIP2_MULT_PORTB_SRC14 | The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
9 | INT_STAT_VIP2_MULT_PORTB_SRC13 | The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
8 | INT_STAT_VIP2_MULT_PORTB_SRC12 | The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
7 | INT_STAT_VIP2_MULT_PORTB_SRC11 | The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
6 | INT_STAT_VIP2_MULT_PORTB_SRC10 | The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
5 | INT_STAT_VIP2_MULT_PORTB_SRC9 | The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_VIP2_MULT_PORTB_SRC8 | The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_VIP2_MULT_PORTB_SRC7 | The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_VIP2_MULT_PORTB_SRC6 | The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_VIP2_MULT_PORTB_SRC5 | The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_VIP2_MULT_PORTB_SRC4 | The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x489D D064 | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_VIP2_MULT_ANCB_SRC3 | INT_MASK_VIP2_MULT_ANCB_SRC2 | INT_MASK_VIP2_MULT_ANCB_SRC1 | INT_MASK_VIP2_MULT_ANCB_SRC0 | INT_MASK_VIP2_MULT_ANCA_SRC15 | INT_MASK_VIP2_MULT_ANCA_SRC14 | INT_MASK_VIP2_MULT_ANCA_SRC13 | INT_MASK_VIP2_MULT_ANCA_SRC12 | INT_MASK_VIP2_MULT_ANCA_SRC11 | INT_MASK_VIP2_MULT_ANCA_SRC10 | INT_MASK_VIP2_MULT_ANCA_SRC9 | INT_MASK_VIP2_MULT_ANCA_SRC8 | INT_MASK_VIP2_MULT_ANCA_SRC7 | INT_MASK_VIP2_MULT_ANCA_SRC6 | INT_MASK_VIP2_MULT_ANCA_SRC5 | INT_MASK_VIP2_MULT_ANCA_SRC4 | INT_MASK_VIP2_MULT_ANCA_SRC3 | INT_MASK_VIP2_MULT_ANCA_SRC2 | INT_MASK_VIP2_MULT_ANCA_SRC1 | INT_MASK_VIP2_MULT_ANCA_SRC0 | INT_MASK_VIP2_MULT_PORTB_SRC15 | INT_MASK_VIP2_MULT_PORTB_SRC14 | INT_MASK_VIP2_MULT_PORTB_SRC13 | INT_MASK_VIP2_MULT_PORTB_SRC12 | INT_MASK_VIP2_MULT_PORTB_SRC11 | INT_MASK_VIP2_MULT_PORTB_SRC10 | INT_MASK_VIP2_MULT_PORTB_SRC9 | INT_MASK_VIP2_MULT_PORTB_SRC8 | INT_MASK_VIP2_MULT_PORTB_SRC7 | INT_MASK_VIP2_MULT_PORTB_SRC6 | INT_MASK_VIP2_MULT_PORTB_SRC5 | INT_MASK_VIP2_MULT_PORTB_SRC4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_VIP2_MULT_ANCB_SRC3 | The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_VIP2_MULT_ANCB_SRC2 | The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_VIP2_MULT_ANCB_SRC1 | The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_VIP2_MULT_ANCB_SRC0 | The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27 | INT_MASK_VIP2_MULT_ANCA_SRC15 | The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
26 | INT_MASK_VIP2_MULT_ANCA_SRC14 | The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
25 | INT_MASK_VIP2_MULT_ANCA_SRC13 | The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
24 | INT_MASK_VIP2_MULT_ANCA_SRC12 | The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
23 | INT_MASK_VIP2_MULT_ANCA_SRC11 | The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
22 | INT_MASK_VIP2_MULT_ANCA_SRC10 | The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
21 | INT_MASK_VIP2_MULT_ANCA_SRC9 | The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
20 | INT_MASK_VIP2_MULT_ANCA_SRC8 | The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_VIP2_MULT_ANCA_SRC7 | The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_VIP2_MULT_ANCA_SRC6 | The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_VIP2_MULT_ANCA_SRC5 | The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | INT_MASK_VIP2_MULT_ANCA_SRC4 | The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
15 | INT_MASK_VIP2_MULT_ANCA_SRC3 | The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14 | INT_MASK_VIP2_MULT_ANCA_SRC2 | The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
13 | INT_MASK_VIP2_MULT_ANCA_SRC1 | The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
12 | INT_MASK_VIP2_MULT_ANCA_SRC0 | The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11 | INT_MASK_VIP2_MULT_PORTB_SRC15 | The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
10 | INT_MASK_VIP2_MULT_PORTB_SRC14 | The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
9 | INT_MASK_VIP2_MULT_PORTB_SRC13 | The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
8 | INT_MASK_VIP2_MULT_PORTB_SRC12 | The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
7 | INT_MASK_VIP2_MULT_PORTB_SRC11 | The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
6 | INT_MASK_VIP2_MULT_PORTB_SRC10 | The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
5 | INT_MASK_VIP2_MULT_PORTB_SRC9 | The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_VIP2_MULT_PORTB_SRC8 | The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_VIP2_MULT_PORTB_SRC7 | The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_VIP2_MULT_PORTB_SRC6 | The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_VIP2_MULT_PORTB_SRC5 | The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_VIP2_MULT_PORTB_SRC4 | The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x489D D068 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_TRANSCODE2_CHROMA | INT_STAT_TRANSCODE2_LUMA | INT_STAT_TRANSCODE1_CHROMA | INT_STAT_TRANSCODE1_LUMA | INT_STAT_AUX_IN | INT_STAT_PIP_FRAME | INT_STAT_POST_COMP_WR | INT_STAT_VBI_SD_VENC | RESERVED | INT_STAT_NF_LAST_CHROMA | INT_STAT_NF_LAST_LUMA | INT_STAT_NF_WRITE_CHROMA | INT_STAT_NF_WRITE_LUMA | INT_STAT_OTHER | INT_STAT_VIP2_PORTB_RGB | INT_STAT_VIP2_PORTA_RGB | INT_STAT_VIP2_PORTB_CHROMA | INT_STAT_VIP2_PORTB_LUMA | INT_STAT_VIP2_PORTA_CHROMA | INT_STAT_VIP2_PORTA_LUMA | INT_STAT_VIP2_MULT_ANCB_SRC15 | INT_STAT_VIP2_MULT_ANCB_SRC14 | INT_STAT_VIP2_MULT_ANCB_SRC13 | INT_STAT_VIP2_MULT_ANCB_SRC12 | INT_STAT_VIP2_MULT_ANCB_SRC11 | INT_STAT_VIP2_MULT_ANCB_SRC10 | INT_STAT_VIP2_MULT_ANCB_SRC9 | INT_STAT_VIP2_MULT_ANCB_SRC8 | INT_STAT_VIP2_MULT_ANCB_SRC7 | INT_STAT_VIP2_MULT_ANCB_SRC6 | INT_STAT_VIP2_MULT_ANCB_SRC5 | INT_STAT_VIP2_MULT_ANCB_SRC4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_TRANSCODE2_CHROMA | The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_TRANSCODE2_LUMA | The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_TRANSCODE1_CHROMA | The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_TRANSCODE1_LUMA | The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
27 | INT_STAT_AUX_IN | The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
26 | INT_STAT_PIP_FRAME | The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
25 | INT_STAT_POST_COMP_WR | The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
24 | INT_STAT_VBI_SD_VENC | The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
23 | RESERVED | Reserved | R | 0x0 |
22 | INT_STAT_NF_LAST_CHROMA | The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
21 | INT_STAT_NF_LAST_LUMA | The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
20 | INT_STAT_NF_WRITE_CHROMA | The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_NF_WRITE_LUMA | The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_OTHER | This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_VIP2_PORTB_RGB | The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | INT_STAT_VIP2_PORTA_RGB | The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
15 | INT_STAT_VIP2_PORTB_CHROMA | The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14 | INT_STAT_VIP2_PORTB_LUMA | The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
13 | INT_STAT_VIP2_PORTA_CHROMA | The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
12 | INT_STAT_VIP2_PORTA_LUMA | The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11 | INT_STAT_VIP2_MULT_ANCB_SRC15 | The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
10 | INT_STAT_VIP2_MULT_ANCB_SRC14 | The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
9 | INT_STAT_VIP2_MULT_ANCB_SRC13 | The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
8 | INT_STAT_VIP2_MULT_ANCB_SRC12 | The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
7 | INT_STAT_VIP2_MULT_ANCB_SRC11 | The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
6 | INT_STAT_VIP2_MULT_ANCB_SRC10 | The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
5 | INT_STAT_VIP2_MULT_ANCB_SRC9 | The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_VIP2_MULT_ANCB_SRC8 | The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_VIP2_MULT_ANCB_SRC7 | The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_VIP2_MULT_ANCB_SRC6 | The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_VIP2_MULT_ANCB_SRC5 | The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_VIP2_MULT_ANCB_SRC4 | The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 006C | ||
Physical Address | 0x489D D06C | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_TRANSCODE2_CHROMA | INT_MASK_TRANSCODE2_LUMA | INT_MASK_TRANSCODE1_CHROMA | INT_MASK_TRANSCODE1_LUMA | INT_MASK_AUX_IN | INT_MASK_PIP_FRAME | INT_MASK_POST_COMP_WR | INT_MASK_VBI_SD_VENC | RESERVED | INT_MASK_NF_LAST_CHROMA | INT_MASK_NF_LAST_LUMA | INT_MASK_NF_WRITE_CHROMA | INT_MASK_NF_WRITE_LUMA | INT_MASK_OTHER | INT_MASK_VIP2_PORTB_RGB | INT_MASK_VIP2_PORTA_RGB | INT_MASK_VIP2_PORTB_CHROMA | INT_MASK_VIP2_PORTB_LUMA | INT_MASK_VIP2_PORTA_CHROMA | INT_MASK_VIP2_PORTA_LUMA | INT_MASK_VIP2_MULT_ANCB_SRC15 | INT_MASK_VIP2_MULT_ANCB_SRC14 | INT_MASK_VIP2_MULT_ANCB_SRC13 | INT_MASK_VIP2_MULT_ANCB_SRC12 | INT_MASK_VIP2_MULT_ANCB_SRC11 | INT_MASK_VIP2_MULT_ANCB_SRC10 | INT_MASK_VIP2_MULT_ANCB_SRC9 | INT_MASK_VIP2_MULT_ANCB_SRC8 | INT_MASK_VIP2_MULT_ANCB_SRC7 | INT_MASK_VIP2_MULT_ANCB_SRC6 | INT_MASK_VIP2_MULT_ANCB_SRC5 | INT_MASK_VIP2_MULT_ANCB_SRC4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_TRANSCODE2_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_TRANSCODE2_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_TRANSCODE1_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_TRANSCODE1_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27 | INT_MASK_AUX_IN | The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
26 | INT_MASK_PIP_FRAME | The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
25 | INT_MASK_POST_COMP_WR | The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
24 | INT_MASK_VBI_SD_VENC | The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
23 | RESERVED | Reserved | R | 0x0 |
22 | INT_MASK_NF_LAST_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
21 | INT_MASK_NF_LAST_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
20 | INT_MASK_NF_WRITE_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_NF_WRITE_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_OTHER | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_VIP2_PORTB_RGB | The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | INT_MASK_VIP2_PORTA_RGB | The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
15 | INT_MASK_VIP2_PORTB_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14 | INT_MASK_VIP2_PORTB_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
13 | INT_MASK_VIP2_PORTA_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
12 | INT_MASK_VIP2_PORTA_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11 | INT_MASK_VIP2_MULT_ANCB_SRC15 | The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
10 | INT_MASK_VIP2_MULT_ANCB_SRC14 | The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
9 | INT_MASK_VIP2_MULT_ANCB_SRC13 | The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
8 | INT_MASK_VIP2_MULT_ANCB_SRC12 | The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
7 | INT_MASK_VIP2_MULT_ANCB_SRC11 | The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
6 | INT_MASK_VIP2_MULT_ANCB_SRC10 | The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
5 | INT_MASK_VIP2_MULT_ANCB_SRC9 | The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_VIP2_MULT_ANCB_SRC8 | The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_VIP2_MULT_ANCB_SRC7 | The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_VIP2_MULT_ANCB_SRC6 | The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_VIP2_MULT_ANCB_SRC5 | The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_VIP2_MULT_ANCB_SRC4 | The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x489D D078 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_GRPX1_DATA | INT_STAT_COMP_WRBK | INT_STAT_SC_OUT | RESERVED | INT_STAT_SC_IN_LUMA | INT_STAT_SC_IN_CHROMA | INT_STAT_PIP_WRBK | INT_STAT_DEI_SC_OUT | RESERVED | INT_STAT_DEI_HQ_MV_OUT | RESERVED | INT_STAT_DEI_HQ_MV_IN | RESERVED | INT_STAT_DEI_HQ_3_CHROMA | INT_STAT_DEI_HQ_3_LUMA | INT_STAT_DEI_HQ_2_CHROMA | INT_STAT_DEI_HQ_2_LUMA | INT_STAT_DEI_HQ_1_LUMA | INT_STAT_DEI_HQ_1_CHROMA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_GRPX1_DATA | The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_COMP_WRBK | The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_SC_OUT | The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28:21 | RESERVED | Reserved | R | 0x00 |
20 | INT_STAT_SC_IN_LUMA | The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_SC_IN_CHROMA | The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_PIP_WRBK | The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_DEI_SC_OUT | The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | RESERVED | Reserved | R | 0x0 |
15 | INT_STAT_DEI_HQ_MV_OUT | The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14:13 | RESERVED | Reserved | R | 0x0 |
12 | INT_STAT_DEI_HQ_MV_IN | The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11:6 | RESERVED | Reserved | R | 0x00 |
5 | INT_STAT_DEI_HQ_3_CHROMA | The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_DEI_HQ_3_LUMA | The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_DEI_HQ_2_CHROMA | The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_DEI_HQ_2_LUMA | The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_DEI_HQ_1_LUMA | The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_DEI_HQ_1_CHROMA | The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 007C | ||
Physical Address | 0x489D D07C | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_GRPX1_DATA | INT_MASK_COMP_WRBK | INT_MASK_SC_OUT | RESERVED | INT_MASK_SC_IN_LUMA | INT_MASK_SC_IN_CHROMA | INT_MASK_PIP_WRBK | INT_MASK_DEI_SC_OUT | RESERVED | INT_MASK_DEI_HQ_MV_OUT | RESERVED | INT_MASK_DEI_HQ_MV_IN | RESERVED | INT_MASK_DEI_HQ_3_CHROMA | INT_MASK_DEI_HQ_3_LUMA | INT_MASK_DEI_HQ_2_CHROMA | INT_MASK_DEI_HQ_2_LUMA | INT_MASK_DEI_HQ_1_LUMA | INT_MASK_DEI_HQ_1_CHROMA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_GRPX1_DATA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_COMP_WRBK | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_SC_OUT | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28:21 | RESERVED | Reserved | R | 0x00 |
20 | INT_MASK_SC_IN_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_SC_IN_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_PIP_WRBK | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_DEI_SC_OUT | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | RESERVED | Reserved | R | 0x0 |
15 | INT_MASK_DEI_HQ_MV_OUT | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14:13 | RESERVED | Reserved | R | 0x0 |
12 | INT_MASK_DEI_HQ_MV_IN | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11:6 | RESERVED | Reserved | R | 0x00 |
5 | INT_MASK_DEI_HQ_3_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_DEI_HQ_3_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_DEI_HQ_2_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_DEI_HQ_2_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_DEI_HQ_1_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_DEI_HQ_1_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x489D D080 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | INT_STAT_VIP2_ANC_B | INT_STAT_VIP2_ANC_A | INT_STAT_VIP1_ANC_B | INT_STAT_VIP1_ANC_A | INT_STAT_TRANS2_LUMA | INT_STAT_TRANS2_CHROMA | INT_STAT_TRANS1_LUMA | INT_STAT_TRANS1_CHROMA | INT_STAT_HDMI_WRBK_OUT | INT_STAT_VPI_CTL | INT_STAT_VBI_SDVENC | RESERVED | INT_STAT_NF_420_UV_OUT | INT_STAT_NF_420_Y_OUT | INT_STAT_NF_420_UV_IN | INT_STAT_NF_420_Y_IN | INT_STAT_NF_422_IN | INT_STAT_GRPX3_ST | INT_STAT_GRPX2_ST | INT_STAT_GRPX1_ST | INT_STAT_VIP2_UP_UV | INT_STAT_VIP2_UP_Y | INT_STAT_VIP2_LO_UV | INT_STAT_VIP2_LO_Y | INT_STAT_VIP1_UP_UV | INT_STAT_VIP1_UP_Y | INT_STAT_VIP1_LO_UV | INT_STAT_VIP1_LO_Y | INT_STAT_GRPX3_DATA | INT_STAT_GRPX2_DATA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | Reserved | R | 0 |
30 | RESERVED | Reserved | R | 0 |
29 | INT_STAT_VIP2_ANC_B | The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
28 | INT_STAT_VIP2_ANC_A | The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
27 | INT_STAT_VIP1_ANC_B | The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
26 | INT_STAT_VIP1_ANC_A | The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
25 | INT_STAT_TRANS2_LUMA | The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
24 | INT_STAT_TRANS2_CHROMA | The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
23 | INT_STAT_TRANS1_LUMA | The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
22 | INT_STAT_TRANS1_CHROMA | The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
21 | INT_STAT_HDMI_WRBK_OUT | The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
20 | INT_STAT_VPI_CTL | The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
19 | INT_STAT_VBI_SDVENC | The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
18 | RESERVED | Reserved | R | 0 |
17 | INT_STAT_NF_420_UV_OUT | The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
16 | INT_STAT_NF_420_Y_OUT | The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
15 | INT_STAT_NF_420_UV_IN | The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
14 | INT_STAT_NF_420_Y_IN | The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
13 | INT_STAT_NF_422_IN | The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
12 | INT_STAT_GRPX3_ST | The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
11 | INT_STAT_GRPX2_ST | The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
10 | INT_STAT_GRPX1_ST | The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
9 | INT_STAT_VIP2_UP_UV | The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
8 | INT_STAT_VIP2_UP_Y | The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
7 | INT_STAT_VIP2_LO_UV | The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
6 | INT_STAT_VIP2_LO_Y | The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
5 | INT_STAT_VIP1_UP_UV | The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
4 | INT_STAT_VIP1_UP_Y | The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
3 | INT_STAT_VIP1_LO_UV | The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
2 | INT_STAT_VIP1_LO_Y | The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
1 | INT_STAT_GRPX3_DATA | The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
0 | INT_STAT_GRPX2_DATA | The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW W0toClr | 0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x489D D084 | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | INT_MASK_VIP2_ANC_B | INT_MASK_VIP2_ANC_A | INT_MASK_VIP1_ANC_B | INT_MASK_VIP1_ANC_A | INT_MASK_TRANS2_LUMA | INT_MASK_TRANS2_CHROMA | INT_MASK_TRANS1_LUMA | INT_MASK_TRANS1_CHROMA | INT_MASK_HDMI_WRBK_OUT | INT_MASK_VPI_CTL | INT_MASK_VBI_SDVENC | RESERVED | INT_MASK_NF_420_UV_OUT | INT_MASK_NF_420_Y_OUT | INT_MASK_NF_420_UV_IN | INT_MASK_NF_420_Y_IN | INT_MASK_NF_422_IN | INT_MASK_GRPX3_ST | INT_MASK_GRPX2_ST | INT_MASK_GRPX1_ST | INT_MASK_VIP2_UP_UV | INT_MASK_VIP2_UP_Y | INT_MASK_VIP2_LO_UV | INT_MASK_VIP2_LO_Y | INT_MASK_VIP1_UP_UV | INT_MASK_VIP1_UP_Y | INT_MASK_VIP1_LO_UV | INT_MASK_VIP1_LO_Y | INT_MASK_GRPX3_DATA | INT_MASK_GRPX2_DATA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | Reserved | R | 0 |
30 | RESERVED | Reserved | R | 0 |
29 | INT_MASK_VIP2_ANC_B | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
28 | INT_MASK_VIP2_ANC_A | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
27 | INT_MASK_VIP1_ANC_B | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
26 | INT_MASK_VIP1_ANC_A | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
25 | INT_MASK_TRANS2_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
24 | INT_MASK_TRANS2_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
23 | INT_MASK_TRANS1_LUMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
22 | INT_MASK_TRANS1_CHROMA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
21 | INT_MASK_HDMI_WRBK_OUT | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
20 | INT_MASK_VPI_CTL | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
19 | INT_MASK_VBI_SDVENC | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
18 | RESERVED | Reserved | R | 0 |
17 | INT_MASK_NF_420_UV_OUT | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
16 | INT_MASK_NF_420_Y_OUT | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
15 | INT_MASK_NF_420_UV_IN | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
14 | INT_MASK_NF_420_Y_IN | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
13 | INT_MASK_NF_422_IN | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
12 | INT_MASK_GRPX3_ST | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
11 | INT_MASK_GRPX2_ST | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
10 | INT_MASK_GRPX1_ST | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
9 | INT_MASK_VIP2_UP_UV | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
8 | INT_MASK_VIP2_UP_Y | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
7 | INT_MASK_VIP2_LO_UV | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
6 | INT_MASK_VIP2_LO_Y | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
5 | INT_MASK_VIP1_UP_UV | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
4 | INT_MASK_VIP1_UP_Y | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
3 | INT_MASK_VIP1_LO_UV | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
2 | INT_MASK_VIP1_LO_Y | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
1 | INT_MASK_GRPX3_DATA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
0 | INT_MASK_GRPX2_DATA | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x489D D088 | Instance | VPE_VPDMA |
Description | This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_STAT_CONTROL_DESCRIPTOR_INT15 | INT_STAT_CONTROL_DESCRIPTOR_INT14 | INT_STAT_CONTROL_DESCRIPTOR_INT13 | INT_STAT_CONTROL_DESCRIPTOR_INT12 | INT_STAT_CONTROL_DESCRIPTOR_INT11 | INT_STAT_CONTROL_DESCRIPTOR_INT10 | INT_STAT_CONTROL_DESCRIPTOR_INT9 | INT_STAT_CONTROL_DESCRIPTOR_INT8 | INT_STAT_CONTROL_DESCRIPTOR_INT7 | INT_STAT_CONTROL_DESCRIPTOR_INT6 | INT_STAT_CONTROL_DESCRIPTOR_INT5 | INT_STAT_CONTROL_DESCRIPTOR_INT4 | INT_STAT_CONTROL_DESCRIPTOR_INT3 | INT_STAT_CONTROL_DESCRIPTOR_INT2 | INT_STAT_CONTROL_DESCRIPTOR_INT1 | INT_STAT_CONTROL_DESCRIPTOR_INT0 | INT_STAT_LIST7_NOTIFY | INT_STAT_LIST7_COMPLETE | INT_STAT_LIST6_NOTIFY | INT_STAT_LIST6_COMPLETE | INT_STAT_LIST5_NOTIFY | INT_STAT_LIST5_COMPLETE | INT_STAT_LIST4_NOTIFY | INT_STAT_LIST4_COMPLETE | INT_STAT_LIST3_NOTIFY | INT_STAT_LIST3_COMPLETE | INT_STAT_LIST2_NOTIFY | INT_STAT_LIST2_COMPLETE | INT_STAT_LIST1_NOTIFY | INT_STAT_LIST1_COMPLETE | INT_STAT_LIST0_NOTIFY | INT_STAT_LIST0_COMPLETE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_STAT_CONTROL_DESCRIPTOR_INT15 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
30 | INT_STAT_CONTROL_DESCRIPTOR_INT14 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
29 | INT_STAT_CONTROL_DESCRIPTOR_INT13 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
28 | INT_STAT_CONTROL_DESCRIPTOR_INT12 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
27 | INT_STAT_CONTROL_DESCRIPTOR_INT11 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
26 | INT_STAT_CONTROL_DESCRIPTOR_INT10 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
25 | INT_STAT_CONTROL_DESCRIPTOR_INT9 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
24 | INT_STAT_CONTROL_DESCRIPTOR_INT8 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
23 | INT_STAT_CONTROL_DESCRIPTOR_INT7 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
22 | INT_STAT_CONTROL_DESCRIPTOR_INT6 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
21 | INT_STAT_CONTROL_DESCRIPTOR_INT5 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
20 | INT_STAT_CONTROL_DESCRIPTOR_INT4 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
19 | INT_STAT_CONTROL_DESCRIPTOR_INT3 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
18 | INT_STAT_CONTROL_DESCRIPTOR_INT2 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
17 | INT_STAT_CONTROL_DESCRIPTOR_INT1 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
16 | INT_STAT_CONTROL_DESCRIPTOR_INT0 | A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
15 | INT_STAT_LIST7_NOTIFY | A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
14 | INT_STAT_LIST7_COMPLETE | List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
13 | INT_STAT_LIST6_NOTIFY | A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
12 | INT_STAT_LIST6_COMPLETE | List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
11 | INT_STAT_LIST5_NOTIFY | A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
10 | INT_STAT_LIST5_COMPLETE | List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
9 | INT_STAT_LIST4_NOTIFY | A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
8 | INT_STAT_LIST4_COMPLETE | List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
7 | INT_STAT_LIST3_NOTIFY | A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
6 | INT_STAT_LIST3_COMPLETE | List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
5 | INT_STAT_LIST2_NOTIFY | A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
4 | INT_STAT_LIST2_COMPLETE | List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
3 | INT_STAT_LIST1_NOTIFY | A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
2 | INT_STAT_LIST1_COMPLETE | List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
1 | INT_STAT_LIST0_NOTIFY | A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
0 | INT_STAT_LIST0_COMPLETE | List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 008C | ||
Physical Address | 0x489D D08C | Instance | VPE_VPDMA |
Description | The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_MASK_CONTROL_DESCRIPTOR_INT15 | INT_MASK_CONTROL_DESCRIPTOR_INT14 | INT_MASK_CONTROL_DESCRIPTOR_INT13 | INT_MASK_CONTROL_DESCRIPTOR_INT12 | INT_MASK_CONTROL_DESCRIPTOR_INT11 | INT_MASK_CONTROL_DESCRIPTOR_INT10 | INT_MASK_CONTROL_DESCRIPTOR_INT9 | INT_MASK_CONTROL_DESCRIPTOR_INT8 | INT_MASK_CONTROL_DESCRIPTOR_INT7 | INT_MASK_CONTROL_DESCRIPTOR_INT6 | INT_MASK_CONTROL_DESCRIPTOR_INT5 | INT_MASK_CONTROL_DESCRIPTOR_INT4 | INT_MASK_CONTROL_DESCRIPTOR_INT3 | INT_MASK_CONTROL_DESCRIPTOR_INT2 | INT_MASK_CONTROL_DESCRIPTOR_INT1 | INT_MASK_CONTROL_DESCRIPTOR_INT0 | INT_MASK_LIST7_NOTIFY | INT_MASK_LIST7_COMPLETE | INT_MASK_LIST6_NOTIFY | INT_MASK_LIST6_COMPLETE | INT_MASK_LIST5_NOTIFY | INT_MASK_LIST5_COMPLETE | INT_MASK_LIST4_NOTIFY | INT_MASK_LIST4_COMPLETE | INT_MASK_LIST3_NOTIFY | INT_MASK_LIST3_COMPLETE | INT_MASK_LIST2_NOTIFY | INT_MASK_LIST2_COMPLETE | INT_MASK_LIST1_NOTIFY | INT_MASK_LIST1_COMPLETE | INT_MASK_LIST0_NOTIFY | INT_MASK_LIST0_COMPLETE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | INT_MASK_CONTROL_DESCRIPTOR_INT15 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
30 | INT_MASK_CONTROL_DESCRIPTOR_INT14 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
29 | INT_MASK_CONTROL_DESCRIPTOR_INT13 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
28 | INT_MASK_CONTROL_DESCRIPTOR_INT12 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
27 | INT_MASK_CONTROL_DESCRIPTOR_INT11 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
26 | INT_MASK_CONTROL_DESCRIPTOR_INT10 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
25 | INT_MASK_CONTROL_DESCRIPTOR_INT9 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
24 | INT_MASK_CONTROL_DESCRIPTOR_INT8 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
23 | INT_MASK_CONTROL_DESCRIPTOR_INT7 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
22 | INT_MASK_CONTROL_DESCRIPTOR_INT6 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
21 | INT_MASK_CONTROL_DESCRIPTOR_INT5 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
20 | INT_MASK_CONTROL_DESCRIPTOR_INT4 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
19 | INT_MASK_CONTROL_DESCRIPTOR_INT3 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
18 | INT_MASK_CONTROL_DESCRIPTOR_INT2 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
17 | INT_MASK_CONTROL_DESCRIPTOR_INT1 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
16 | INT_MASK_CONTROL_DESCRIPTOR_INT0 | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
15 | INT_MASK_LIST7_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
14 | INT_MASK_LIST7_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
13 | INT_MASK_LIST6_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
12 | INT_MASK_LIST6_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
11 | INT_MASK_LIST5_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
10 | INT_MASK_LIST5_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
9 | INT_MASK_LIST4_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
8 | INT_MASK_LIST4_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
7 | INT_MASK_LIST3_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
6 | INT_MASK_LIST3_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
5 | INT_MASK_LIST2_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
4 | INT_MASK_LIST2_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
3 | INT_MASK_LIST1_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
2 | INT_MASK_LIST1_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
1 | INT_MASK_LIST0_NOTIFY | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
0 | INT_MASK_LIST0_COMPLETE | The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. | RW | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x489D D200 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_1_chroma | ||||
0x1 : vpi_ctl | ||||
0x2: dei_hq_1_luma | ||||
0x3: dei_hq_2_luma | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_1_chroma | ||||
0x1 : vpi_ctl | ||||
0x2: dei_hq_1_luma | ||||
0x3: dei_hq_2_luma | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x489D D204 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_1_luma | ||||
0x1 : dei_hq_1_chroma | ||||
0x2: dei_hq_2_luma | ||||
0x3: dei_hq_2_chroma | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_1_luma | ||||
0x1 : dei_hq_1_chroma | ||||
0x2: dei_hq_2_luma | ||||
0x3: dei_hq_2_chroma | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0208 | ||
Physical Address | 0x489D D208 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_2_luma | ||||
0x1 : dei_hq_1_luma | ||||
0x2: dei_hq_2_chroma | ||||
0x3: dei_hq_3_luma | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_2_luma | ||||
0x1 : dei_hq_1_luma | ||||
0x2: dei_hq_2_chroma | ||||
0x3: dei_hq_3_luma | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 020C | ||
Physical Address | 0x489D D20C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_2_luma | ||||
0x1 : dei_hq_1_luma | ||||
0x2: dei_hq_2_chroma | ||||
0x3: dei_hq_3_luma | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_2_luma | ||||
0x1 : dei_hq_1_luma | ||||
0x2: dei_hq_2_chroma | ||||
0x3: dei_hq_3_luma | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x489D D210 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_3_luma | ||||
0x1 : dei_hq_2_chroma | ||||
0x 2: dei_hq_3_chroma | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_3_luma | ||||
0x1 : dei_hq_2_chroma | ||||
0x 2: dei_hq_3_chroma | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x489D D214 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_3_luma | ||||
0x1 : dei_hq_2_chroma | ||||
0x 2: dei_hq_3_chroma | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_3_luma | ||||
0x1 : dei_hq_2_chroma | ||||
0x 2: dei_hq_3_chroma | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x489D D218 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : dei_hq_3_chroma | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_3_chroma | ||||
0x1 : dei_hq_3_chroma | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 021C | ||
Physical Address | 0x489D D21C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0220 | ||
Physical Address | 0x489D D220 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0224 | ||
Physical Address | 0x489D D224 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0228 | ||
Physical Address | 0x489D D228 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: dei_hq_mv_in | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: dei_hq_mv_in | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 022C | ||
Physical Address | 0x489D D22C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: dei_hq_mv_in | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: dei_hq_mv_in | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0230 | ||
Physical Address | 0x489D D230 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_mv_in | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_mv_in | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0234 | ||
Physical Address | 0x489D D234 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : dei_hq_mv_in | ||||
0x2: | ||||
0x3:dei_hq_mv_out | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : dei_hq_mv_in | ||||
0x2: | ||||
0x3:dei_hq_mv_out | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0238 | ||
Physical Address | 0x489D D238 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: dei_hq_mv_out | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: dei_hq_mv_out | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 023C | ||
Physical Address | 0x489D D23C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_mv_out | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : dei_hq_mv_out | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0240 | ||
Physical Address | 0x489D D240 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : dei_hq_mv_out | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : dei_hq_mv_out | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0244 | ||
Physical Address | 0x489D D244 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0248 | ||
Physical Address | 0x489D D248 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 024C | ||
Physical Address | 0x489D D24C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0250 | ||
Physical Address | 0x489D D250 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0254 | ||
Physical Address | 0x489D D254 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0258 | ||
Physical Address | 0x489D D258 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 025C | ||
Physical Address | 0x489D D25C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0260 | ||
Physical Address | 0x489D D260 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0264 | ||
Physical Address | 0x489D D264 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0268 | ||
Physical Address | 0x489D D268 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 026C | ||
Physical Address | 0x489D D26C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0270 | ||
Physical Address | 0x489D D270 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0274 | ||
Physical Address | 0x489D D274 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0278 | ||
Physical Address | 0x489D D278 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 027C | ||
Physical Address | 0x489D D27C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0280 | ||
Physical Address | 0x489D D280 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0284 | ||
Physical Address | 0x489D D284 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0288 | ||
Physical Address | 0x489D D288 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: vip1_up_y | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: | ||||
0x3: vip1_up_y | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0x0 : command request | ||||
0x1 : command accept | ||||
0x2: data request | ||||
0x3: data rcvd | ||||
0x4: data empty | ||||
0x5: data full | ||||
0x6: frame start | ||||
0x7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 028C | ||
Physical Address | 0x489D D28C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: vip1_up_y | ||||
0x3: vip1_up_uv | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : | ||||
0x1 : | ||||
0x2: vip1_up_y | ||||
0x3: vip1_up_uv | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0290 | ||
Physical Address | 0x489D D290 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : vip1_up_uv | ||||
0x1 : vip1_up_y | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : vip1_up_uv | ||||
0x1 : vip1_up_y | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0294 | ||
Physical Address | 0x489D D294 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : vip1_up_uv | ||||
0x1 : vip1_up_y | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : vip1_up_uv | ||||
0x1 : vip1_up_y | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0298 | ||
Physical Address | 0x489D D298 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0x0 : Running Average | ||||
0x1 : Minimum Value | ||||
0x2: Maximum Value | ||||
0x3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0x0 : vip1_up_uv | ||||
0x1 : vip1_up_y | ||||
0x2: | ||||
0x3: | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0x0 : vip1_up_uv | ||||
0x1 : vip1_up_y | ||||
0x2: | ||||
0x3: | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 029C | ||
Physical Address | 0x489D D29C | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02A0 | ||
Physical Address | 0x489D D2A0 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02A4 | ||
Physical Address | 0x489D D2A4 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02A8 | ||
Physical Address | 0x489D D2A8 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02AC | ||
Physical Address | 0x489D D2AC | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02B0 | ||
Physical Address | 0x489D D2B0 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02B4 | ||
Physical Address | 0x489D D2B4 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02B8 | ||
Physical Address | 0x489D D2B8 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02BC | ||
Physical Address | 0x489D D2BC | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02C0 | ||
Physical Address | 0x489D D2C0 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02C4 | ||
Physical Address | 0x489D D2C4 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02C8 | ||
Physical Address | 0x489D D2C8 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0:vpi_ctl | ||||
1:vpi_ctl | ||||
2:vpi_ctl | ||||
3:vpi_ctl | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0:vpi_ctl | ||||
1:vpi_ctl | ||||
2:vpi_ctl | ||||
3:vpi_ctl | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02CC | ||
Physical Address | 0x489D D2CC | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0: vpi_ctl | ||||
1: dei_hq_1_chroma | ||||
2: dei_hq_1_chroma | ||||
3: dei_hq_1_luma | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0: vpi_ctl | ||||
1: dei_hq_1_chroma | ||||
2: dei_hq_1_chroma | ||||
3: dei_hq_1_luma | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 02D0 | ||
Physical Address | 0x489D D2D0 | Instance | VPE_VPDMA |
Description | The register can be used to capture timing differences between events in the VPDMA | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_MODE | STOP_CLIENT | RESERVED | STOP_COUNT | RESERVED | START_CLIENT | RESERVED | START_COUNT | CURR_COUNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | CAPTURE_MODE | Sets how the counter should be updated. Updating this value will also clear the current counter stored value. | RW | 0x0 |
0: Running Average | ||||
1: Minimum Value | ||||
2: Maximum Value | ||||
3: Last Value | ||||
29:28 | STOP_CLIENT | Sets the client whose event stops the performance monitor counter. | RW | 0x0 |
0: vpi_ctl | ||||
1: dei_hq_1_chroma | ||||
2: dei_hq_1_chroma | ||||
3: dei_hq_1_luma | ||||
27 | RESERVED | R | 0x0 | |
26:24 | STOP_COUNT | Sets the value that stops the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
23:22 | RESERVED | R | 0x0 | |
21:20 | START_CLIENT | Sets the client whose event starts the performance monitor counter. | RW | 0x0 |
0: vpi_ctl | ||||
1: dei_hq_1_chroma | ||||
2: dei_hq_1_chroma | ||||
3: dei_hq_1_luma | ||||
19 | RESERVED | R | 0x0 | |
18:16 | START_COUNT | Sets the value that starts the performance monitor counter. | RW | 0x0 |
0: command request | ||||
1: command accept | ||||
2: data request | ||||
3: data rcvd | ||||
4: data empty | ||||
5: data full | ||||
6: frame start | ||||
7: frame end | ||||
15:0 | CURR_COUNT | The current value of the perfomance monitor counter | R | 0x0 |
VPE Register Manual |
Address Offset | 0x0000 0300 | ||
Physical Address | 0x489D D300 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | LINE_MODE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:8 | LINE_MODE | Selects the output mode of the line buffer. | RW | 0x0 |
0: repeat lines twice each output data line gets 2 times the number of frame lines. | ||||
1: each line once with Line Buffer Disabled, so no mirroring. Each line gets frame lines with identical data. | ||||
2: Each line seen once Mirroring is enabled so the top lines get the top lines repeated at the top of the frame and the bottom lines have the bottom lines repeated. Each line of data gets frame lines + number of buffered lines. | ||||
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. | ||||
7:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0304 | ||
Physical Address | 0x489D D304 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0308 | ||
Physical Address | 0x489D D308 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 030C | ||
Physical Address | 0x489D D30C | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | LINE_MODE | 3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:8 | LINE_MODE | Selects the output mode of the line buffer. | RW | 0x0 |
0: repeat lines twice each output data line gets 2 times the number of frame lines. | ||||
1: each line once with Line Buffer Disabled, so no mirroring. Each line gets frame lines with identical data. | ||||
2: Each line seen once Mirroring is enabled so the top lines get the top lines repeated at the top of the frame and the bottom lines have the bottom lines repeated. Each line of data gets frame lines + number of buffered lines. | ||||
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. | ||||
7:0 | 3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0310 | ||
Physical Address | 0x489D D310 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0314 | ||
Physical Address | 0x489D D314 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | LINE_MODE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:8 | LINE_MODE | Selects the output mode of the line buffer. | RW | 0x0 |
0: repeat lines twice each output data line gets 2 times the number of frame lines. | ||||
1: each line once with Line Buffer Disabled, so no mirroring. Each line gets frame lines with identical data. | ||||
2: Each line seen once Mirroring is enabled so the top lines get the top lines repeated at the top of the frame and the bottom lines have the bottom lines repeated. Each line of data gets frame lines + number of buffered lines. | ||||
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. | ||||
7:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0330 | ||
Physical Address | 0x489D D330 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 033C | ||
Physical Address | 0x489D D33C | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0390 | ||
Physical Address | 0x489D D390 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 0394 | ||
Physical Address | 0x489D D394 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |
Address Offset | 0x0000 03D0 | ||
Physical Address | 0x489D D3D0 | Instance | VPE_VPDMA |
Description | The register holds status information and control for the client. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REQ_DELAY | REQ_RATE | BUSY | DMA_ACTIVE | FRAME_START | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | REQ_DELAY | The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible. | RW | 0x0 |
23:16 | REQ_RATE | The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins. | R | 0x0 |
15 | BUSY | Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory. | R | 0x0 |
14 | DMA_ACTIVE | Signals if the client is currently actively sending DMA requests | R | 0x0 |
13:10 | FRAME_START | The source of the start frame event for the client. | RW | 0x0 |
0 : Change in value of hdmi_field_id | ||||
1 : Change in value of dvo2_field_id | ||||
2 : Change in value of hdcomp_field_id | ||||
3 : Change in value of sd_field_id | ||||
4 : Use List Manager Internal Field0 | ||||
5 : Use List Manager Internal Field1 | ||||
6 : Use List Manager Internal Field2 | ||||
7 : Start on channel active | ||||
9:0 | RESERVED | R | 0x0 |
VPE Functional Description |
VPE Register Manual |