SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Register Name | Type | Register Width (Bits) | Address Offset | CM_CORE__L3INIT Physical Address L4_CFG Interconnect |
---|---|---|---|---|
CM_L3INIT_CLKSTCTRL | RW | 32 | 0x0000 0000 | 0x4A00 9300 |
CM_L3INIT_STATICDEP | RW | 32 | 0x0000 0004 | 0x4A00 9304 |
CM_L3INIT_DYNAMICDEP | R | 32 | 0x0000 0008 | 0x4A00 9308 |
CM_L3INIT_MMC1_CLKCTRL | RW | 32 | 0x0000 0028 | 0x4A00 9328 |
CM_L3INIT_MMC2_CLKCTRL | RW | 32 | 0x0000 0030 | 0x4A00 9330 |
CM_L3INIT_USB_OTG_SS2_CLKCTRL | RW | 32 | 0x0000 0040 | 0x4A00 9340 |
CM_L3INIT_USB_OTG_SS3_CLKCTRL | RW | 32 | 0x0000 0048 | 0x4A00 9348 |
CM_L3INIT_USB_OTG_SS4_CLKCTRL | RW | 32 | 0x0000 0050 | 0x4A00 9350 |
CM_L3INIT_MLB_SS_CLKCTRL | RW | 32 | 0x0000 0058 | 0x4A00 9358 |
CM_L3INIT_IEEE1500_2_OCP_CLKCTRL | R | 32 | 0x0000 0078 | 0x4A00 9378 |
CM_L3INIT_SATA_CLKCTRL | RW | 32 | 0x0000 0088 | 0x4A00 9388 |
CM_PCIE_CLKSTCTRL | RW | 32 | 0x0000 00A0 | 0x4A00 93A0 |
CM_PCIE_STATICDEP | RW | 32 | 0x0000 00A4 | 0x4A00 93A4 |
CM_PCIE_PCIESS1_CLKCTRL | RW | 32 | 0x0000 00B0 | 0x4A00 93B0 |
CM_PCIE_PCIESS2_CLKCTRL | RW | 32 | 0x0000 00B8 | 0x4A00 93B8 |
CM_GMAC_CLKSTCTRL | RW | 32 | 0x0000 00C0 | 0x4A00 93C0 |
CM_GMAC_STATICDEP | RW | 32 | 0x0000 00C4 | 0x4A00 93C4 |
CM_GMAC_DYNAMICDEP | R | 32 | 0x0000 00C8 | 0x4A00 93C8 |
CM_GMAC_GMAC_CLKCTRL | RW | 32 | 0x0000 00D0 | 0x4A00 93D0 |
CM_L3INIT_OCP2SCP1_CLKCTRL | RW | 32 | 0x0000 00E0 | 0x4A00 93E0 |
CM_L3INIT_OCP2SCP3_CLKCTRL | RW | 32 | 0x0000 00E8 | 0x4A00 93E8 |
CM_L3INIT_USB_OTG_SS1_CLKCTRL | RW | 32 | 0x0000 00F0 | 0x4A00 93F0 |