31-14 | Reserved | 0 | Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. |
13 | DBZ | 0-1 | Divide-By-Zero. Status indicating if a Divide-By-Zero condition occurred since last time it was cleared. Once set, software MUST clear this bit. It is set only if the DBZE bit is set. |
12 | DBZE | 0-1 | Divide-By-Zero exception enable. When set to 1, CPU takes an UNDEF interrupt when a divide-by-zero condition is detected by DIV, DIVU, MOD, or MODU instructions. By default this bit is disabled. |
11-8 | INUM | | Interrupt Number. Indicates the interrupt ID of the last taken interrupt. |
| 0 | Reset |
| 1h | NMI |
| 2h | SWI |
| 3h | UNDEF |
| 4h | INT4 |
| 5h | INT5 |
| 6h | INT6 |
| 7h | INT7 |
| 8h | INT8 |
| 9h | INT9 |
| Ah | INT10 |
| Bh | INT11 |
| Ch | INT12 |
| Dh | INT13 |
| Eh | INT14 |
| Fh | INT15 |
7 | V | 0-1 | Overflow bit. Arithmetic operations that results in overflow or borrow set this bit. See individual instruction descriptions for instructions that modify the V bit. |
6 | SAT | 0-1 | Saturation bit. Arithmetic operations whose results have been saturated set this bit. See individual instruction descriptions for instructions that modify the SAT bit. |
5 | C | 0-1 | Carry bit. Arithmetic operations that results in carry out or borrow set this bit. See individual instruction descriptions for instructions that modify the C bit. |
4 | GT | 0-1 | Greater-than bit. This bit is set or cleared based on the result of a CMP instruction. (GT = 1 if Rx > Ry; else GT = 0). See individual instruction descriptions for instructions that modify the GT bit. |
3 | LT | 0-1 | Less-than bit. This bit is set or cleared based on the result of a CMP instruction. (LT = 1 if Rx < Ry; else LT = 0). See individual instruction descriptions for instructions that modify the LT bit. |
2 | EQ | 0-1 | Equal bit. This bit is set to 1 if the result of an instruction execution results in a zero result or the result of a CMP instruction returns equality (EQ = 1 if Rx == Ry; else EQ = 0). See individual instruction descriptions for instructions that modify the EQ bit. |
1 | Reserved | 0 | Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. |
0 | GIE | | Global interrupt enable. |
| 0 | Disables all interrupts, except the reset interrupt and NMI (nonmaskable interrupt). |
| 1 | Enables all interrupts. |