SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The watchdog timer is based on an upward 32-bit counter coupled with a prescaler. The counter overflow is signaled through two independent signals: a simple reset signal and an interrupt signal, both active low. The use of these signals depends on whether they are connected or not. For this information, see Figure 24-18. The interrupt generation mechanism is controlled through the WIRQENSET/WIRQENCLR and WIRQSTAT registers.
The prescaler ratio can be set from 1 to 128 by accessing the WCLR[4:2] PTV bit field and the WCLR[5] PRE bit of the watchdog control register (WCLR).
The current timer value can be accessed on-the-fly by reading the watchdog timer counter register (WCRR), modified by accessing the watchdog timer load register (WLDR) (no on-the-fly update), or reloaded by following a specific reload sequence on the watchdog timer trigger register (WTGR). A start/stop sequence applied to the watchdog timer start/stop register (WSPR) can start and stop the watchdog timers.
Figure 24-20 is a functional block diagram of the watchdog timer.