SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
There is an IRQ_CROSSBAR module in the device, which is controlled by registers in the CTRL_MODULE_CORE submodule. The IRQ_CROSSBAR is able to map any of its input signals to any of its outputs. This module is associated with the device interrupt sources. The IRQs from all the device modules are connected to the IRQ_CROSSBAR inputs. Each module IRQ is connected only to one cross-bar input. Each output of the IRQ_CROSSBAR module is connected only to one interrupt line of certain interrupt controller (INTC). Thus, the device IRQs are mapped to the device INTCs through the IRQ_CROSSBAR. Some of these IRQs are mapped by default to certain interrupt lines of one of the device INTCs, but there are IRQs which are not mapped by default to any interrupt line of any device INTC. All IRQs, connected to the IRQ_CROSSBAR inputs, can be remapped to other interrupt lines of the different device INTCs through the CTRL_CORE_X_IRQ_B_A registers. Each of these registers has a structure described in Table 20-15.
Bits | Field Name | Description | Type | Note |
---|---|---|---|---|
31:25 | RESERVED | R | ||
24:16 | X_IRQ_A | Selects an interrupt source signal for the X_IRQ_A INTC line | RW | X is summarization. It is equal to:
A is also summarization. It shows the number of the line for the corresponding INTC. A is equal to 0, 1, 2, ..., and so on, depending on the count of the INTC lines controlled by the IRQ_CROSSBAR module. For more details, see Table 20-16. |
0x0: Reserved | ||||
0x1: Maps IRQ_CROSSBAR input 1 to X_IRQ_A INTC line | ||||
0x2: Maps IRQ_CROSSBAR input 2 to X_IRQ_A INTC line | ||||
0x-: .................................................... | ||||
0x64: Maps IRQ_CROSSBAR input 100 to X_IRQ_A INTC line | ||||
0x-: .................................................... | ||||
0x190 to 0x1FF: Reserved | ||||
15:9 | RESERVED | R | ||
8:0 | X_IRQ_B | Selects an interrupt source signal for the X_IRQ_B INTC line | RW | B is summarization. It shows the number of the line for the corresponding INTC. B is equal to 0, 1, 2, ..., and so on, depending on the count of the INTC lines controlled by the IRQ_CROSSBAR module. |
0x0: Reserved | ||||
0x1: Maps IRQ_CROSSBAR input 1 to X_IRQ_B INTC line | ||||
0x2: Maps IRQ_CROSSBAR input 2 to X_IRQ_B INTC line | ||||
0x-: .................................................... | ||||
0x64: Maps IRQ_CROSSBAR input 100 to X_IRQ_B INTC line | ||||
0x-: .................................................... | ||||
0x190 to 0x1FF: Reserved |
Figure 20-10 represents the way in which the IRQ_CROSSBAR module works. It shows the device modules and their IRQs connected to the IRQ_CROSSBAR inputs, the structure of the cross-bar and its outputs connected to the device INTCs.
Each IRQ_CROSSBAR control register has two 9-bit fields. Each 9-bit field is associated only with one interrupt line. Through this 9-bit field any of the IRQs connected to the IRQ_CROSSBAR inputs can be mapped to the INTC line associated with this 9-bit field. For example, the register CTRL_CORE_MPU_IRQ_74_75 is associated with MPU_IRQ_74 and MPU_IRQ_75. The 9-bit field CTRL_CORE_MPU_IRQ_74_75[24:16] MPU_IRQ_75 is associated only with MPU_IRQ_75 interrupt line of the MPU INTC. Setting this bit field to any other value different than its reset value will map another module IRQ to the MPU_IRQ_75 interrupt line. The default (reset) value of this bit field is 0x46 which corresponds to the IRQ_CROSSBAR_70 input. The PBIAS_IRQ is connected to this cross-bar input. Setting another register to 0x46 will cause the PBIAS_IRQ to be mapped to another INTC line. For example, if the CTRL_CORE_DSP1_IRQ_40_41[8:0] DSP1_IRQ_40 is set to 0x46 the PBIAS_IRQ will be mapped to the DSP1_IRQ_40 interrupt line. The same logic also applies to the other interrupt lines of the device INTCs.
In addition, not all of the interrupt lines of a given INTC are controlled by the IRQ_CROSSBAR registers. This means, that there are interrupt lines which are not connected to any IRQ_CROSSBAR output and thus only one IRQ is connected to these interrupt lines. In the most common case these lines are used by interrupt sources internal or specific for the corresponding module, which has an INTC.
Table 20-16 shows which lines of each INTC are associated with the IRQ_CROSSBAR control registers. The rest of the INTC lines (not listed in the table) cannot be controlled by the cross-bar registers.
MPU INTC Lines | DSP INTC Lines | IPU INTC Lines | EVE INTC Lines |
---|---|---|---|
MPU_IRQ_4, MPU_IRQ_7 to MPU_IRQ_130, MPU_IRQ_133 to MPU_IRQ_159 | DSP1_IRQ_32 to DSP1_IRQ_95, DSP2_IRQ_32 to DSP2_IRQ_95 | IPU1_IRQ_23 to IPU1_IRQ_79, IPU2_IRQ_23 to IPU2_IRQ_79 | EVE1_IRQ_0 to EVE1_IRQ_7, EVE2_IRQ_0 to EVE2_IRQ_7 |
The individual connection between all module IRQs and all IRQ_CROSSBAR inputs is shown in Section 19.3.8, Mapping of Device Interrupts to IRQ_CROSSBAR Inputs of Chapter 19, Interrupt Controllers.
In addition, the CTRL_CORE_OVS_IRQ_IO_MUX register is used to select for observation on two external pads any IRQ connected to the IRQ_CROSSBAR inputs. Using the CTRL_CORE_OVS_IRQ_IO_MUX[17:9] OVS_IRQ_IO_MUX_2 bit field all IRQs can be mapped to the obs_irq2 signal. The CTRL_CORE_OVS_IRQ_IO_MUX[8:0] OVS_IRQ_IO_MUX_1 bit field maps all IRQs to the obs_irq1 signal. For example, setting the CTRL_CORE_OVS_IRQ_IO_MUX[8:0] OVS_IRQ_IO_MUX_1 to 0x18 maps the GPIO1_IRQ_1 to the obs_irq1 line and thus this IRQ can be observed.