The UART can generate interrupts when the following conditions are observed:
- Overrun error
- Break error
- Parity error
- Framing error
- Receive time-out
- Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
- Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together
before being sent to the interrupt controller, so the UART can only generate a
single interrupt request to the controller at any given time. Software can service
multiple interrupt events in a single interrupt service routine by reading the UART
Masked Interrupt Status (UARTMIS) register.
The interrupt events that can trigger a
controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register
by setting the corresponding IM bits. If interrupts are not used, the raw interrupt
status is visible by way of the UART Raw Interrupt Status (UARTRIS) register.
Note: For receive time-out, the RTIM bit in the
UARTIM register must be set to see the RTMIS and RTRIS status in the UARTMIS and
UARTRIS registers.
Interrupts are always cleared (for the UARTMIS and
UARTRIS registers) by writing a 1 to the corresponding bit in the UART Interrupt
Clear (UARTICR) register.
The receive time-out interrupt is asserted when
the receive FIFO is not empty, and no further data is received over a 32-bit period
when the HSE bit is clear or over a 64-bit period when the HSE bit is set. The
receive time-out interrupt is cleared either when the FIFO becomes empty through
reading all the data (or by reading the holding register), or when a 1 is written to
the corresponding bit in the UARTICR register.
The receive interrupt changes state when one of
the following events occurs:
- If the FIFOs are enabled and
the receive FIFO reaches the programmed trigger level, the RXRIS bit is set.
The receive interrupt is cleared by reading data from the receive FIFO until
the receive FIFO becomes less than the trigger level, or by clearing the
interrupt by writing a 1 to the RXIC bit.
- If the FIFOs are disabled
(have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by
performing a single read of the receive FIFO, or by clearing the interrupt
by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of
the following events occurs:
- If the FIFOs are enabled and
the transmit FIFO progresses through the programmed trigger level, the TXRIS
bit is set. The transmit interrupt is based on a transition through level,
therefore the FIFO must be written past the programmed trigger level
otherwise no further transmit interrupts are generated. The transmit
interrupt is cleared by writing data to the transmit FIFO until the transmit
FIFO becomes greater than the trigger level, or by clearing the interrupt by
writing a 1 to the TXIC bit.
- If the FIFOs are disabled
(have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. The transmit interrupt
is cleared by performing a single write to the transmit FIFO, or by clearing
the interrupt by writing a 1 to the TXIC bit.