SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 41-122 lists the memory-mapped registers for the NVIC registers. All register offset addresses not listed in Table 41-122 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
100h | NVIC_ISER0 | NVIC Interrupt Set Enable Register 0 | Go | |
104h | NVIC_ISER1 | NVIC Interrupt Set Enable Register 1 | Go | |
180h | NVIC_ICER0 | NVIC Interrupt Clear Enable Register 0 | Go | |
184h | NVIC_ICER1 | NVIC Interrupt Clear Enable Register 1 | Go | |
200h | NVIC_ISPR0 | NVIC Interrupt Set Pending Register 0 | Go | |
204h | NVIC_ISPR1 | NVIC Interrupt Set Pending Register 1 | Go | |
208h | NVIC_ISPR2 | NVIC Interrupt Set Pending Register 2 | Go | |
280h | NVIC_ICPR0 | NVIC Interrupt Clear Pending Register 0 | Go | |
284h | NVIC_ICPR1 | NVIC Interrupt Clear Pending Register 1 | Go | |
300h | NVIC_IABR0 | NVIC Interrupt Active Bit Register 0 | Go | |
304h | NVIC_IABR1 | NVIC Interrupt Active Bit Register 1 | Go | |
400h | NVIC_IPR0 | NVIC Interrupt Priority Register 0 | Go | |
404h | NVIC_IPR1 | NVIC Interrupt Priority Register 1 | Go | |
408h | NVIC_IPR2 | NVIC Interrupt Priority Register 2 | Go | |
40Ch | NVIC_IPR3 | NVIC Interrupt Priority Register 3 | Go | |
410h | NVIC_IPR4 | NVIC Interrupt Priority Register 4 | Go | |
414h | NVIC_IPR5 | NVIC Interrupt Priority Register 5 | Go | |
418h | NVIC_IPR6 | NVIC Interrupt Priority Register 6 | Go | |
41Ch | NVIC_IPR7 | NVIC Interrupt Priority Register 7 | Go | |
420h | NVIC_IPR8 | NVIC Interrupt Priority Register 8 | Go | |
424h | NVIC_IPR9 | NVIC Interrupt Priority Register 9 | Go | |
428h | NVIC_IPR10 | NVIC Interrupt Priority Register 10 | Go | |
42Ch | NVIC_IPR11 | NVIC Interrupt Priority Register 11 | Go | |
430h | NVIC_IPR12 | NVIC Interrupt Priority Register 12 | Go | |
434h | NVIC_IPR13 | NVIC Interrupt Priority Register 13 | Go | |
438h | NVIC_IPR14 | NVIC Interrupt Priority Register 14 | Go | |
43Ch | NVIC_IPR15 | NVIC Interrupt Priority Register 15 | Go | |
F00h | STIR | Software Trigger Interrupt Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 41-123 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
NVIC_ISER0 is shown in Figure 41-113 and described in Table 41-124.
Return to the Summary Table.
NVIC Interrupt Set Enable Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SETENA31 | SETENA30 | SETENA29 | SETENA28 | SETENA27 | SETENA26 | SETENA25 | SETENA24 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SETENA23 | SETENA22 | SETENA21 | SETENA20 | SETENA19 | SETENA18 | SETENA17 | SETENA16 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SETENA15 | SETENA14 | SETENA13 | SETENA12 | SETENA11 | SETENA10 | SETENA9 | SETENA8 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA7 | SETENA6 | SETENA5 | SETENA4 | SETENA3 | SETENA2 | SETENA1 | SETENA0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SETENA31 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt31. Read: 0 = interrupt31 disabled 1 = interrupt31 enabled. Reset type: CM.SYSRESETn |
30 | SETENA30 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt30. Read: 0 = interrupt30 disabled 1 = interrupt30 enabled. Reset type: CM.SYSRESETn |
29 | SETENA29 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt29. Read: 0 = interrupt29 disabled 1 = interrupt29 enabled. Reset type: CM.SYSRESETn |
28 | SETENA28 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt28. Read: 0 = interrupt28 disabled 1 = interrupt28 enabled. Reset type: CM.SYSRESETn |
27 | SETENA27 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt27. Read: 0 = interrupt27 disabled 1 = interrupt27 enabled. Reset type: CM.SYSRESETn |
26 | SETENA26 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt26. Read: 0 = interrupt26 disabled 1 = interrupt26 enabled. Reset type: CM.SYSRESETn |
25 | SETENA25 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt25. Read: 0 = interrupt25 disabled 1 = interrupt25 enabled. Reset type: CM.SYSRESETn |
24 | SETENA24 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt24. Read: 0 = interrupt24 disabled 1 = interrupt24 enabled. Reset type: CM.SYSRESETn |
23 | SETENA23 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt23. Read: 0 = interrupt23 disabled 1 = interrupt23 enabled. Reset type: CM.SYSRESETn |
22 | SETENA22 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt22. Read: 0 = interrupt22 disabled 1 = interrupt22 enabled. Reset type: CM.SYSRESETn |
21 | SETENA21 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt21. Read: 0 = interrupt21 disabled 1 = interrupt21 enabled. Reset type: CM.SYSRESETn |
20 | SETENA20 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt20. Read: 0 = interrupt20 disabled 1 = interrupt20 enabled. Reset type: CM.SYSRESETn |
19 | SETENA19 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt19. Read: 0 = interrupt19 disabled 1 = interrupt19 enabled. Reset type: CM.SYSRESETn |
18 | SETENA18 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt18. Read: 0 = interrupt18 disabled 1 = interrupt18 enabled. Reset type: CM.SYSRESETn |
17 | SETENA17 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt17. Read: 0 = interrupt17 disabled 1 = interrupt17 enabled. Reset type: CM.SYSRESETn |
16 | SETENA16 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt16. Read: 0 = interrupt16 disabled 1 = interrupt16 enabled. Reset type: CM.SYSRESETn |
15 | SETENA15 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt15. Read: 0 = interrupt15 disabled 1 = interrupt15 enabled. Reset type: CM.SYSRESETn |
14 | SETENA14 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt14. Read: 0 = interrupt14 disabled 1 = interrupt14 enabled. Reset type: CM.SYSRESETn |
13 | SETENA13 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt13. Read: 0 = interrupt13 disabled 1 = interrupt13 enabled. Reset type: CM.SYSRESETn |
12 | SETENA12 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt12. Read: 0 = interrupt12 disabled 1 = interrupt12 enabled. Reset type: CM.SYSRESETn |
11 | SETENA11 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt11. Read: 0 = interrupt11 disabled 1 = interrupt11 enabled. Reset type: CM.SYSRESETn |
10 | SETENA10 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt10. Read: 0 = interrupt10 disabled 1 = interrupt10 enabled. Reset type: CM.SYSRESETn |
9 | SETENA9 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt9. Read: 0 = interrupt9 disabled 1 = interrupt9 enabled. Reset type: CM.SYSRESETn |
8 | SETENA8 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt8. Read: 0 = interrupt8 disabled 1 = interrupt8 enabled. Reset type: CM.SYSRESETn |
7 | SETENA7 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt7. Read: 0 = interrupt7 disabled 1 = interrupt7 enabled. Reset type: CM.SYSRESETn |
6 | SETENA6 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt6. Read: 0 = interrupt6 disabled 1 = interrupt6 enabled. Reset type: CM.SYSRESETn |
5 | SETENA5 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt5. Read: 0 = interrupt5 disabled 1 = interrupt5 enabled. Reset type: CM.SYSRESETn |
4 | SETENA4 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt4. Read: 0 = interrupt4 disabled 1 = interrupt4 enabled. Reset type: CM.SYSRESETn |
3 | SETENA3 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt3. Read: 0 = interrupt3 disabled 1 = interrupt3 enabled. Reset type: CM.SYSRESETn |
2 | SETENA2 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt2. Read: 0 = interrupt2 disabled 1 = interrupt2 enabled. Reset type: CM.SYSRESETn |
1 | SETENA1 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt1. Read: 0 = interrupt1 disabled 1 = interrupt1 enabled. Reset type: CM.SYSRESETn |
0 | SETENA0 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt0. Read: 0 = interrupt0 disabled 1 = interrupt0 enabled. Reset type: CM.SYSRESETn |
NVIC_ISER1 is shown in Figure 41-114 and described in Table 41-125.
Return to the Summary Table.
NVIC Interrupt Set Enable Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SETENA63 | SETENA62 | SETENA61 | SETENA60 | SETENA59 | SETENA58 | SETENA57 | SETENA56 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SETENA55 | SETENA54 | SETENA53 | SETENA52 | SETENA51 | SETENA50 | SETENA49 | SETENA48 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SETENA47 | SETENA46 | SETENA45 | SETENA44 | SETENA43 | SETENA42 | SETENA41 | SETENA40 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA39 | SETENA38 | SETENA37 | SETENA36 | SETENA35 | SETENA34 | SETENA33 | SETENA32 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SETENA63 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt63. Read: 0 = interrupt63 disabled 1 = interrupt63 enabled. Reset type: CM.SYSRESETn |
30 | SETENA62 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt62. Read: 0 = interrupt62 disabled 1 = interrupt62 enabled. Reset type: CM.SYSRESETn |
29 | SETENA61 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt61. Read: 0 = interrupt61 disabled 1 = interrupt61 enabled. Reset type: CM.SYSRESETn |
28 | SETENA60 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt60. Read: 0 = interrupt60 disabled 1 = interrupt60 enabled. Reset type: CM.SYSRESETn |
27 | SETENA59 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt59. Read: 0 = interrupt59 disabled 1 = interrupt59 enabled. Reset type: CM.SYSRESETn |
26 | SETENA58 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt58. Read: 0 = interrupt58 disabled 1 = interrupt58 enabled. Reset type: CM.SYSRESETn |
25 | SETENA57 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt57. Read: 0 = interrupt57 disabled 1 = interrupt57 enabled. Reset type: CM.SYSRESETn |
24 | SETENA56 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt56. Read: 0 = interrupt56 disabled 1 = interrupt56 enabled. Reset type: CM.SYSRESETn |
23 | SETENA55 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt55. Read: 0 = interrupt55 disabled 1 = interrupt55 enabled. Reset type: CM.SYSRESETn |
22 | SETENA54 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt54. Read: 0 = interrupt54 disabled 1 = interrupt54 enabled. Reset type: CM.SYSRESETn |
21 | SETENA53 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt53. Read: 0 = interrupt53 disabled 1 = interrupt53 enabled. Reset type: CM.SYSRESETn |
20 | SETENA52 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt52. Read: 0 = interrupt52 disabled 1 = interrupt52 enabled. Reset type: CM.SYSRESETn |
19 | SETENA51 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt51. Read: 0 = interrupt51 disabled 1 = interrupt51 enabled. Reset type: CM.SYSRESETn |
18 | SETENA50 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt50. Read: 0 = interrupt50 disabled 1 = interrupt50 enabled. Reset type: CM.SYSRESETn |
17 | SETENA49 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt49. Read: 0 = interrupt49 disabled 1 = interrupt49 enabled. Reset type: CM.SYSRESETn |
16 | SETENA48 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt48. Read: 0 = interrupt48 disabled 1 = interrupt48 enabled. Reset type: CM.SYSRESETn |
15 | SETENA47 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt47. Read: 0 = interrupt47 disabled 1 = interrupt47 enabled. Reset type: CM.SYSRESETn |
14 | SETENA46 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt46. Read: 0 = interrupt46 disabled 1 = interrupt46 enabled. Reset type: CM.SYSRESETn |
13 | SETENA45 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt45. Read: 0 = interrupt45 disabled 1 = interrupt45 enabled. Reset type: CM.SYSRESETn |
12 | SETENA44 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt44. Read: 0 = interrupt44 disabled 1 = interrupt44 enabled. Reset type: CM.SYSRESETn |
11 | SETENA43 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt43. Read: 0 = interrupt43 disabled 1 = interrupt43 enabled. Reset type: CM.SYSRESETn |
10 | SETENA42 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt42. Read: 0 = interrupt42 disabled 1 = interrupt42 enabled. Reset type: CM.SYSRESETn |
9 | SETENA41 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt41. Read: 0 = interrupt41 disabled 1 = interrupt41 enabled. Reset type: CM.SYSRESETn |
8 | SETENA40 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt40. Read: 0 = interrupt40 disabled 1 = interrupt40 enabled. Reset type: CM.SYSRESETn |
7 | SETENA39 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt39. Read: 0 = interrupt39 disabled 1 = interrupt39 enabled. Reset type: CM.SYSRESETn |
6 | SETENA38 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt38. Read: 0 = interrupt38 disabled 1 = interrupt38 enabled. Reset type: CM.SYSRESETn |
5 | SETENA37 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt37. Read: 0 = interrupt37 disabled 1 = interrupt37 enabled. Reset type: CM.SYSRESETn |
4 | SETENA36 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt36. Read: 0 = interrupt36 disabled 1 = interrupt36 enabled. Reset type: CM.SYSRESETn |
3 | SETENA35 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt35. Read: 0 = interrupt35 disabled 1 = interrupt35 enabled. Reset type: CM.SYSRESETn |
2 | SETENA34 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt34. Read: 0 = interrupt34 disabled 1 = interrupt34 enabled. Reset type: CM.SYSRESETn |
1 | SETENA33 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt33. Read: 0 = interrupt33 disabled 1 = interrupt33 enabled. Reset type: CM.SYSRESETn |
0 | SETENA32 | R/W1S | 0h | Interrupt set-enable bits. Write: =0 = no effect 1 = enable interrupt32. Read: 0 = interrupt32 disabled 1 = interrupt32 enabled. Reset type: CM.SYSRESETn |
NVIC_ICER0 is shown in Figure 41-115 and described in Table 41-126.
Return to the Summary Table.
NVIC Interrupt Clear Enable Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLRENA31 | CLRENA30 | CLRENA29 | CLRENA28 | CLRENA27 | CLRENA26 | CLRENA25 | CLRENA24 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLRENA23 | CLRENA22 | CLRENA21 | CLRENA20 | CLRENA19 | CLRENA18 | CLRENA17 | CLRENA16 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLRENA15 | CLRENA14 | CLRENA13 | CLRENA12 | CLRENA11 | CLRENA10 | CLRENA9 | CLRENA8 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA7 | CLRENA6 | CLRENA5 | CLRENA4 | CLRENA3 | CLRENA2 | CLRENA1 | CLRENA0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLRENA31 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt31. Read: 0 = interrupt31 disabled 1 = interrupt31 enabled. Reset type: CM.SYSRESETn |
30 | CLRENA30 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt30. Read: 0 = interrupt30 disabled 1 = interrupt30 enabled. Reset type: CM.SYSRESETn |
29 | CLRENA29 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt29. Read: 0 = interrupt29 disabled 1 = interrupt29 enabled. Reset type: CM.SYSRESETn |
28 | CLRENA28 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt28. Read: 0 = interrupt28 disabled 1 = interrupt28 enabled. Reset type: CM.SYSRESETn |
27 | CLRENA27 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt27. Read: 0 = interrupt27 disabled 1 = interrupt27 enabled. Reset type: CM.SYSRESETn |
26 | CLRENA26 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt26. Read: 0 = interrupt26 disabled 1 = interrupt26 enabled. Reset type: CM.SYSRESETn |
25 | CLRENA25 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt25. Read: 0 = interrupt25 disabled 1 = interrupt25 enabled. Reset type: CM.SYSRESETn |
24 | CLRENA24 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt24. Read: 0 = interrupt24 disabled 1 = interrupt24 enabled. Reset type: CM.SYSRESETn |
23 | CLRENA23 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt23. Read: 0 = interrupt23 disabled 1 = interrupt23 enabled. Reset type: CM.SYSRESETn |
22 | CLRENA22 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt22. Read: 0 = interrupt22 disabled 1 = interrupt22 enabled. Reset type: CM.SYSRESETn |
21 | CLRENA21 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt21. Read: 0 = interrupt21 disabled 1 = interrupt21 enabled. Reset type: CM.SYSRESETn |
20 | CLRENA20 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt20. Read: 0 = interrupt20 disabled 1 = interrupt20 enabled. Reset type: CM.SYSRESETn |
19 | CLRENA19 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt19. Read: 0 = interrupt19 disabled 1 = interrupt19 enabled. Reset type: CM.SYSRESETn |
18 | CLRENA18 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt18. Read: 0 = interrupt18 disabled 1 = interrupt18 enabled. Reset type: CM.SYSRESETn |
17 | CLRENA17 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt17. Read: 0 = interrupt17 disabled 1 = interrupt17 enabled. Reset type: CM.SYSRESETn |
16 | CLRENA16 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt16. Read: 0 = interrupt16 disabled 1 = interrupt16 enabled. Reset type: CM.SYSRESETn |
15 | CLRENA15 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt15. Read: 0 = interrupt15 disabled 1 = interrupt15 enabled. Reset type: CM.SYSRESETn |
14 | CLRENA14 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt14. Read: 0 = interrupt14 disabled 1 = interrupt14 enabled. Reset type: CM.SYSRESETn |
13 | CLRENA13 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt13. Read: 0 = interrupt13 disabled 1 = interrupt13 enabled. Reset type: CM.SYSRESETn |
12 | CLRENA12 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt12. Read: 0 = interrupt12 disabled 1 = interrupt12 enabled. Reset type: CM.SYSRESETn |
11 | CLRENA11 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt11. Read: 0 = interrupt11 disabled 1 = interrupt11 enabled. Reset type: CM.SYSRESETn |
10 | CLRENA10 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt10. Read: 0 = interrupt10 disabled 1 = interrupt10 enabled. Reset type: CM.SYSRESETn |
9 | CLRENA9 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt9. Read: 0 = interrupt9 disabled 1 = interrupt9 enabled. Reset type: CM.SYSRESETn |
8 | CLRENA8 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt8. Read: 0 = interrupt8 disabled 1 = interrupt8 enabled. Reset type: CM.SYSRESETn |
7 | CLRENA7 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt7. Read: 0 = interrupt7 disabled 1 = interrupt7 enabled. Reset type: CM.SYSRESETn |
6 | CLRENA6 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt6. Read: 0 = interrupt6 disabled 1 = interrupt6 enabled. Reset type: CM.SYSRESETn |
5 | CLRENA5 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt5. Read: 0 = interrupt5 disabled 1 = interrupt5 enabled. Reset type: CM.SYSRESETn |
4 | CLRENA4 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt4. Read: 0 = interrupt4 disabled 1 = interrupt4 enabled. Reset type: CM.SYSRESETn |
3 | CLRENA3 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt3. Read: 0 = interrupt3 disabled 1 = interrupt3 enabled. Reset type: CM.SYSRESETn |
2 | CLRENA2 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt2. Read: 0 = interrupt2 disabled 1 = interrupt2 enabled. Reset type: CM.SYSRESETn |
1 | CLRENA1 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt1. Read: 0 = interrupt1 disabled 1 = interrupt1 enabled. Reset type: CM.SYSRESETn |
0 | CLRENA0 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt0. Read: 0 = interrupt0 disabled 1 = interrupt0 enabled. Reset type: CM.SYSRESETn |
NVIC_ICER1 is shown in Figure 41-116 and described in Table 41-127.
Return to the Summary Table.
NVIC Interrupt Clear Enable Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLRENA63 | CLRENA62 | CLRENA61 | CLRENA60 | CLRENA59 | CLRENA58 | CLRENA57 | CLRENA56 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLRENA55 | CLRENA54 | CLRENA53 | CLRENA52 | CLRENA51 | CLRENA50 | CLRENA49 | CLRENA48 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLRENA47 | CLRENA46 | CLRENA45 | CLRENA44 | CLRENA43 | CLRENA42 | CLRENA41 | CLRENA40 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA39 | CLRENA38 | CLRENA37 | CLRENA36 | CLRENA35 | CLRENA34 | CLRENA33 | CLRENA32 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLRENA63 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt63. Read: 0 = interrupt63 disabled 1 = interrupt63 enabled. Reset type: CM.SYSRESETn |
30 | CLRENA62 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt62. Read: 0 = interrupt62 disabled 1 = interrupt62 enabled. Reset type: CM.SYSRESETn |
29 | CLRENA61 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt61. Read: 0 = interrupt61 disabled 1 = interrupt61 enabled. Reset type: CM.SYSRESETn |
28 | CLRENA60 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt60. Read: 0 = interrupt60 disabled 1 = interrupt60 enabled. Reset type: CM.SYSRESETn |
27 | CLRENA59 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt59. Read: 0 = interrupt59 disabled 1 = interrupt59 enabled. Reset type: CM.SYSRESETn |
26 | CLRENA58 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt58. Read: 0 = interrupt58 disabled 1 = interrupt58 enabled. Reset type: CM.SYSRESETn |
25 | CLRENA57 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt57. Read: 0 = interrupt57 disabled 1 = interrupt57 enabled. Reset type: CM.SYSRESETn |
24 | CLRENA56 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt56. Read: 0 = interrupt56 disabled 1 = interrupt56 enabled. Reset type: CM.SYSRESETn |
23 | CLRENA55 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt55. Read: 0 = interrupt55 disabled 1 = interrupt55 enabled. Reset type: CM.SYSRESETn |
22 | CLRENA54 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt54. Read: 0 = interrupt54 disabled 1 = interrupt54 enabled. Reset type: CM.SYSRESETn |
21 | CLRENA53 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt53. Read: 0 = interrupt53 disabled 1 = interrupt53 enabled. Reset type: CM.SYSRESETn |
20 | CLRENA52 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt52. Read: 0 = interrupt52 disabled 1 = interrupt52 enabled. Reset type: CM.SYSRESETn |
19 | CLRENA51 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt51. Read: 0 = interrupt51 disabled 1 = interrupt51 enabled. Reset type: CM.SYSRESETn |
18 | CLRENA50 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt50. Read: 0 = interrupt50 disabled 1 = interrupt50 enabled. Reset type: CM.SYSRESETn |
17 | CLRENA49 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt49. Read: 0 = interrupt49 disabled 1 = interrupt49 enabled. Reset type: CM.SYSRESETn |
16 | CLRENA48 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt48. Read: 0 = interrupt48 disabled 1 = interrupt48 enabled. Reset type: CM.SYSRESETn |
15 | CLRENA47 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt47. Read: 0 = interrupt47 disabled 1 = interrupt47 enabled. Reset type: CM.SYSRESETn |
14 | CLRENA46 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt46. Read: 0 = interrupt46 disabled 1 = interrupt46 enabled. Reset type: CM.SYSRESETn |
13 | CLRENA45 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt45. Read: 0 = interrupt45 disabled 1 = interrupt45 enabled. Reset type: CM.SYSRESETn |
12 | CLRENA44 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt44. Read: 0 = interrupt44 disabled 1 = interrupt44 enabled. Reset type: CM.SYSRESETn |
11 | CLRENA43 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt43. Read: 0 = interrupt43 disabled 1 = interrupt43 enabled. Reset type: CM.SYSRESETn |
10 | CLRENA42 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt42. Read: 0 = interrupt42 disabled 1 = interrupt42 enabled. Reset type: CM.SYSRESETn |
9 | CLRENA41 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt41. Read: 0 = interrupt41 disabled 1 = interrupt41 enabled. Reset type: CM.SYSRESETn |
8 | CLRENA40 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt40. Read: 0 = interrupt40 disabled 1 = interrupt40 enabled. Reset type: CM.SYSRESETn |
7 | CLRENA39 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt39. Read: 0 = interrupt39 disabled 1 = interrupt39 enabled. Reset type: CM.SYSRESETn |
6 | CLRENA38 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt38. Read: 0 = interrupt38 disabled 1 = interrupt38 enabled. Reset type: CM.SYSRESETn |
5 | CLRENA37 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt37. Read: 0 = interrupt37 disabled 1 = interrupt37 enabled. Reset type: CM.SYSRESETn |
4 | CLRENA36 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt36. Read: 0 = interrupt36 disabled 1 = interrupt36 enabled. Reset type: CM.SYSRESETn |
3 | CLRENA35 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt35. Read: 0 = interrupt35 disabled 1 = interrupt35 enabled. Reset type: CM.SYSRESETn |
2 | CLRENA34 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt34. Read: 0 = interrupt34 disabled 1 = interrupt34 enabled. Reset type: CM.SYSRESETn |
1 | CLRENA33 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt33. Read: 0 = interrupt33 disabled 1 = interrupt33 enabled. Reset type: CM.SYSRESETn |
0 | CLRENA32 | R/W1S | 0h | Interrupt clear enable bits. Write: =0 = no effect 1 = disable interrupt32. Read: 0 = interrupt32 disabled 1 = interrupt32 enabled. Reset type: CM.SYSRESETn |
NVIC_ISPR0 is shown in Figure 41-117 and described in Table 41-128.
Return to the Summary Table.
NVIC Interrupt Set Pending Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SETPEND31 | SETPEND30 | SETPEND29 | SETPEND28 | SETPEND27 | SETPEND26 | SETPEND25 | SETPEND24 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SETPEND23 | SETPEND22 | SETPEND21 | SETPEND20 | SETPEND19 | SETPEND18 | SETPEND17 | SETPEND16 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SETPEND15 | SETPEND14 | SETPEND13 | SETPEND12 | SETPEND11 | SETPEND10 | SETPEND9 | SETPEND8 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND7 | SETPEND6 | SETPEND5 | SETPEND4 | SETPEND3 | SETPEND2 | SETPEND1 | SETPEND0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SETPEND31 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 31 state to pending. Read: 0 = interrupt31 is not pending 1 = interrupt31 is pending. Reset type: CM.SYSRESETn |
30 | SETPEND30 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 30 state to pending. Read: 0 = interrupt30 is not pending 1 = interrupt30 is pending. Reset type: CM.SYSRESETn |
29 | SETPEND29 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 29 state to pending. Read: 0 = interrupt29 is not pending 1 = interrupt29 is pending. Reset type: CM.SYSRESETn |
28 | SETPEND28 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 28 state to pending. Read: 0 = interrupt28 is not pending 1 = interrupt28 is pending. Reset type: CM.SYSRESETn |
27 | SETPEND27 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 27 state to pending. Read: 0 = interrupt27 is not pending 1 = interrupt27 is pending. Reset type: CM.SYSRESETn |
26 | SETPEND26 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 26 state to pending. Read: 0 = interrupt26 is not pending 1 = interrupt26 is pending. Reset type: CM.SYSRESETn |
25 | SETPEND25 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 25 state to pending. Read: 0 = interrupt25 is not pending 1 = interrupt25 is pending. Reset type: CM.SYSRESETn |
24 | SETPEND24 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 24 state to pending. Read: 0 = interrupt24 is not pending 1 = interrupt24 is pending. Reset type: CM.SYSRESETn |
23 | SETPEND23 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 23 state to pending. Read: 0 = interrupt23 is not pending 1 = interrupt23 is pending. Reset type: CM.SYSRESETn |
22 | SETPEND22 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 22 state to pending. Read: 0 = interrupt22 is not pending 1 = interrupt22 is pending. Reset type: CM.SYSRESETn |
21 | SETPEND21 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 21 state to pending. Read: 0 = interrupt21 is not pending 1 = interrupt21 is pending. Reset type: CM.SYSRESETn |
20 | SETPEND20 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 20 state to pending. Read: 0 = interrupt20 is not pending 1 = interrupt20 is pending. Reset type: CM.SYSRESETn |
19 | SETPEND19 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 19 state to pending. Read: 0 = interrupt19 is not pending 1 = interrupt19 is pending. Reset type: CM.SYSRESETn |
18 | SETPEND18 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 18 state to pending. Read: 0 = interrupt18 is not pending 1 = interrupt18 is pending. Reset type: CM.SYSRESETn |
17 | SETPEND17 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 17 state to pending. Read: 0 = interrupt17 is not pending 1 = interrupt17 is pending. Reset type: CM.SYSRESETn |
16 | SETPEND16 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 16 state to pending. Read: 0 = interrupt16 is not pending 1 = interrupt16 is pending. Reset type: CM.SYSRESETn |
15 | SETPEND15 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 15 state to pending. Read: 0 = interrupt15 is not pending 1 = interrupt15 is pending. Reset type: CM.SYSRESETn |
14 | SETPEND14 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 14 state to pending. Read: 0 = interrupt14 is not pending 1 = interrupt14 is pending. Reset type: CM.SYSRESETn |
13 | SETPEND13 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 13 state to pending. Read: 0 = interrupt13 is not pending 1 = interrupt13 is pending. Reset type: CM.SYSRESETn |
12 | SETPEND12 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 12 state to pending. Read: 0 = interrupt12 is not pending 1 = interrupt12 is pending. Reset type: CM.SYSRESETn |
11 | SETPEND11 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 11 state to pending. Read: 0 = interrupt11 is not pending 1 = interrupt11 is pending. Reset type: CM.SYSRESETn |
10 | SETPEND10 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 10 state to pending. Read: 0 = interrupt10 is not pending 1 = interrupt10 is pending. Reset type: CM.SYSRESETn |
9 | SETPEND9 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 9 state to pending. Read: 0 = interrupt9 is not pending 1 = interrupt9 is pending. Reset type: CM.SYSRESETn |
8 | SETPEND8 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 8 state to pending. Read: 0 = interrupt8 is not pending 1 = interrupt8 is pending. Reset type: CM.SYSRESETn |
7 | SETPEND7 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 7 state to pending. Read: 0 = interrupt7 is not pending 1 = interrupt7 is pending. Reset type: CM.SYSRESETn |
6 | SETPEND6 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 6 state to pending. Read: 0 = interrupt6 is not pending 1 = interrupt6 is pending. Reset type: CM.SYSRESETn |
5 | SETPEND5 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 5 state to pending. Read: 0 = interrupt5 is not pending 1 = interrupt5 is pending. Reset type: CM.SYSRESETn |
4 | SETPEND4 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 4 state to pending. Read: 0 = interrupt4 is not pending 1 = interrupt4 is pending. Reset type: CM.SYSRESETn |
3 | SETPEND3 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 3 state to pending. Read: 0 = interrupt3 is not pending 1 = interrupt3 is pending. Reset type: CM.SYSRESETn |
2 | SETPEND2 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 2 state to pending. Read: 0 = interrupt2 is not pending 1 = interrupt2 is pending. Reset type: CM.SYSRESETn |
1 | SETPEND1 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 1 state to pending. Read: 0 = interrupt1 is not pending 1 = interrupt1 is pending. Reset type: CM.SYSRESETn |
0 | SETPEND0 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 0 state to pending. Read: 0 = interrupt0 is not pending 1 = interrupt0 is pending. Reset type: CM.SYSRESETn |
NVIC_ISPR1 is shown in Figure 41-118 and described in Table 41-129.
Return to the Summary Table.
NVIC Interrupt Set Pending Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SETPEND63 | SETPEND62 | SETPEND61 | SETPEND60 | SETPEND59 | SETPEND58 | SETPEND57 | SETPEND56 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SETPEND55 | SETPEND54 | SETPEND53 | SETPEND52 | SETPEND51 | SETPEND50 | SETPEND49 | SETPEND48 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SETPEND47 | SETPEND46 | SETPEND45 | SETPEND44 | SETPEND43 | SETPEND42 | SETPEND41 | SETPEND40 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND39 | SETPEND38 | SETPEND37 | SETPEND36 | SETPEND35 | SETPEND34 | SETPEND33 | SETPEND32 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SETPEND63 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 63 state to pending. Read: 0 = interrupt63 is not pending 1 = interrupt63 is pending. Reset type: CM.SYSRESETn |
30 | SETPEND62 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 62 state to pending. Read: 0 = interrupt62 is not pending 1 = interrupt62 is pending. Reset type: CM.SYSRESETn |
29 | SETPEND61 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 61 state to pending. Read: 0 = interrupt61 is not pending 1 = interrupt61 is pending. Reset type: CM.SYSRESETn |
28 | SETPEND60 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 60 state to pending. Read: 0 = interrupt60 is not pending 1 = interrupt60 is pending. Reset type: CM.SYSRESETn |
27 | SETPEND59 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 59 state to pending. Read: 0 = interrupt59 is not pending 1 = interrupt59 is pending. Reset type: CM.SYSRESETn |
26 | SETPEND58 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 58 state to pending. Read: 0 = interrupt58 is not pending 1 = interrupt58 is pending. Reset type: CM.SYSRESETn |
25 | SETPEND57 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 57 state to pending. Read: 0 = interrupt57 is not pending 1 = interrupt57 is pending. Reset type: CM.SYSRESETn |
24 | SETPEND56 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 56 state to pending. Read: 0 = interrupt56 is not pending 1 = interrupt56 is pending. Reset type: CM.SYSRESETn |
23 | SETPEND55 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 55 state to pending. Read: 0 = interrupt55 is not pending 1 = interrupt55 is pending. Reset type: CM.SYSRESETn |
22 | SETPEND54 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 54 state to pending. Read: 0 = interrupt54 is not pending 1 = interrupt54 is pending. Reset type: CM.SYSRESETn |
21 | SETPEND53 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 53 state to pending. Read: 0 = interrupt53 is not pending 1 = interrupt53 is pending. Reset type: CM.SYSRESETn |
20 | SETPEND52 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 52 state to pending. Read: 0 = interrupt52 is not pending 1 = interrupt52 is pending. Reset type: CM.SYSRESETn |
19 | SETPEND51 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 51 state to pending. Read: 0 = interrupt51 is not pending 1 = interrupt51 is pending. Reset type: CM.SYSRESETn |
18 | SETPEND50 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 50 state to pending. Read: 0 = interrupt50 is not pending 1 = interrupt50 is pending. Reset type: CM.SYSRESETn |
17 | SETPEND49 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 49 state to pending. Read: 0 = interrupt49 is not pending 1 = interrupt49 is pending. Reset type: CM.SYSRESETn |
16 | SETPEND48 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 48 state to pending. Read: 0 = interrupt48 is not pending 1 = interrupt48 is pending. Reset type: CM.SYSRESETn |
15 | SETPEND47 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 47 state to pending. Read: 0 = interrupt47 is not pending 1 = interrupt47 is pending. Reset type: CM.SYSRESETn |
14 | SETPEND46 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 46 state to pending. Read: 0 = interrupt46 is not pending 1 = interrupt46 is pending. Reset type: CM.SYSRESETn |
13 | SETPEND45 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 45 state to pending. Read: 0 = interrupt45 is not pending 1 = interrupt45 is pending. Reset type: CM.SYSRESETn |
12 | SETPEND44 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 44 state to pending. Read: 0 = interrupt44 is not pending 1 = interrupt44 is pending. Reset type: CM.SYSRESETn |
11 | SETPEND43 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 43 state to pending. Read: 0 = interrupt43 is not pending 1 = interrupt43 is pending. Reset type: CM.SYSRESETn |
10 | SETPEND42 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 42 state to pending. Read: 0 = interrupt42 is not pending 1 = interrupt42 is pending. Reset type: CM.SYSRESETn |
9 | SETPEND41 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 41 state to pending. Read: 0 = interrupt41 is not pending 1 = interrupt41 is pending. Reset type: CM.SYSRESETn |
8 | SETPEND40 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 40 state to pending. Read: 0 = interrupt40 is not pending 1 = interrupt40 is pending. Reset type: CM.SYSRESETn |
7 | SETPEND39 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 39 state to pending. Read: 0 = interrupt39 is not pending 1 = interrupt39 is pending. Reset type: CM.SYSRESETn |
6 | SETPEND38 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 38 state to pending. Read: 0 = interrupt38 is not pending 1 = interrupt38 is pending. Reset type: CM.SYSRESETn |
5 | SETPEND37 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 37 state to pending. Read: 0 = interrupt37 is not pending 1 = interrupt37 is pending. Reset type: CM.SYSRESETn |
4 | SETPEND36 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 36 state to pending. Read: 0 = interrupt36 is not pending 1 = interrupt36 is pending. Reset type: CM.SYSRESETn |
3 | SETPEND35 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 35 state to pending. Read: 0 = interrupt35 is not pending 1 = interrupt35 is pending. Reset type: CM.SYSRESETn |
2 | SETPEND34 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 34 state to pending. Read: 0 = interrupt34 is not pending 1 = interrupt34 is pending. Reset type: CM.SYSRESETn |
1 | SETPEND33 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 33 state to pending. Read: 0 = interrupt33 is not pending 1 = interrupt33 is pending. Reset type: CM.SYSRESETn |
0 | SETPEND32 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 32 state to pending. Read: 0 = interrupt32 is not pending 1 = interrupt32 is pending. Reset type: CM.SYSRESETn |
NVIC_ISPR2 is shown in Figure 41-119 and described in Table 41-130.
Return to the Summary Table.
NVIC Interrupt Set Pending Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SETPEND95 | SETPEND94 | SETPEND93 | SETPEND92 | SETPEND91 | SETPEND90 | SETPEND89 | SETPEND88 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SETPEND87 | SETPEND86 | SETPEND85 | SETPEND84 | SETPEND83 | SETPEND82 | SETPEND81 | SETPEND80 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SETPEND79 | SETPEND78 | SETPEND77 | SETPEND76 | SETPEND75 | SETPEND74 | SETPEND73 | SETPEND72 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND71 | SETPEND70 | SETPEND69 | SETPEND68 | SETPEND67 | SETPEND66 | SETPEND65 | SETPEND64 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SETPEND95 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 95 state to pending. Read: 0 = interrupt95 is not pending 1 = interrupt95 is pending. Reset type: CM.SYSRESETn |
30 | SETPEND94 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 94 state to pending. Read: 0 = interrupt94 is not pending 1 = interrupt94 is pending. Reset type: CM.SYSRESETn |
29 | SETPEND93 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 93 state to pending. Read: 0 = interrupt93 is not pending 1 = interrupt93 is pending. Reset type: CM.SYSRESETn |
28 | SETPEND92 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 92 state to pending. Read: 0 = interrupt92 is not pending 1 = interrupt92 is pending. Reset type: CM.SYSRESETn |
27 | SETPEND91 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 91 state to pending. Read: 0 = interrupt91 is not pending 1 = interrupt91 is pending. Reset type: CM.SYSRESETn |
26 | SETPEND90 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 90 state to pending. Read: 0 = interrupt90 is not pending 1 = interrupt90 is pending. Reset type: CM.SYSRESETn |
25 | SETPEND89 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 89 state to pending. Read: 0 = interrupt89 is not pending 1 = interrupt89 is pending. Reset type: CM.SYSRESETn |
24 | SETPEND88 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 88 state to pending. Read: 0 = interrupt88 is not pending 1 = interrupt88 is pending. Reset type: CM.SYSRESETn |
23 | SETPEND87 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 87 state to pending. Read: 0 = interrupt87 is not pending 1 = interrupt87 is pending. Reset type: CM.SYSRESETn |
22 | SETPEND86 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 86 state to pending. Read: 0 = interrupt86 is not pending 1 = interrupt86 is pending. Reset type: CM.SYSRESETn |
21 | SETPEND85 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 85 state to pending. Read: 0 = interrupt85 is not pending 1 = interrupt85 is pending. Reset type: CM.SYSRESETn |
20 | SETPEND84 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 84 state to pending. Read: 0 = interrupt84 is not pending 1 = interrupt84 is pending. Reset type: CM.SYSRESETn |
19 | SETPEND83 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 83 state to pending. Read: 0 = interrupt83 is not pending 1 = interrupt83 is pending. Reset type: CM.SYSRESETn |
18 | SETPEND82 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 82 state to pending. Read: 0 = interrupt82 is not pending 1 = interrupt82 is pending. Reset type: CM.SYSRESETn |
17 | SETPEND81 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 81 state to pending. Read: 0 = interrupt81 is not pending 1 = interrupt81 is pending. Reset type: CM.SYSRESETn |
16 | SETPEND80 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 80 state to pending. Read: 0 = interrupt80 is not pending 1 = interrupt80 is pending. Reset type: CM.SYSRESETn |
15 | SETPEND79 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 79 state to pending. Read: 0 = interrupt79 is not pending 1 = interrupt79 is pending. Reset type: CM.SYSRESETn |
14 | SETPEND78 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 78 state to pending. Read: 0 = interrupt78 is not pending 1 = interrupt78 is pending. Reset type: CM.SYSRESETn |
13 | SETPEND77 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 77 state to pending. Read: 0 = interrupt77 is not pending 1 = interrupt77 is pending. Reset type: CM.SYSRESETn |
12 | SETPEND76 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 76 state to pending. Read: 0 = interrupt76 is not pending 1 = interrupt76 is pending. Reset type: CM.SYSRESETn |
11 | SETPEND75 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 75 state to pending. Read: 0 = interrupt75 is not pending 1 = interrupt75 is pending. Reset type: CM.SYSRESETn |
10 | SETPEND74 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 74 state to pending. Read: 0 = interrupt74 is not pending 1 = interrupt74 is pending. Reset type: CM.SYSRESETn |
9 | SETPEND73 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 73 state to pending. Read: 0 = interrupt73 is not pending 1 = interrupt73 is pending. Reset type: CM.SYSRESETn |
8 | SETPEND72 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 72 state to pending. Read: 0 = interrupt72 is not pending 1 = interrupt72 is pending. Reset type: CM.SYSRESETn |
7 | SETPEND71 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 71 state to pending. Read: 0 = interrupt71 is not pending 1 = interrupt71 is pending. Reset type: CM.SYSRESETn |
6 | SETPEND70 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 70 state to pending. Read: 0 = interrupt70 is not pending 1 = interrupt70 is pending. Reset type: CM.SYSRESETn |
5 | SETPEND69 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 69 state to pending. Read: 0 = interrupt69 is not pending 1 = interrupt69 is pending. Reset type: CM.SYSRESETn |
4 | SETPEND68 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 68 state to pending. Read: 0 = interrupt68 is not pending 1 = interrupt68 is pending. Reset type: CM.SYSRESETn |
3 | SETPEND67 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 67 state to pending. Read: 0 = interrupt67 is not pending 1 = interrupt67 is pending. Reset type: CM.SYSRESETn |
2 | SETPEND66 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 66 state to pending. Read: 0 = interrupt66 is not pending 1 = interrupt66 is pending. Reset type: CM.SYSRESETn |
1 | SETPEND65 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 65 state to pending. Read: 0 = interrupt65 is not pending 1 = interrupt65 is pending. Reset type: CM.SYSRESETn |
0 | SETPEND64 | R/W1S | 0h | Set interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 64 state to pending. Read: 0 = interrupt64 is not pending 1 = interrupt64 is pending. Reset type: CM.SYSRESETn |
NVIC_ICPR0 is shown in Figure 41-120 and described in Table 41-131.
Return to the Summary Table.
NVIC Interrupt Clear Pending Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLRPEND31 | CLRPEND30 | CLRPEND29 | CLRPEND28 | CLRPEND27 | CLRPEND26 | CLRPEND25 | CLRPEND24 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLRPEND23 | CLRPEND22 | CLRPEND21 | CLRPEND20 | CLRPEND19 | CLRPEND18 | CLRPEND17 | CLRPEND16 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLRPEND15 | CLRPEND14 | CLRPEND13 | CLRPEND12 | CLRPEND11 | CLRPEND10 | CLRPEND9 | CLRPEND8 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND7 | CLRPEND6 | CLRPEND5 | CLRPEND4 | CLRPEND3 | CLRPEND2 | CLRPEND1 | CLRPEND0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLRPEND31 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 31 state to not pending. Read: 0 = interrupt31 is not pending 1 = interrupt31 is pending. Reset type: CM.SYSRESETn |
30 | CLRPEND30 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 30 state to not pending. Read: 0 = interrupt30 is not pending 1 = interrupt30 is pending. Reset type: CM.SYSRESETn |
29 | CLRPEND29 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 29 state to not pending. Read: 0 = interrupt29 is not pending 1 = interrupt29 is pending. Reset type: CM.SYSRESETn |
28 | CLRPEND28 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 28 state to not pending. Read: 0 = interrupt28 is not pending 1 = interrupt28 is pending. Reset type: CM.SYSRESETn |
27 | CLRPEND27 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 27 state to not pending. Read: 0 = interrupt27 is not pending 1 = interrupt27 is pending. Reset type: CM.SYSRESETn |
26 | CLRPEND26 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 26 state to not pending. Read: 0 = interrupt26 is not pending 1 = interrupt26 is pending. Reset type: CM.SYSRESETn |
25 | CLRPEND25 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 25 state to not pending. Read: 0 = interrupt25 is not pending 1 = interrupt25 is pending. Reset type: CM.SYSRESETn |
24 | CLRPEND24 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 24 state to not pending. Read: 0 = interrupt24 is not pending 1 = interrupt24 is pending. Reset type: CM.SYSRESETn |
23 | CLRPEND23 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 23 state to not pending. Read: 0 = interrupt23 is not pending 1 = interrupt23 is pending. Reset type: CM.SYSRESETn |
22 | CLRPEND22 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 22 state to not pending. Read: 0 = interrupt22 is not pending 1 = interrupt22 is pending. Reset type: CM.SYSRESETn |
21 | CLRPEND21 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 21 state to not pending. Read: 0 = interrupt21 is not pending 1 = interrupt21 is pending. Reset type: CM.SYSRESETn |
20 | CLRPEND20 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 20 state to not pending. Read: 0 = interrupt20 is not pending 1 = interrupt20 is pending. Reset type: CM.SYSRESETn |
19 | CLRPEND19 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 19 state to not pending. Read: 0 = interrupt19 is not pending 1 = interrupt19 is pending. Reset type: CM.SYSRESETn |
18 | CLRPEND18 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 18 state to not pending. Read: 0 = interrupt18 is not pending 1 = interrupt18 is pending. Reset type: CM.SYSRESETn |
17 | CLRPEND17 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 17 state to not pending. Read: 0 = interrupt17 is not pending 1 = interrupt17 is pending. Reset type: CM.SYSRESETn |
16 | CLRPEND16 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 16 state to not pending. Read: 0 = interrupt16 is not pending 1 = interrupt16 is pending. Reset type: CM.SYSRESETn |
15 | CLRPEND15 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 15 state to not pending. Read: 0 = interrupt15 is not pending 1 = interrupt15 is pending. Reset type: CM.SYSRESETn |
14 | CLRPEND14 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 14 state to not pending. Read: 0 = interrupt14 is not pending 1 = interrupt14 is pending. Reset type: CM.SYSRESETn |
13 | CLRPEND13 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 13 state to not pending. Read: 0 = interrupt13 is not pending 1 = interrupt13 is pending. Reset type: CM.SYSRESETn |
12 | CLRPEND12 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 12 state to not pending. Read: 0 = interrupt12 is not pending 1 = interrupt12 is pending. Reset type: CM.SYSRESETn |
11 | CLRPEND11 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 11 state to not pending. Read: 0 = interrupt11 is not pending 1 = interrupt11 is pending. Reset type: CM.SYSRESETn |
10 | CLRPEND10 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 10 state to not pending. Read: 0 = interrupt10 is not pending 1 = interrupt10 is pending. Reset type: CM.SYSRESETn |
9 | CLRPEND9 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 9 state to not pending. Read: 0 = interrupt9 is not pending 1 = interrupt9 is pending. Reset type: CM.SYSRESETn |
8 | CLRPEND8 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 8 state to not pending. Read: 0 = interrupt8 is not pending 1 = interrupt8 is pending. Reset type: CM.SYSRESETn |
7 | CLRPEND7 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 7 state to not pending. Read: 0 = interrupt7 is not pending 1 = interrupt7 is pending. Reset type: CM.SYSRESETn |
6 | CLRPEND6 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 6 state to not pending. Read: 0 = interrupt6 is not pending 1 = interrupt6 is pending. Reset type: CM.SYSRESETn |
5 | CLRPEND5 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 5 state to not pending. Read: 0 = interrupt5 is not pending 1 = interrupt5 is pending. Reset type: CM.SYSRESETn |
4 | CLRPEND4 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 4 state to not pending. Read: 0 = interrupt4 is not pending 1 = interrupt4 is pending. Reset type: CM.SYSRESETn |
3 | CLRPEND3 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 3 state to not pending. Read: 0 = interrupt3 is not pending 1 = interrupt3 is pending. Reset type: CM.SYSRESETn |
2 | CLRPEND2 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 2 state to not pending. Read: 0 = interrupt2 is not pending 1 = interrupt2 is pending. Reset type: CM.SYSRESETn |
1 | CLRPEND1 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 1 state to not pending. Read: 0 = interrupt1 is not pending 1 = interrupt1 is pending. Reset type: CM.SYSRESETn |
0 | CLRPEND0 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 0 state to not pending. Read: 0 = interrupt0 is not pending 1 = interrupt0 is pending. Reset type: CM.SYSRESETn |
NVIC_ICPR1 is shown in Figure 41-121 and described in Table 41-132.
Return to the Summary Table.
NVIC Interrupt Clear Pending Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLRPEND63 | CLRPEND62 | CLRPEND61 | CLRPEND60 | CLRPEND59 | CLRPEND58 | CLRPEND57 | CLRPEND56 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLRPEND55 | CLRPEND54 | CLRPEND53 | CLRPEND52 | CLRPEND51 | CLRPEND50 | CLRPEND49 | CLRPEND48 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLRPEND47 | CLRPEND46 | CLRPEND45 | CLRPEND44 | CLRPEND43 | CLRPEND42 | CLRPEND41 | CLRPEND40 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND39 | CLRPEND38 | CLRPEND37 | CLRPEND36 | CLRPEND35 | CLRPEND34 | CLRPEND33 | CLRPEND32 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLRPEND63 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 63 state to not pending. Read: 0 = interrupt63 is not pending 1 = interrupt63 is pending. Reset type: CM.SYSRESETn |
30 | CLRPEND62 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 62 state to not pending. Read: 0 = interrupt62 is not pending 1 = interrupt62 is pending. Reset type: CM.SYSRESETn |
29 | CLRPEND61 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 61 state to not pending. Read: 0 = interrupt61 is not pending 1 = interrupt61 is pending. Reset type: CM.SYSRESETn |
28 | CLRPEND60 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 60 state to not pending. Read: 0 = interrupt60 is not pending 1 = interrupt60 is pending. Reset type: CM.SYSRESETn |
27 | CLRPEND59 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 59 state to not pending. Read: 0 = interrupt59 is not pending 1 = interrupt59 is pending. Reset type: CM.SYSRESETn |
26 | CLRPEND58 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 58 state to not pending. Read: 0 = interrupt58 is not pending 1 = interrupt58 is pending. Reset type: CM.SYSRESETn |
25 | CLRPEND57 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 57 state to not pending. Read: 0 = interrupt57 is not pending 1 = interrupt57 is pending. Reset type: CM.SYSRESETn |
24 | CLRPEND56 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 56 state to not pending. Read: 0 = interrupt56 is not pending 1 = interrupt56 is pending. Reset type: CM.SYSRESETn |
23 | CLRPEND55 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 55 state to not pending. Read: 0 = interrupt55 is not pending 1 = interrupt55 is pending. Reset type: CM.SYSRESETn |
22 | CLRPEND54 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 54 state to not pending. Read: 0 = interrupt54 is not pending 1 = interrupt54 is pending. Reset type: CM.SYSRESETn |
21 | CLRPEND53 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 53 state to not pending. Read: 0 = interrupt53 is not pending 1 = interrupt53 is pending. Reset type: CM.SYSRESETn |
20 | CLRPEND52 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 52 state to not pending. Read: 0 = interrupt52 is not pending 1 = interrupt52 is pending. Reset type: CM.SYSRESETn |
19 | CLRPEND51 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 51 state to not pending. Read: 0 = interrupt51 is not pending 1 = interrupt51 is pending. Reset type: CM.SYSRESETn |
18 | CLRPEND50 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 50 state to not pending. Read: 0 = interrupt50 is not pending 1 = interrupt50 is pending. Reset type: CM.SYSRESETn |
17 | CLRPEND49 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 49 state to not pending. Read: 0 = interrupt49 is not pending 1 = interrupt49 is pending. Reset type: CM.SYSRESETn |
16 | CLRPEND48 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 48 state to not pending. Read: 0 = interrupt48 is not pending 1 = interrupt48 is pending. Reset type: CM.SYSRESETn |
15 | CLRPEND47 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 47 state to not pending. Read: 0 = interrupt47 is not pending 1 = interrupt47 is pending. Reset type: CM.SYSRESETn |
14 | CLRPEND46 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 46 state to not pending. Read: 0 = interrupt46 is not pending 1 = interrupt46 is pending. Reset type: CM.SYSRESETn |
13 | CLRPEND45 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 45 state to not pending. Read: 0 = interrupt45 is not pending 1 = interrupt45 is pending. Reset type: CM.SYSRESETn |
12 | CLRPEND44 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 44 state to not pending. Read: 0 = interrupt44 is not pending 1 = interrupt44 is pending. Reset type: CM.SYSRESETn |
11 | CLRPEND43 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 43 state to not pending. Read: 0 = interrupt43 is not pending 1 = interrupt43 is pending. Reset type: CM.SYSRESETn |
10 | CLRPEND42 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 42 state to not pending. Read: 0 = interrupt42 is not pending 1 = interrupt42 is pending. Reset type: CM.SYSRESETn |
9 | CLRPEND41 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 41 state to not pending. Read: 0 = interrupt41 is not pending 1 = interrupt41 is pending. Reset type: CM.SYSRESETn |
8 | CLRPEND40 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 40 state to not pending. Read: 0 = interrupt40 is not pending 1 = interrupt40 is pending. Reset type: CM.SYSRESETn |
7 | CLRPEND39 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 39 state to not pending. Read: 0 = interrupt39 is not pending 1 = interrupt39 is pending. Reset type: CM.SYSRESETn |
6 | CLRPEND38 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 38 state to not pending. Read: 0 = interrupt38 is not pending 1 = interrupt38 is pending. Reset type: CM.SYSRESETn |
5 | CLRPEND37 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 37 state to not pending. Read: 0 = interrupt37 is not pending 1 = interrupt37 is pending. Reset type: CM.SYSRESETn |
4 | CLRPEND36 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 36 state to not pending. Read: 0 = interrupt36 is not pending 1 = interrupt36 is pending. Reset type: CM.SYSRESETn |
3 | CLRPEND35 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 35 state to not pending. Read: 0 = interrupt35 is not pending 1 = interrupt35 is pending. Reset type: CM.SYSRESETn |
2 | CLRPEND34 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 34 state to not pending. Read: 0 = interrupt34 is not pending 1 = interrupt34 is pending. Reset type: CM.SYSRESETn |
1 | CLRPEND33 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 33 state to not pending. Read: 0 = interrupt33 is not pending 1 = interrupt33 is pending. Reset type: CM.SYSRESETn |
0 | CLRPEND32 | R/W1S | 0h | Clear interrupt pending bits. Write: =0 = no effect 1 = changes interrupt 32 state to not pending. Read: 0 = interrupt32 is not pending 1 = interrupt32 is pending. Reset type: CM.SYSRESETn |
NVIC_IABR0 is shown in Figure 41-122 and described in Table 41-133.
Return to the Summary Table.
NVIC Interrupt Active Bit Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ACTIVE31 | ACTIVE30 | ACTIVE29 | ACTIVE28 | ACTIVE27 | ACTIVE26 | ACTIVE25 | ACTIVE24 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ACTIVE23 | ACTIVE22 | ACTIVE21 | ACTIVE20 | ACTIVE19 | ACTIVE18 | ACTIVE17 | ACTIVE16 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ACTIVE15 | ACTIVE14 | ACTIVE13 | ACTIVE12 | ACTIVE11 | ACTIVE10 | ACTIVE9 | ACTIVE8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE7 | ACTIVE6 | ACTIVE5 | ACTIVE4 | ACTIVE3 | ACTIVE2 | ACTIVE1 | ACTIVE0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ACTIVE31 | R | 0h | Active interrupt bits. 0 = interrupt31 is not active. 1 = interrupt31 is active. Reset type: CM.SYSRESETn |
30 | ACTIVE30 | R | 0h | Active interrupt bits. 0 = interrupt30 is not active. 1 = interrupt30 is active. Reset type: CM.SYSRESETn |
29 | ACTIVE29 | R | 0h | Active interrupt bits. 0 = interrupt29 is not active. 1 = interrupt29 is active. Reset type: CM.SYSRESETn |
28 | ACTIVE28 | R | 0h | Active interrupt bits. 0 = interrupt28 is not active. 1 = interrupt28 is active. Reset type: CM.SYSRESETn |
27 | ACTIVE27 | R | 0h | Active interrupt bits. 0 = interrupt27 is not active. 1 = interrupt27 is active. Reset type: CM.SYSRESETn |
26 | ACTIVE26 | R | 0h | Active interrupt bits. 0 = interrupt26 is not active. 1 = interrupt26 is active. Reset type: CM.SYSRESETn |
25 | ACTIVE25 | R | 0h | Active interrupt bits. 0 = interrupt25 is not active. 1 = interrupt25 is active. Reset type: CM.SYSRESETn |
24 | ACTIVE24 | R | 0h | Active interrupt bits. 0 = interrupt24 is not active. 1 = interrupt24 is active. Reset type: CM.SYSRESETn |
23 | ACTIVE23 | R | 0h | Active interrupt bits. 0 = interrupt23 is not active. 1 = interrupt23 is active. Reset type: CM.SYSRESETn |
22 | ACTIVE22 | R | 0h | Active interrupt bits. 0 = interrupt22 is not active. 1 = interrupt22 is active. Reset type: CM.SYSRESETn |
21 | ACTIVE21 | R | 0h | Active interrupt bits. 0 = interrupt21 is not active. 1 = interrupt21 is active. Reset type: CM.SYSRESETn |
20 | ACTIVE20 | R | 0h | Active interrupt bits. 0 = interrupt20 is not active. 1 = interrupt20 is active. Reset type: CM.SYSRESETn |
19 | ACTIVE19 | R | 0h | Active interrupt bits. 0 = interrupt19 is not active. 1 = interrupt19 is active. Reset type: CM.SYSRESETn |
18 | ACTIVE18 | R | 0h | Active interrupt bits. 0 = interrupt18 is not active. 1 = interrupt18 is active. Reset type: CM.SYSRESETn |
17 | ACTIVE17 | R | 0h | Active interrupt bits. 0 = interrupt17 is not active. 1 = interrupt17 is active. Reset type: CM.SYSRESETn |
16 | ACTIVE16 | R | 0h | Active interrupt bits. 0 = interrupt16 is not active. 1 = interrupt16 is active. Reset type: CM.SYSRESETn |
15 | ACTIVE15 | R | 0h | Active interrupt bits. 0 = interrupt15 is not active. 1 = interrupt15 is active. Reset type: CM.SYSRESETn |
14 | ACTIVE14 | R | 0h | Active interrupt bits. 0 = interrupt14 is not active. 1 = interrupt14 is active. Reset type: CM.SYSRESETn |
13 | ACTIVE13 | R | 0h | Active interrupt bits. 0 = interrupt13 is not active. 1 = interrupt13 is active. Reset type: CM.SYSRESETn |
12 | ACTIVE12 | R | 0h | Active interrupt bits. 0 = interrupt12 is not active. 1 = interrupt12 is active. Reset type: CM.SYSRESETn |
11 | ACTIVE11 | R | 0h | Active interrupt bits. 0 = interrupt11 is not active. 1 = interrupt11 is active. Reset type: CM.SYSRESETn |
10 | ACTIVE10 | R | 0h | Active interrupt bits. 0 = interrupt10 is not active. 1 = interrupt10 is active. Reset type: CM.SYSRESETn |
9 | ACTIVE9 | R | 0h | Active interrupt bits. 0 = interrupt9 is not active. 1 = interrupt9 is active. Reset type: CM.SYSRESETn |
8 | ACTIVE8 | R | 0h | Active interrupt bits. 0 = interrupt8 is not active. 1 = interrupt8 is active. Reset type: CM.SYSRESETn |
7 | ACTIVE7 | R | 0h | Active interrupt bits. 0 = interrupt7 is not active. 1 = interrupt7 is active. Reset type: CM.SYSRESETn |
6 | ACTIVE6 | R | 0h | Active interrupt bits. 0 = interrupt6 is not active. 1 = interrupt6 is active. Reset type: CM.SYSRESETn |
5 | ACTIVE5 | R | 0h | Active interrupt bits. 0 = interrupt5 is not active. 1 = interrupt5 is active. Reset type: CM.SYSRESETn |
4 | ACTIVE4 | R | 0h | Active interrupt bits. 0 = interrupt4 is not active. 1 = interrupt4 is active. Reset type: CM.SYSRESETn |
3 | ACTIVE3 | R | 0h | Active interrupt bits. 0 = interrupt3 is not active. 1 = interrupt3 is active. Reset type: CM.SYSRESETn |
2 | ACTIVE2 | R | 0h | Active interrupt bits. 0 = interrupt2 is not active. 1 = interrupt2 is active. Reset type: CM.SYSRESETn |
1 | ACTIVE1 | R | 0h | Active interrupt bits. 0 = interrupt1 is not active. 1 = interrupt1 is active. Reset type: CM.SYSRESETn |
0 | ACTIVE0 | R | 0h | Active interrupt bits. 0 = interrupt0 is not active. 1 = interrupt0 is active. Reset type: CM.SYSRESETn |
NVIC_IABR1 is shown in Figure 41-123 and described in Table 41-134.
Return to the Summary Table.
NVIC Interrupt Active Bit Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ACTIVE63 | ACTIVE62 | ACTIVE61 | ACTIVE60 | ACTIVE59 | ACTIVE58 | ACTIVE57 | ACTIVE56 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ACTIVE55 | ACTIVE54 | ACTIVE53 | ACTIVE52 | ACTIVE51 | ACTIVE50 | ACTIVE49 | ACTIVE48 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ACTIVE47 | ACTIVE46 | ACTIVE45 | ACTIVE44 | ACTIVE43 | ACTIVE42 | ACTIVE41 | ACTIVE40 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE39 | ACTIVE38 | ACTIVE37 | ACTIVE36 | ACTIVE35 | ACTIVE34 | ACTIVE33 | ACTIVE32 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ACTIVE63 | R | 0h | Active interrupt bits. 0 = interrupt63 is not active. 1 = interrupt63 is active. Reset type: CM.SYSRESETn |
30 | ACTIVE62 | R | 0h | Active interrupt bits. 0 = interrupt62 is not active. 1 = interrupt62 is active. Reset type: CM.SYSRESETn |
29 | ACTIVE61 | R | 0h | Active interrupt bits. 0 = interrupt61 is not active. 1 = interrupt61 is active. Reset type: CM.SYSRESETn |
28 | ACTIVE60 | R | 0h | Active interrupt bits. 0 = interrupt60 is not active. 1 = interrupt60 is active. Reset type: CM.SYSRESETn |
27 | ACTIVE59 | R | 0h | Active interrupt bits. 0 = interrupt59 is not active. 1 = interrupt59 is active. Reset type: CM.SYSRESETn |
26 | ACTIVE58 | R | 0h | Active interrupt bits. 0 = interrupt58 is not active. 1 = interrupt58 is active. Reset type: CM.SYSRESETn |
25 | ACTIVE57 | R | 0h | Active interrupt bits. 0 = interrupt57 is not active. 1 = interrupt57 is active. Reset type: CM.SYSRESETn |
24 | ACTIVE56 | R | 0h | Active interrupt bits. 0 = interrupt56 is not active. 1 = interrupt56 is active. Reset type: CM.SYSRESETn |
23 | ACTIVE55 | R | 0h | Active interrupt bits. 0 = interrupt55 is not active. 1 = interrupt55 is active. Reset type: CM.SYSRESETn |
22 | ACTIVE54 | R | 0h | Active interrupt bits. 0 = interrupt54 is not active. 1 = interrupt54 is active. Reset type: CM.SYSRESETn |
21 | ACTIVE53 | R | 0h | Active interrupt bits. 0 = interrupt53 is not active. 1 = interrupt53 is active. Reset type: CM.SYSRESETn |
20 | ACTIVE52 | R | 0h | Active interrupt bits. 0 = interrupt52 is not active. 1 = interrupt52 is active. Reset type: CM.SYSRESETn |
19 | ACTIVE51 | R | 0h | Active interrupt bits. 0 = interrupt51 is not active. 1 = interrupt51 is active. Reset type: CM.SYSRESETn |
18 | ACTIVE50 | R | 0h | Active interrupt bits. 0 = interrupt50 is not active. 1 = interrupt50 is active. Reset type: CM.SYSRESETn |
17 | ACTIVE49 | R | 0h | Active interrupt bits. 0 = interrupt49 is not active. 1 = interrupt49 is active. Reset type: CM.SYSRESETn |
16 | ACTIVE48 | R | 0h | Active interrupt bits. 0 = interrupt48 is not active. 1 = interrupt48 is active. Reset type: CM.SYSRESETn |
15 | ACTIVE47 | R | 0h | Active interrupt bits. 0 = interrupt47 is not active. 1 = interrupt47 is active. Reset type: CM.SYSRESETn |
14 | ACTIVE46 | R | 0h | Active interrupt bits. 0 = interrupt46 is not active. 1 = interrupt46 is active. Reset type: CM.SYSRESETn |
13 | ACTIVE45 | R | 0h | Active interrupt bits. 0 = interrupt45 is not active. 1 = interrupt45 is active. Reset type: CM.SYSRESETn |
12 | ACTIVE44 | R | 0h | Active interrupt bits. 0 = interrupt44 is not active. 1 = interrupt44 is active. Reset type: CM.SYSRESETn |
11 | ACTIVE43 | R | 0h | Active interrupt bits. 0 = interrupt43 is not active. 1 = interrupt43 is active. Reset type: CM.SYSRESETn |
10 | ACTIVE42 | R | 0h | Active interrupt bits. 0 = interrupt42 is not active. 1 = interrupt42 is active. Reset type: CM.SYSRESETn |
9 | ACTIVE41 | R | 0h | Active interrupt bits. 0 = interrupt41 is not active. 1 = interrupt41 is active. Reset type: CM.SYSRESETn |
8 | ACTIVE40 | R | 0h | Active interrupt bits. 0 = interrupt40 is not active. 1 = interrupt40 is active. Reset type: CM.SYSRESETn |
7 | ACTIVE39 | R | 0h | Active interrupt bits. 0 = interrupt39 is not active. 1 = interrupt39 is active. Reset type: CM.SYSRESETn |
6 | ACTIVE38 | R | 0h | Active interrupt bits. 0 = interrupt38 is not active. 1 = interrupt38 is active. Reset type: CM.SYSRESETn |
5 | ACTIVE37 | R | 0h | Active interrupt bits. 0 = interrupt37 is not active. 1 = interrupt37 is active. Reset type: CM.SYSRESETn |
4 | ACTIVE36 | R | 0h | Active interrupt bits. 0 = interrupt36 is not active. 1 = interrupt36 is active. Reset type: CM.SYSRESETn |
3 | ACTIVE35 | R | 0h | Active interrupt bits. 0 = interrupt35 is not active. 1 = interrupt35 is active. Reset type: CM.SYSRESETn |
2 | ACTIVE34 | R | 0h | Active interrupt bits. 0 = interrupt34 is not active. 1 = interrupt34 is active. Reset type: CM.SYSRESETn |
1 | ACTIVE33 | R | 0h | Active interrupt bits. 0 = interrupt33 is not active. 1 = interrupt33 is active. Reset type: CM.SYSRESETn |
0 | ACTIVE32 | R | 0h | Active interrupt bits. 0 = interrupt32 is not active. 1 = interrupt32 is active. Reset type: CM.SYSRESETn |
NVIC_IPR0 is shown in Figure 41-124 and described in Table 41-135.
Return to the Summary Table.
NVIC Interrupt Priority Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_3 | RESERVED | PRI_2 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_1 | RESERVED | PRI_0 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_3 | R/W | 0h | Priority of interrupt 3. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_2 | R/W | 0h | Priority of interrupt 2. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_1 | R/W | 0h | Priority of interrupt 1. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_0 | R/W | 0h | Priority of interrupt 0. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR1 is shown in Figure 41-125 and described in Table 41-136.
Return to the Summary Table.
NVIC Interrupt Priority Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_7 | RESERVED | PRI_6 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_5 | RESERVED | PRI_4 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_7 | R/W | 0h | Priority of interrupt 7. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_6 | R/W | 0h | Priority of interrupt 6. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_5 | R/W | 0h | Priority of interrupt 5. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_4 | R/W | 0h | Priority of interrupt 4. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR2 is shown in Figure 41-126 and described in Table 41-137.
Return to the Summary Table.
NVIC Interrupt Priority Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_11 | RESERVED | PRI_10 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_9 | RESERVED | PRI_8 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_11 | R/W | 0h | Priority of interrupt 11. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_10 | R/W | 0h | Priority of interrupt 10. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_9 | R/W | 0h | Priority of interrupt 9. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_8 | R/W | 0h | Priority of interrupt 8. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR3 is shown in Figure 41-127 and described in Table 41-138.
Return to the Summary Table.
NVIC Interrupt Priority Register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_15 | RESERVED | PRI_14 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_13 | RESERVED | PRI_12 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_15 | R/W | 0h | Priority of interrupt 15. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_14 | R/W | 0h | Priority of interrupt 14. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_13 | R/W | 0h | Priority of interrupt 13. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_12 | R/W | 0h | Priority of interrupt 12. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR4 is shown in Figure 41-128 and described in Table 41-139.
Return to the Summary Table.
NVIC Interrupt Priority Register 4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_19 | RESERVED | PRI_18 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_17 | RESERVED | PRI_16 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_19 | R/W | 0h | Priority of interrupt 19. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_18 | R/W | 0h | Priority of interrupt 18. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_17 | R/W | 0h | Priority of interrupt 17. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_16 | R/W | 0h | Priority of interrupt 16. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR5 is shown in Figure 41-129 and described in Table 41-140.
Return to the Summary Table.
NVIC Interrupt Priority Register 5
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_23 | RESERVED | PRI_22 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_21 | RESERVED | PRI_20 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_23 | R/W | 0h | Priority of interrupt 23. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_22 | R/W | 0h | Priority of interrupt 22. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_21 | R/W | 0h | Priority of interrupt 21. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_20 | R/W | 0h | Priority of interrupt 20. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR6 is shown in Figure 41-130 and described in Table 41-141.
Return to the Summary Table.
NVIC Interrupt Priority Register 6
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_27 | RESERVED | PRI_26 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_25 | RESERVED | PRI_24 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_27 | R/W | 0h | Priority of interrupt 27. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_26 | R/W | 0h | Priority of interrupt 26. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_25 | R/W | 0h | Priority of interrupt 25. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_24 | R/W | 0h | Priority of interrupt 24. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR7 is shown in Figure 41-131 and described in Table 41-142.
Return to the Summary Table.
NVIC Interrupt Priority Register 7
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_31 | RESERVED | PRI_30 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_29 | RESERVED | PRI_28 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_31 | R/W | 0h | Priority of interrupt 31. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_30 | R/W | 0h | Priority of interrupt 30. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_29 | R/W | 0h | Priority of interrupt 29. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_28 | R/W | 0h | Priority of interrupt 28. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR8 is shown in Figure 41-132 and described in Table 41-143.
Return to the Summary Table.
NVIC Interrupt Priority Register 8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_35 | RESERVED | PRI_34 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_33 | RESERVED | PRI_32 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_35 | R/W | 0h | Priority of interrupt 35. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_34 | R/W | 0h | Priority of interrupt 34. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_33 | R/W | 0h | Priority of interrupt 33. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_32 | R/W | 0h | Priority of interrupt 32. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR9 is shown in Figure 41-133 and described in Table 41-144.
Return to the Summary Table.
NVIC Interrupt Priority Register 9
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_39 | RESERVED | PRI_38 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_37 | RESERVED | PRI_36 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_39 | R/W | 0h | Priority of interrupt 39. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_38 | R/W | 0h | Priority of interrupt 38. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_37 | R/W | 0h | Priority of interrupt 37. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_36 | R/W | 0h | Priority of interrupt 36. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR10 is shown in Figure 41-134 and described in Table 41-145.
Return to the Summary Table.
NVIC Interrupt Priority Register 10
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_43 | RESERVED | PRI_42 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_41 | RESERVED | PRI_40 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_43 | R/W | 0h | Priority of interrupt 43. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_42 | R/W | 0h | Priority of interrupt 42. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_41 | R/W | 0h | Priority of interrupt 41. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_40 | R/W | 0h | Priority of interrupt 40. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR11 is shown in Figure 41-135 and described in Table 41-146.
Return to the Summary Table.
NVIC Interrupt Priority Register 11
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_47 | RESERVED | PRI_46 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_45 | RESERVED | PRI_44 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_47 | R/W | 0h | Priority of interrupt 47. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_46 | R/W | 0h | Priority of interrupt 46. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_45 | R/W | 0h | Priority of interrupt 45. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_44 | R/W | 0h | Priority of interrupt 44. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR12 is shown in Figure 41-136 and described in Table 41-147.
Return to the Summary Table.
NVIC Interrupt Priority Register 12
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_51 | RESERVED | PRI_50 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_49 | RESERVED | PRI_48 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_51 | R/W | 0h | Priority of interrupt 51. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_50 | R/W | 0h | Priority of interrupt 50. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_49 | R/W | 0h | Priority of interrupt 49. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_48 | R/W | 0h | Priority of interrupt 48. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR13 is shown in Figure 41-137 and described in Table 41-148.
Return to the Summary Table.
NVIC Interrupt Priority Register 13
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_55 | RESERVED | PRI_54 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_53 | RESERVED | PRI_52 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_55 | R/W | 0h | Priority of interrupt 55. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_54 | R/W | 0h | Priority of interrupt 54. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_53 | R/W | 0h | Priority of interrupt 53. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_52 | R/W | 0h | Priority of interrupt 52. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR14 is shown in Figure 41-138 and described in Table 41-149.
Return to the Summary Table.
NVIC Interrupt Priority Register 14
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_59 | RESERVED | PRI_58 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_57 | RESERVED | PRI_56 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_59 | R/W | 0h | Priority of interrupt 59. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_58 | R/W | 0h | Priority of interrupt 58. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_57 | R/W | 0h | Priority of interrupt 57. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_56 | R/W | 0h | Priority of interrupt 56. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
NVIC_IPR15 is shown in Figure 41-139 and described in Table 41-150.
Return to the Summary Table.
NVIC Interrupt Priority Register 15
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PRI_63 | RESERVED | PRI_62 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI_61 | RESERVED | PRI_60 | RESERVED | ||||||||||||
R/W-0h | R-0h | R/W-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | PRI_63 | R/W | 0h | Priority of interrupt 63. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
28-24 | RESERVED | R | 0h | Reserved |
23-21 | PRI_62 | R/W | 0h | Priority of interrupt 62. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
20-16 | RESERVED | R | 0h | Reserved |
15-13 | PRI_61 | R/W | 0h | Priority of interrupt 61. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
12-8 | RESERVED | R | 0h | Reserved |
7-5 | PRI_60 | R/W | 0h | Priority of interrupt 60. Each implementation-defined priority field can hold a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. Register priority value fields are eight bits wide, and non-implemented low-order bits read as zero and ignore writes. Reset type: CM.SYSRESETn |
4-0 | RESERVED | R | 0h | Reserved |
STIR is shown in Figure 41-140 and described in Table 41-151.
Return to the Summary Table.
Software Trigger Interrupt Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTID | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8-0 | INTID | R/W | 0h | Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. Reset type: CM.SYSRESETn |