SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 3-248 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses not listed in Table 3-248 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | DxLOCK | Dedicated RAM Config Lock Register | EALLOW | Go |
2h | DxCOMMIT | Dedicated RAM Config Lock Commit Register | EALLOW | Go |
8h | DxACCPROT0 | Dedicated RAM Config Register | EALLOW | Go |
10h | DxTEST | Dedicated RAM TEST Register | EALLOW | Go |
12h | DxINIT | Dedicated RAM Init Register | EALLOW | Go |
14h | DxINITDONE | Dedicated RAM InitDone Status Register | Go | |
16h | DxRAMTEST_LOCK | Lock register to Dx RAM TEST registers | Go | |
20h | LSxLOCK | Local Shared RAM Config Lock Register | EALLOW | Go |
22h | LSxCOMMIT | Local Shared RAM Config Lock Commit Register | EALLOW | Go |
24h | LSxMSEL | Local Shared RAM Master Sel Register | EALLOW | Go |
26h | LSxCLAPGM | Local Shared RAM Prog/Exe control Register | EALLOW | Go |
28h | LSxACCPROT0 | Local Shared RAM Config Register 0 | EALLOW | Go |
2Ah | LSxACCPROT1 | Local Shared RAM Config Register 1 | EALLOW | Go |
30h | LSxTEST | Local Shared RAM TEST Register | EALLOW | Go |
32h | LSxINIT | Local Shared RAM Init Register | EALLOW | Go |
34h | LSxINITDONE | Local Shared RAM InitDone Status Register | Go | |
36h | LSxRAMTEST_LOCK | Lock register to LSx RAM TEST registers | Go | |
40h | GSxLOCK | Global Shared RAM Config Lock Register | EALLOW | Go |
42h | GSxCOMMIT | Global Shared RAM Config Lock Commit Register | EALLOW | Go |
44h | GSxMSEL | Global Shared RAM Master Sel Register | EALLOW | Go |
48h | GSxACCPROT0 | Global Shared RAM Access Protection Register 0 | EALLOW | Go |
4Ah | GSxACCPROT1 | Global Shared RAM Access Protection Register 1 | EALLOW | Go |
4Ch | GSxACCPROT2 | Global Shared RAM Access Protection Register 2 | EALLOW | Go |
4Eh | GSxACCPROT3 | Global Shared RAM Access Protection Register 3 | EALLOW | Go |
50h | GSxTEST | Global Shared RAM TEST Register | EALLOW | Go |
52h | GSxINIT | Global Shared RAM Init Register | EALLOW | Go |
54h | GSxINITDONE | Global Shared RAM InitDone Status Register | Go | |
56h | GSxRAMTEST_LOCK | Lock register to GSx RAM TEST registers | Go | |
60h | MSGxLOCK | Message RAM Config Lock Register | Go | |
62h | MSGxCOMMIT | Message RAM Config Lock Commit Register | Go | |
68h | MSGxACCPROT0 | Message RAM Access Protection Register 0 | EALLOW | Go |
6Ah | MSGxACCPROT1 | Message RAM Access Protection Register 1 | EALLOW | Go |
6Ch | MSGxACCPROT2 | Message RAM Access Protection Register 2 | EALLOW | Go |
70h | MSGxTEST | Message RAM TEST Register | EALLOW | Go |
72h | MSGxINIT | Message RAM Init Register | EALLOW | Go |
74h | MSGxINITDONE | Message RAM InitDone Status Register | Go | |
76h | MSGxRAMTEST_LOCK | Lock register to MSGx RAM TEST registers | Go | |
A0h | ROM_LOCK | ROM Config Lock Register | Go | |
A2h | ROM_TEST | ROM TEST Register | Go | |
A4h | ROM_FORCE_ERROR | ROM Force Error register | Go | |
AAh | PERI_MEM_TEST_LOCK | Peripheral Memory Test Lock Register | Go | |
ACh | PERI_MEM_TEST_CONTROL | Peripheral Memory Test control Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-249 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
DxLOCK is shown in Figure 3-234 and described in Table 3-250.
Return to the Summary Table.
Dedicated RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_D1 | LOCK_D0 | LOCK_M1 | LOCK_M0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | LOCK_D1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for D1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
2 | LOCK_D0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for D0 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
1 | LOCK_M1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
0 | LOCK_M0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
DxCOMMIT is shown in Figure 3-235 and described in Table 3-251.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_D1 | COMMIT_D0 | COMMIT_M1 | COMMIT_M0 | |||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | COMMIT_D1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for D1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_D0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for D0 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_M1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_M0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
DxACCPROT0 is shown in Figure 3-236 and described in Table 3-252.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_D1 | FETCHPROT_D1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_D0 | FETCHPROT_D0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_M1 | FETCHPROT_M1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_M0 | FETCHPROT_M0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_D1 | R/W | 0h | CPU Write Protection For D1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_D1 | R/W | 0h | Fetch Protection For D1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_D0 | R/W | 0h | CPU Write Protection For D0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
16 | FETCHPROT_D0 | R/W | 0h | Fetch Protection For D0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_M1 | R/W | 0h | CPU WR Protection For M1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
8 | FETCHPROT_M1 | R/W | 0h | Fetch Protection For M1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_M0 | R/W | 0h | CPU WR Protection For M0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
0 | FETCHPROT_M0 | R/W | 0h | Fetch Protection For M0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
DxTEST is shown in Figure 3-237 and described in Table 3-253.
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Dedicated RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_D1 | TEST_D0 | TEST_M1 | TEST_M0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7-6 | TEST_D1 | R/W | 0h | Selects the defferent modes for D1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Reset type: SYSRSn |
5-4 | TEST_D0 | R/W | 0h | Selects the defferent modes for D0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Reset type: SYSRSn |
3-2 | TEST_M1 | R/W | 0h | Selects the defferent modes for M1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Reset type: SYSRSn |
1-0 | TEST_M0 | R/W | 0h | Selects the defferent modes for M0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Reset type: SYSRSn |
DxINIT is shown in Figure 3-238 and described in Table 3-254.
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Dedicated RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_D1 | INIT_D0 | INIT_M1 | INIT_M0 | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | INIT_D1 | R-0/W1S | 0h | RAM Initialization control for D1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_D0 | R-0/W1S | 0h | RAM Initialization control for D0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_M1 | R-0/W1S | 0h | RAM Initialization control for M1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_M0 | R-0/W1S | 0h | RAM Initialization control for M0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
DxINITDONE is shown in Figure 3-239 and described in Table 3-255.
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Dedicated RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_D1 | INITDONE_D0 | INITDONE_M1 | INITDONE_M0 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | INITDONE_D1 | R | 0h | RAM Initialization status for D1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
2 | INITDONE_D0 | R | 0h | RAM Initialization status for D0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
1 | INITDONE_M1 | R | 0h | RAM Initialization status for M1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
0 | INITDONE_M0 | R | 0h | RAM Initialization status for M0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
DxRAMTEST_LOCK is shown in Figure 3-240 and described in Table 3-256.
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Lock register to Dx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | D1 | D0 | M1 | M0 | |||||||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-4 | RESERVED | R | 0h | Reserved |
3 | D1 | R/W | 0h | 0: Allows writes to DxTEST.TEST_D1 field. 1: Blocks writes to DxTEST.TEST_D1 field Reset type: SYSRSn |
2 | D0 | R/W | 0h | 0: Allows writes to DxTEST.TEST_D0 field. 1: Blocks writes to DxTEST.TEST_D0 field Reset type: SYSRSn |
1 | M1 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M1 field. 1: Blocks writes to DxTEST.TEST_M1 field Reset type: SYSRSn |
0 | M0 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M0 field. 1: Blocks writes to DxTEST.TEST_M0 field Reset type: SYSRSn |
LSxLOCK is shown in Figure 3-241 and described in Table 3-257.
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Local Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK_LS7 | LOCK_LS6 | LOCK_LS5 | LOCK_LS4 | LOCK_LS3 | LOCK_LS2 | LOCK_LS1 | LOCK_LS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | LOCK_LS7 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and register fields test for LS7 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
6 | LOCK_LS6 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS6 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
5 | LOCK_LS5 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS5 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
4 | LOCK_LS4 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS4 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
3 | LOCK_LS3 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS3 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
2 | LOCK_LS2 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS2 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
1 | LOCK_LS1 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS1 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
0 | LOCK_LS0 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS0 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are blocked. Reset type: SYSRSn |
LSxCOMMIT is shown in Figure 3-242 and described in Table 3-258.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMMIT_LS7 | COMMIT_LS6 | COMMIT_LS5 | COMMIT_LS4 | COMMIT_LS3 | COMMIT_LS2 | COMMIT_LS1 | COMMIT_LS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | COMMIT_LS7 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS7 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
6 | COMMIT_LS6 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS6 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
5 | COMMIT_LS5 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS5 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
4 | COMMIT_LS4 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS4 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
3 | COMMIT_LS3 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS3 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_LS2 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS2 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_LS1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS1 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_LS0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS0 RAM: 0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are permanently blocked. Reset type: SYSRSn |
LSxMSEL is shown in Figure 3-243 and described in Table 3-259.
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Local Shared RAM Master Sel Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSEL_LS7 | MSEL_LS6 | MSEL_LS5 | MSEL_LS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSEL_LS3 | MSEL_LS2 | MSEL_LS1 | MSEL_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-14 | MSEL_LS7 | R/W | 0h | Master Select for LS7 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
13-12 | MSEL_LS6 | R/W | 0h | Master Select for LS6 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
11-10 | MSEL_LS5 | R/W | 0h | Master Select for LS5 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
9-8 | MSEL_LS4 | R/W | 0h | Master Select for LS4 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
7-6 | MSEL_LS3 | R/W | 0h | Master Select for LS3 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
5-4 | MSEL_LS2 | R/W | 0h | Master Select for LS2 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
3-2 | MSEL_LS1 | R/W | 0h | Master Select for LS1 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
1-0 | MSEL_LS0 | R/W | 0h | Master Select for LS0 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
LSxCLAPGM is shown in Figure 3-244 and described in Table 3-260.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAPGM_LS7 | CLAPGM_LS6 | CLAPGM_LS5 | CLAPGM_LS4 | CLAPGM_LS3 | CLAPGM_LS2 | CLAPGM_LS1 | CLAPGM_LS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | CLAPGM_LS7 | R/W | 0h | Selects LS7 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
6 | CLAPGM_LS6 | R/W | 0h | Selects LS6 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
5 | CLAPGM_LS5 | R/W | 0h | Selects LS5 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
4 | CLAPGM_LS4 | R/W | 0h | Selects LS4 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
3 | CLAPGM_LS3 | R/W | 0h | Selects LS3 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
2 | CLAPGM_LS2 | R/W | 0h | Selects LS2 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
1 | CLAPGM_LS1 | R/W | 0h | Selects LS1 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
0 | CLAPGM_LS0 | R/W | 0h | Selects LS0 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
LSxACCPROT0 is shown in Figure 3-245 and described in Table 3-261.
Return to the Summary Table.
Local Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_LS3 | FETCHPROT_LS3 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_LS2 | FETCHPROT_LS2 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS1 | FETCHPROT_LS1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS0 | FETCHPROT_LS0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_LS3 | R/W | 0h | CPU WR Protection For LS3 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_LS3 | R/W | 0h | Fetch Protection For LS3 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_LS2 | R/W | 0h | CPU WR Protection For LS2 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_LS2 | R/W | 0h | Fetch Protection For LS2 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS1 | R/W | 0h | CPU WR Protection For LS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS1 | R/W | 0h | Fetch Protection For LS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS0 | R/W | 0h | CPU WR Protection For LS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS0 | R/W | 0h | Fetch Protection For LS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxACCPROT1 is shown in Figure 3-246 and described in Table 3-262.
Return to the Summary Table.
Local Shared RAM Config Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_LS7 | FETCHPROT_LS7 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_LS6 | FETCHPROT_LS6 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS5 | FETCHPROT_LS5 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS4 | FETCHPROT_LS4 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_LS7 | R/W | 0h | CPU WR Protection For LS7 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_LS7 | R/W | 0h | Fetch Protection For LS7 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_LS6 | R/W | 0h | CPU WR Protection For LS6 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_LS6 | R/W | 0h | Fetch Protection For LS6 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS5 | R/W | 0h | CPU WR Protection For LS5 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS5 | R/W | 0h | Fetch Protection For LS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS4 | R/W | 0h | CPU WR Protection For LS4 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS4 | R/W | 0h | Fetch Protection For LS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxTEST is shown in Figure 3-247 and described in Table 3-263.
Return to the Summary Table.
Local Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_LS7 | TEST_LS6 | TEST_LS5 | TEST_LS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_LS3 | TEST_LS2 | TEST_LS1 | TEST_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-14 | TEST_LS7 | R/W | 0h | Selects the defferent modes for LS7 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
13-12 | TEST_LS6 | R/W | 0h | Selects the defferent modes for LS6 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
11-10 | TEST_LS5 | R/W | 0h | Selects the defferent modes for LS5 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
9-8 | TEST_LS4 | R/W | 0h | Selects the defferent modes for LS4 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
7-6 | TEST_LS3 | R/W | 0h | Selects the defferent modes for LS3 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
5-4 | TEST_LS2 | R/W | 0h | Selects the defferent modes for LS2 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
3-2 | TEST_LS1 | R/W | 0h | Selects the defferent modes for LS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
1-0 | TEST_LS0 | R/W | 0h | Selects the defferent modes for LS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ecc bits. 10: Writes are allowed to ecc bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
LSxINIT is shown in Figure 3-248 and described in Table 3-264.
Return to the Summary Table.
Local Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INIT_LS7 | INIT_LS6 | INIT_LS5 | INIT_LS4 | INIT_LS3 | INIT_LS2 | INIT_LS1 | INIT_LS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | INIT_LS7 | R-0/W1S | 0h | RAM Initialization control for LS7 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INIT_LS6 | R-0/W1S | 0h | RAM Initialization control for LS6 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_LS5 | R-0/W1S | 0h | RAM Initialization control for LS5 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | INIT_LS4 | R-0/W1S | 0h | RAM Initialization control for LS4 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | INIT_LS3 | R-0/W1S | 0h | RAM Initialization control for LS3 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_LS2 | R-0/W1S | 0h | RAM Initialization control for LS2 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_LS1 | R-0/W1S | 0h | RAM Initialization control for LS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_LS0 | R-0/W1S | 0h | RAM Initialization control for LS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
LSxINITDONE is shown in Figure 3-249 and described in Table 3-265.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITDONE_LS7 | INITDONE_LS6 | INITDONE_LS5 | INITDONE_LS4 | INITDONE_LS3 | INITDONE_LS2 | INITDONE_LS1 | INITDONE_LS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | INITDONE_LS7 | R | 0h | RAM Initialization status for LS7 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
6 | INITDONE_LS6 | R | 0h | RAM Initialization status for LS6 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
5 | INITDONE_LS5 | R | 0h | RAM Initialization status for LS5 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | INITDONE_LS4 | R | 0h | RAM Initialization status for LS4 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
3 | INITDONE_LS3 | R | 0h | RAM Initialization status for LS3 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
2 | INITDONE_LS2 | R | 0h | RAM Initialization status for LS2 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_LS1 | R | 0h | RAM Initialization status for LS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_LS0 | R | 0h | RAM Initialization status for LS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
LSxRAMTEST_LOCK is shown in Figure 3-250 and described in Table 3-266.
Return to the Summary Table.
Lock register to LSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LS7 | LS6 | LS5 | LS4 | LS3 | LS2 | LS1 | LS0 | |||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7 | LS7 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS7 field. 1: Blocks writes to LSxTEST.TEST_LS7 field. Reset type: SYSRSn |
6 | LS6 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS6 field. 1: Blocks writes to LSxTEST.TEST_LS6 field. Reset type: SYSRSn |
5 | LS5 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS5 field. 1: Blocks writes to LSxTEST.TEST_LS5 field. Reset type: SYSRSn |
4 | LS4 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS4 field. 1: Blocks writes to LSxTEST.TEST_LS4 field. Reset type: SYSRSn |
3 | LS3 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS3 field. 1: Blocks writes to LSxTEST.TEST_LS3 field. Reset type: SYSRSn |
2 | LS2 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS2 field. 1: Blocks writes to LSxTEST.TEST_LS2 field. Reset type: SYSRSn |
1 | LS1 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS1 field. 1: Blocks writes to LSxTEST.TEST_LS1 field. Reset type: SYSRSn |
0 | LS0 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS0 field. 1: Blocks writes to LSxTEST.TEST_LS0 field. Reset type: SYSRSn |
GSxLOCK is shown in Figure 3-251 and described in Table 3-267.
Return to the Summary Table.
Global Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK_GS15 | LOCK_GS14 | LOCK_GS13 | LOCK_GS12 | LOCK_GS11 | LOCK_GS10 | LOCK_GS9 | LOCK_GS8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK_GS7 | LOCK_GS6 | LOCK_GS5 | LOCK_GS4 | LOCK_GS3 | LOCK_GS2 | LOCK_GS1 | LOCK_GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | LOCK_GS15 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS15 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
14 | LOCK_GS14 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS14 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
13 | LOCK_GS13 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS13 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
12 | LOCK_GS12 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS12 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
11 | LOCK_GS11 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS11 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
10 | LOCK_GS10 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS10 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
9 | LOCK_GS9 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS9 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
8 | LOCK_GS8 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS8 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
7 | LOCK_GS7 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS7 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
6 | LOCK_GS6 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS6 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
5 | LOCK_GS5 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS5 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
4 | LOCK_GS4 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS4 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
3 | LOCK_GS3 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS3 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
2 | LOCK_GS2 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS2 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
1 | LOCK_GS1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
0 | LOCK_GS0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS0 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
GSxCOMMIT is shown in Figure 3-252 and described in Table 3-268.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COMMIT_GS15 | COMMIT_GS14 | COMMIT_GS13 | COMMIT_GS12 | COMMIT_GS11 | COMMIT_GS10 | COMMIT_GS9 | COMMIT_GS8 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMMIT_GS7 | COMMIT_GS6 | COMMIT_GS5 | COMMIT_GS4 | COMMIT_GS3 | COMMIT_GS2 | COMMIT_GS1 | COMMIT_GS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | COMMIT_GS15 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS15 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
14 | COMMIT_GS14 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS14 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
13 | COMMIT_GS13 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS13 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
12 | COMMIT_GS12 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS12 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
11 | COMMIT_GS11 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS11 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
10 | COMMIT_GS10 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS10 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
9 | COMMIT_GS9 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS9 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
8 | COMMIT_GS8 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS8 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
7 | COMMIT_GS7 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS7 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
6 | COMMIT_GS6 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS6 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
5 | COMMIT_GS5 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS5 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
4 | COMMIT_GS4 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS4 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
3 | COMMIT_GS3 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS3 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_GS2 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS2 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_GS1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_GS0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS0 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
GSxMSEL is shown in Figure 3-253 and described in Table 3-269.
Return to the Summary Table.
Global Shared RAM Master Sel Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSEL_GS15 | MSEL_GS14 | MSEL_GS13 | MSEL_GS12 | MSEL_GS11 | MSEL_GS10 | MSEL_GS9 | MSEL_GS8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSEL_GS7 | MSEL_GS6 | MSEL_GS5 | MSEL_GS4 | MSEL_GS3 | MSEL_GS2 | MSEL_GS1 | MSEL_GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | MSEL_GS15 | R/W | 0h | Master Select for GS15 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
14 | MSEL_GS14 | R/W | 0h | Master Select for GS14 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
13 | MSEL_GS13 | R/W | 0h | Master Select for GS13 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
12 | MSEL_GS12 | R/W | 0h | Master Select for GS12 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
11 | MSEL_GS11 | R/W | 0h | Master Select for GS11 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
10 | MSEL_GS10 | R/W | 0h | Master Select for GS10 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
9 | MSEL_GS9 | R/W | 0h | Master Select for GS9 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
8 | MSEL_GS8 | R/W | 0h | Master Select for GS8 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
7 | MSEL_GS7 | R/W | 0h | Master Select for GS7 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
6 | MSEL_GS6 | R/W | 0h | Master Select for GS6 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
5 | MSEL_GS5 | R/W | 0h | Master Select for GS5 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
4 | MSEL_GS4 | R/W | 0h | Master Select for GS4 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
3 | MSEL_GS3 | R/W | 0h | Master Select for GS3 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
2 | MSEL_GS2 | R/W | 0h | Master Select for GS2 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
1 | MSEL_GS1 | R/W | 0h | Master Select for GS1 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
0 | MSEL_GS0 | R/W | 0h | Master Select for GS0 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
GSxACCPROT0 is shown in Figure 3-254 and described in Table 3-270.
Return to the Summary Table.
Global Shared RAM Access Protection Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS3 | CPUWRPROT_GS3 | FETCHPROT_GS3 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS2 | CPUWRPROT_GS2 | FETCHPROT_GS2 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS1 | CPUWRPROT_GS1 | FETCHPROT_GS1 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS0 | CPUWRPROT_GS0 | FETCHPROT_GS0 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS3 | R/W | 0h | DMA WR Protection For GS3 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS3 | R/W | 0h | CPU WR Protection For GS3 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS3 | R/W | 0h | Fetch Protection For GS3 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS2 | R/W | 0h | DMA WR Protection For GS2 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS2 | R/W | 0h | CPU WR Protection For GS2 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS2 | R/W | 0h | Fetch Protection For GS2 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS1 | R/W | 0h | DMA WR Protection For GS1 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS1 | R/W | 0h | CPU WR Protection For GS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS1 | R/W | 0h | Fetch Protection For GS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS0 | R/W | 0h | DMA WR Protection For GS0 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS0 | R/W | 0h | CPU WR Protection For GS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS0 | R/W | 0h | Fetch Protection For GS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxACCPROT1 is shown in Figure 3-255 and described in Table 3-271.
Return to the Summary Table.
Global Shared RAM Access Protection Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS7 | CPUWRPROT_GS7 | FETCHPROT_GS7 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS6 | CPUWRPROT_GS6 | FETCHPROT_GS6 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS5 | CPUWRPROT_GS5 | FETCHPROT_GS5 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS4 | CPUWRPROT_GS4 | FETCHPROT_GS4 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS7 | R/W | 0h | DMA WR Protection For GS7 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS7 | R/W | 0h | CPU WR Protection For GS7 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS7 | R/W | 0h | Fetch Protection For GS7 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS6 | R/W | 0h | DMA WR Protection For GS6 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS6 | R/W | 0h | CPU WR Protection For GS6 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS6 | R/W | 0h | Fetch Protection For GS6 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS5 | R/W | 0h | DMA WR Protection For GS5 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS5 | R/W | 0h | CPU WR Protection For GS5 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS5 | R/W | 0h | Fetch Protection For GS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS4 | R/W | 0h | DMA WR Protection For GS4 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS4 | R/W | 0h | CPU WR Protection For GS4 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS4 | R/W | 0h | Fetch Protection For GS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxACCPROT2 is shown in Figure 3-256 and described in Table 3-272.
Return to the Summary Table.
Global Shared RAM Access Protection Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS11 | CPUWRPROT_GS11 | FETCHPROT_GS11 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS10 | CPUWRPROT_GS10 | FETCHPROT_GS10 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS9 | CPUWRPROT_GS9 | FETCHPROT_GS9 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS8 | CPUWRPROT_GS8 | FETCHPROT_GS8 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS11 | R/W | 0h | DMA WR Protection For GS11 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS11 | R/W | 0h | CPU WR Protection For GS11 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS11 | R/W | 0h | Fetch Protection For GS11 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS10 | R/W | 0h | DMA WR Protection For GS10 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS10 | R/W | 0h | CPU WR Protection For GS10 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS10 | R/W | 0h | Fetch Protection For GS10 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS9 | R/W | 0h | DMA WR Protection For GS9 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS9 | R/W | 0h | CPU WR Protection For GS9 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS9 | R/W | 0h | Fetch Protection For GS9 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS8 | R/W | 0h | DMA WR Protection For GS8 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS8 | R/W | 0h | CPU WR Protection For GS8 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS8 | R/W | 0h | Fetch Protection For GS8 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxACCPROT3 is shown in Figure 3-257 and described in Table 3-273.
Return to the Summary Table.
Global Shared RAM Access Protection Register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS15 | CPUWRPROT_GS15 | FETCHPROT_GS15 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS14 | CPUWRPROT_GS14 | FETCHPROT_GS14 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS13 | CPUWRPROT_GS13 | FETCHPROT_GS13 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS12 | CPUWRPROT_GS12 | FETCHPROT_GS12 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS15 | R/W | 0h | DMA WR Protection For GS15 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS15 | R/W | 0h | CPU WR Protection For GS15 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS15 | R/W | 0h | Fetch Protection For GS15 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS14 | R/W | 0h | DMA WR Protection For GS14 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS14 | R/W | 0h | CPU WR Protection For GS14 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS14 | R/W | 0h | Fetch Protection For GS14 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS13 | R/W | 0h | DMA WR Protection For GS13 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS13 | R/W | 0h | CPU WR Protection For GS13 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS13 | R/W | 0h | Fetch Protection For GS13 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS12 | R/W | 0h | DMA WR Protection For GS12 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS12 | R/W | 0h | CPU WR Protection For GS12 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS12 | R/W | 0h | Fetch Protection For GS12 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxTEST is shown in Figure 3-258 and described in Table 3-274.
Return to the Summary Table.
Global Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TEST_GS15 | TEST_GS14 | TEST_GS13 | TEST_GS12 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TEST_GS11 | TEST_GS10 | TEST_GS9 | TEST_GS8 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_GS7 | TEST_GS6 | TEST_GS5 | TEST_GS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_GS3 | TEST_GS2 | TEST_GS1 | TEST_GS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | TEST_GS15 | R/W | 0h | Selects the defferent modes for GS15 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
29-28 | TEST_GS14 | R/W | 0h | Selects the defferent modes for GS14 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
27-26 | TEST_GS13 | R/W | 0h | Selects the defferent modes for GS13 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
25-24 | TEST_GS12 | R/W | 0h | Selects the defferent modes for GS12 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
23-22 | TEST_GS11 | R/W | 0h | Selects the defferent modes for GS11 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
21-20 | TEST_GS10 | R/W | 0h | Selects the defferent modes for GS10 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
19-18 | TEST_GS9 | R/W | 0h | Selects the defferent modes for GS9 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
17-16 | TEST_GS8 | R/W | 0h | Selects the defferent modes for GS8 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
15-14 | TEST_GS7 | R/W | 0h | Selects the defferent modes for GS7 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
13-12 | TEST_GS6 | R/W | 0h | Selects the defferent modes for GS6 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
11-10 | TEST_GS5 | R/W | 0h | Selects the defferent modes for GS5 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
9-8 | TEST_GS4 | R/W | 0h | Selects the defferent modes for GS4 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
7-6 | TEST_GS3 | R/W | 0h | Selects the defferent modes for GS3 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
5-4 | TEST_GS2 | R/W | 0h | Selects the defferent modes for GS2 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
3-2 | TEST_GS1 | R/W | 0h | Selects the defferent modes for GS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_GS0 | R/W | 0h | Selects the defferent modes for GS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
GSxINIT is shown in Figure 3-259 and described in Table 3-275.
Return to the Summary Table.
Global Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INIT_GS15 | INIT_GS14 | INIT_GS13 | INIT_GS12 | INIT_GS11 | INIT_GS10 | INIT_GS9 | INIT_GS8 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INIT_GS7 | INIT_GS6 | INIT_GS5 | INIT_GS4 | INIT_GS3 | INIT_GS2 | INIT_GS1 | INIT_GS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | INIT_GS15 | R-0/W1S | 0h | RAM Initialization control for GS15 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
14 | INIT_GS14 | R-0/W1S | 0h | RAM Initialization control for GS14 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
13 | INIT_GS13 | R-0/W1S | 0h | RAM Initialization control for GS13 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
12 | INIT_GS12 | R-0/W1S | 0h | RAM Initialization control for GS12 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
11 | INIT_GS11 | R-0/W1S | 0h | RAM Initialization control for GS11 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
10 | INIT_GS10 | R-0/W1S | 0h | RAM Initialization control for GS10 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
9 | INIT_GS9 | R-0/W1S | 0h | RAM Initialization control for GS9 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
8 | INIT_GS8 | R-0/W1S | 0h | RAM Initialization control for GS8 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
7 | INIT_GS7 | R-0/W1S | 0h | RAM Initialization control for GS7 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INIT_GS6 | R-0/W1S | 0h | RAM Initialization control for GS6 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_GS5 | R-0/W1S | 0h | RAM Initialization control for GS5 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | INIT_GS4 | R-0/W1S | 0h | RAM Initialization control for GS4 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | INIT_GS3 | R-0/W1S | 0h | RAM Initialization control for GS3 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_GS2 | R-0/W1S | 0h | RAM Initialization control for GS2 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_GS1 | R-0/W1S | 0h | RAM Initialization control for GS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_GS0 | R-0/W1S | 0h | RAM Initialization control for GS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
GSxINITDONE is shown in Figure 3-260 and described in Table 3-276.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INITDONE_GS15 | INITDONE_GS14 | INITDONE_GS13 | INITDONE_GS12 | INITDONE_GS11 | INITDONE_GS10 | INITDONE_GS9 | INITDONE_GS8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITDONE_GS7 | INITDONE_GS6 | INITDONE_GS5 | INITDONE_GS4 | INITDONE_GS3 | INITDONE_GS2 | INITDONE_GS1 | INITDONE_GS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | INITDONE_GS15 | R | 0h | RAM Initialization status for GS15 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
14 | INITDONE_GS14 | R | 0h | RAM Initialization status for GS14 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
13 | INITDONE_GS13 | R | 0h | RAM Initialization status for GS13 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
12 | INITDONE_GS12 | R | 0h | RAM Initialization status for GS12 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
11 | INITDONE_GS11 | R | 0h | RAM Initialization status for GS11 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
10 | INITDONE_GS10 | R | 0h | RAM Initialization status for GS10 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
9 | INITDONE_GS9 | R | 0h | RAM Initialization status for GS9 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
8 | INITDONE_GS8 | R | 0h | RAM Initialization status for GS8 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
7 | INITDONE_GS7 | R | 0h | RAM Initialization status for GS7 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
6 | INITDONE_GS6 | R | 0h | RAM Initialization status for GS6 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
5 | INITDONE_GS5 | R | 0h | RAM Initialization status for GS5 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | INITDONE_GS4 | R | 0h | RAM Initialization status for GS4 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
3 | INITDONE_GS3 | R | 0h | RAM Initialization status for GS3 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
2 | INITDONE_GS2 | R | 0h | RAM Initialization status for GS2 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_GS1 | R | 0h | RAM Initialization status for GS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_GS0 | R | 0h | RAM Initialization status for GS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
GSxRAMTEST_LOCK is shown in Figure 3-261 and described in Table 3-277.
Return to the Summary Table.
Lock register to GSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GS15 | GS14 | GS13 | GS12 | GS11 | GS10 | GS9 | GS8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GS7 | GS6 | GS5 | GS4 | GS3 | GS2 | GS1 | GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15 | GS15 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS15 field. 1: Blocks writes to GSxTEST.TEST_GS15 field. Reset type: SYSRSn |
14 | GS14 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS14 field. 1: Blocks writes to GSxTEST.TEST_GS14 field. Reset type: SYSRSn |
13 | GS13 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS13 field. 1: Blocks writes to GSxTEST.TEST_GS13 field. Reset type: SYSRSn |
12 | GS12 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS12 field. 1: Blocks writes to GSxTEST.TEST_GS12 field. Reset type: SYSRSn |
11 | GS11 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS11 field. 1: Blocks writes to GSxTEST.TEST_GS11 field. Reset type: SYSRSn |
10 | GS10 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS10 field. 1: Blocks writes to GSxTEST.TEST_GS10 field. Reset type: SYSRSn |
9 | GS9 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS9 field. 1: Blocks writes to GSxTEST.TEST_GS9 field. Reset type: SYSRSn |
8 | GS8 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS8 field. 1: Blocks writes to GSxTEST.TEST_GS8 field. Reset type: SYSRSn |
7 | GS7 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS7 field. 1: Blocks writes to GSxTEST.TEST_GS7 field. Reset type: SYSRSn |
6 | GS6 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS6 field. 1: Blocks writes to GSxTEST.TEST_GS6 field. Reset type: SYSRSn |
5 | GS5 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS5 field. 1: Blocks writes to GSxTEST.TEST_GS5 field. Reset type: SYSRSn |
4 | GS4 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS4 field. 1: Blocks writes to GSxTEST.TEST_GS4 field. Reset type: SYSRSn |
3 | GS3 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS3 field. 1: Blocks writes to GSxTEST.TEST_GS3 field. Reset type: SYSRSn |
2 | GS2 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS2 field. 1: Blocks writes to GSxTEST.TEST_GS2 field. Reset type: SYSRSn |
1 | GS1 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS1 field. 1: Blocks writes to GSxTEST.TEST_GS1 field. Reset type: SYSRSn |
0 | GS0 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS0 field. 1: Blocks writes to GSxTEST.TEST_GS0 field. Reset type: SYSRSn |
MSGxLOCK is shown in Figure 3-262 and described in Table 3-278.
Return to the Summary Table.
Message RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LOCK_DMATOCLA2 | LOCK_CLA2TODMA | LOCK_CPUTOCM_MSGRAM1 | LOCK_CPUTOCM_MSGRAM0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK_CPUTOCPU_MSGRAM1 | LOCK_DMATOCLA1 | LOCK_CLA1TODMA | RESERVED | RESERVED | LOCK_CLA1TOCPU | LOCK_CPUTOCLA1 | LOCK_CPUTOCPU_MSGRAM0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | LOCK_DMATOCLA2 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for DMA2CLA MSG RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
10 | LOCK_CLA2TODMA | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CLA2DMA MSG RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
9 | LOCK_CPUTOCM_MSGRAM1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CPU2CM MSG RAM1: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
8 | LOCK_CPUTOCM_MSGRAM0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CPU2CM MSG RAM0: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
7 | LOCK_CPUTOCPU_MSGRAM1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CPU2CPU MSG RAM1: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
6 | LOCK_DMATOCLA1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test for DMATOCLA1 RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
5 | LOCK_CLA1TODMA | R/W | 0h | Locks the write to access protection, master select, initialization control and test for CLA1TODMA RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | LOCK_CLA1TOCPU | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CLA1TOCPU RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
1 | LOCK_CPUTOCLA1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CPUTOCLA1 RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
0 | LOCK_CPUTOCPU_MSGRAM0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for CPU2CPU MSG RAM0: 0: Write to ACCPROT, INIT fields are allowed. 1: Write to ACCPROT, INIT fields are blocked. Reset type: SYSRSn |
MSGxCOMMIT is shown in Figure 3-263 and described in Table 3-279.
Return to the Summary Table.
Message RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COMMIT_DMATOCLA_MSGRAM1 | COMMIT_CLATODMA_MSGRAM0 | COMMIT_CPUTOCM_MSGRAM1 | COMMIT_CPUTOCM_MSGRAM0 | |||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMMIT_CPUTOCPU_MSGRAM1 | COMMIT_DMATOCLA1 | COMMIT_CLA1TODMA | RESERVED | RESERVED | COMMIT_CLA1TOCPU | COMMIT_CPUTOCLA1 | COMMIT_CPUTOCPU_MSGRAM0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | COMMIT_DMATOCLA_MSGRAM1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for DMA2CLA MSG RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
10 | COMMIT_CLATODMA_MSGRAM0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for CLA2DMA MSG RAM: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
9 | COMMIT_CPUTOCM_MSGRAM1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for CPU2CM MSG RAM1: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
8 | COMMIT_CPUTOCM_MSGRAM0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for CPU2CM MSG RAM0: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
7 | COMMIT_CPUTOCPU_MSGRAM1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for CPU2CPU MSG RAM1: 0: Write to INIT fields are allowed. 1: Write to INIT fields are blocked. Reset type: SYSRSn |
6 | COMMIT_DMATOCLA1 | R/WSonce | 0h | 0: Write to, INIT fields are allowed. 1: Write to, INIT fields are blocked. Reset type: SYSRSn |
5 | COMMIT_CLA1TODMA | R/WSonce | 0h | 0: Write to, INIT fields are allowed. 1: Write to, INIT fields are blocked. Reset type: SYSRSn |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | COMMIT_CLA1TOCPU | R/WSonce | 0h | Locks the write to access protection, master select, initialization control and test register fields for CLA1TOCPU RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
1 | COMMIT_CPUTOCLA1 | R/WSonce | 0h | Locks the write to access protection, master select, initialization control and test register fields for CPUTOCLA1 RAM: 0: Write to ACCPROT, INIT and Mselect fields are allowed. 1: Write to ACCPROT, INIT and Mselect fields are blocked. Reset type: SYSRSn |
0 | COMMIT_CPUTOCPU_MSGRAM0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for D0 RAM: 0: Write to ACCPROT, INIT fields are allowed based on value of lock field in MSGxLOCK register. 1: Write to ACCPROT, INIT are permanently blocked. Reset type: SYSRSn |
MSGxACCPROT0 is shown in Figure 3-264 and described in Table 3-280.
Return to the Summary Table.
Message RAM Access Protection Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_CPUTOCPU_MSGRAM0 | CPUWRPROT_CPUTOCPU_MSGRAM0 | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-19 | RESERVED | R | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_CPUTOCPU_MSGRAM0 | R/W | 0h | DMA WR Protection For CPUTOCPU_MSGRAM0 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_CPUTOCPU_MSGRAM0 | R/W | 0h | CPU WR Protection For CPUTOCPU_MSGRAM0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
MSGxACCPROT1 is shown in Figure 3-265 and described in Table 3-281.
Return to the Summary Table.
Message RAM Access Protection Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_CPUTOCPU_MSGRAM1 | CPUWRPROT_CPUTOCPU_MSGRAM1 | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_CPUTOCPU_MSGRAM1 | R/W | 0h | DMA WR Protection For CPUTOCPU_MSGRAM1 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_CPUTOCPU_MSGRAM1 | R/W | 0h | CPU WR Protection For CPUTOCPU_MSGRAM1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | RESERVED | R/W | 0h | Reserved |
23-19 | RESERVED | R | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7-3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
MSGxACCPROT2 is shown in Figure 3-266 and described in Table 3-282.
Return to the Summary Table.
Message RAM Access Protection Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_CPUTOCM_MSGRAM1 | CPUWRPROT_CPUTOCM_MSGRAM1 | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_CPUTOCM_MSGRAM0 | CPUWRPROT_CPUTOCM_MSGRAM0 | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-19 | RESERVED | R | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_CPUTOCM_MSGRAM1 | R/W | 0h | DMA WR Protection For CPUTOCM_MSGRAM1 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_CPUTOCM_MSGRAM1 | R/W | 0h | CPU WR Protection For CPUTOCM_MSGRAM1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | RESERVED | R/W | 0h | Reserved |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_CPUTOCM_MSGRAM0 | R/W | 0h | DMA WR Protection For CPUTOCM_MSGRAM0 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_CPUTOCM_MSGRAM0 | R/W | 0h | CPU WR Protection For CPUTOCM_MSGRAM0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
MSGxTEST is shown in Figure 3-267 and described in Table 3-283.
Return to the Summary Table.
Message RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | TEST_CPUTOCM_MSGRAM1 | TEST_CPUTOCM_MSGRAM0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_CPUTOCPU_MSGRAM1 | TEST_DMATOCLA1 | TEST_CLA1TODMA | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_CLA1TOCPU | TEST_CPUTOCLA1 | TEST_CPUTOCPU_MSGRAM0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | TEST_CPUTOCM_MSGRAM1 | R/W | 0h | Selects the defferent modes for CPUTOCM MSG RAM1: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
17-16 | TEST_CPUTOCM_MSGRAM0 | R/W | 0h | Selects the defferent modes for CPUTOCM MSG RAM0: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
15-14 | TEST_CPUTOCPU_MSGRAM1 | R/W | 0h | Selects the defferent modes for CPUTOCPU MSG RAM0: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
13-12 | TEST_DMATOCLA1 | R/W | 0h | Selects the defferent modes for DMATOCLA1 MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
11-10 | TEST_CLA1TODMA | R/W | 0h | Selects the defferent modes for CLA1TODMA MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | TEST_CLA1TOCPU | R/W | 0h | Selects the defferent modes for CLA1TOCPU MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
3-2 | TEST_CPUTOCLA1 | R/W | 0h | Selects the defferent modes for CPUTOCLA1 MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_CPUTOCPU_MSGRAM0 | R/W | 0h | Selects the defferent modes for CPUTOCPU MSG RAM0: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/nmi is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
MSGxINIT is shown in Figure 3-268 and described in Table 3-284.
Return to the Summary Table.
Message RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | INIT_CPUTOCM_MSGRAM1 | INIT_CPUTOCM_MSGRAM0 | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INIT_CPUTOCPU_MSGRAM1 | INIT_DMATOCLA1 | INIT_CLA1TODMA | RESERVED | RESERVED | INIT_CLA1TOCPU | INIT_CPUTOCLA1 | INIT_CPUTOCPU_MSGRAM0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | INIT_CPUTOCM_MSGRAM1 | R-0/W1S | 0h | RAM Initialization control for CPUTOCM MSG RAM1: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
8 | INIT_CPUTOCM_MSGRAM0 | R-0/W1S | 0h | RAM Initialization control for CPUTOCM MSG RAM0: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
7 | INIT_CPUTOCPU_MSGRAM1 | R-0/W1S | 0h | RAM Initialization control for CPUTOCPU MSG RAM1: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INIT_DMATOCLA1 | R-0/W1S | 0h | RAM Initialization control for DMATOCLA1 MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_CLA1TODMA | R-0/W1S | 0h | RAM Initialization control for CLA1TODMA MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | INIT_CLA1TOCPU | R-0/W1S | 0h | RAM Initialization control for CLA1TOCPU MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_CPUTOCLA1 | R-0/W1S | 0h | RAM Initialization control for CPUTOCLA1 MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_CPUTOCPU_MSGRAM0 | R-0/W1S | 0h | RAM Initialization control for CPUTOCPU MSG RAM0: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
MSGxINITDONE is shown in Figure 3-269 and described in Table 3-285.
Return to the Summary Table.
Message RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | INITDONE_CPUTOCM_MSGRAM1 | INITDONE_CPUTOCM_MSGRAM0 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITDONE_CPUTOCPU_MSGRAM1 | INITDONE_DMATOCLA1 | INITDONE_CLA1TODMA | RESERVED | RESERVED | INITDONE_CLA1TOCPU | INITDONE_CPUTOCLA1 | INITDONE_CPUTOCPU_MSGRAM0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | INITDONE_CPUTOCM_MSGRAM1 | R | 0h | RAM Initialization status for CPUTOCM MSG RAM1: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
8 | INITDONE_CPUTOCM_MSGRAM0 | R | 0h | RAM Initialization status for CPUTOCM MSG RAM0: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
7 | INITDONE_CPUTOCPU_MSGRAM1 | R | 0h | RAM Initialization status for CPUTOCPU MSG RAM1: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INITDONE_DMATOCLA1 | R | 0h | RAM Initialization status for DMATOCLA1 MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
5 | INITDONE_CLA1TODMA | R | 0h | RAM Initialization status for CLA1TODMA MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | INITDONE_CLA1TOCPU | R | 0h | RAM Initialization status for CLA1TOCPU MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_CPUTOCLA1 | R | 0h | RAM Initialization status for CPUTOCLA1 MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_CPUTOCPU_MSGRAM0 | R | 0h | RAM Initialization status for CPUTOCPU MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
MSGxRAMTEST_LOCK is shown in Figure 3-270 and described in Table 3-286.
Return to the Summary Table.
Lock register to MSGx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMATOCLA2 | CLA2TODMA | CPUTOCM_MSGRAM1 | CPUTOCM_MSGRAM0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPUTOCPU_MSGRAM1 | DMATOCLA1 | CLA1TODMA | CLA2TOCPU | CPUTOCLA2 | CLA1TOCPU | CPUTOCLA1 | CPUTOCPU_MSGRAM0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-12 | RESERVED | R | 0h | Reserved |
11 | DMATOCLA2 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_DMATOCLA2 field. 1: Blocks writes to MSGxTEST.TEST_DMATOCLA2 field. Reset type: SYSRSn |
10 | CLA2TODMA | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CLA2TODMA field. 1: Blocks writes to MSGxTEST.TEST_CLA2TODMA field. Reset type: SYSRSn |
9 | CPUTOCM_MSGRAM1 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCM_MSGRAM1 field. 1: Blocks writes to MSGxTEST.TEST_CPUTOCM_MSGRAM1 field. Reset type: SYSRSn |
8 | CPUTOCM_MSGRAM0 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCM_MSGRAM0 field. 1: Blocks writes to MSGxTEST.TEST_CPUTOCM_MSGRAM0 field. Reset type: SYSRSn |
7 | CPUTOCPU_MSGRAM1 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM1 field. 1: Blocks writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM1 field. Reset type: SYSRSn |
6 | DMATOCLA1 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_DMATOCLA1 field. 1: Blocks writes to MSGxTEST.TEST_DMATOCLA1 field. Reset type: SYSRSn |
5 | CLA1TODMA | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CLA1TODMA field. 1: Blocks writes to MSGxTEST.TEST_CLA1TODMA field. Reset type: SYSRSn |
4 | CLA2TOCPU | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CLA2TOCPU field. 1: Blocks writes to MSGxTEST.TEST_CLA2TOCPU field. Reset type: SYSRSn |
3 | CPUTOCLA2 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCLA2 field. 1: Blocks writes to MSGxTEST.TEST_CPUTOCLA2 field. Reset type: SYSRSn |
2 | CLA1TOCPU | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CLA1TOCPU field. 1: Blocks writes to MSGxTEST.TEST_CLA1TOCPU field. Reset type: SYSRSn |
1 | CPUTOCLA1 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCLA1 field. 1: Blocks writes to MSGxTEST.TEST_CPUTOCLA1 field. Reset type: SYSRSn |
0 | CPUTOCPU_MSGRAM0 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM0 field. 1: Blocks writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM0 field. Reset type: SYSRSn |
ROM_LOCK is shown in Figure 3-271 and described in Table 3-287.
Return to the Summary Table.
ROM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_CLADATAROM | LOCK_SECUREROM | LOCK_BOOTROM | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-3 | RESERVED | R | 0h | Reserved |
2 | LOCK_CLADATAROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of CLADATAROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
1 | LOCK_SECUREROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of SECUREROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
0 | LOCK_BOOTROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of BOOTROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
ROM_TEST is shown in Figure 3-272 and described in Table 3-288.
Return to the Summary Table.
ROM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_CLADATAROM | TEST_SECUREROM | TEST_BOOTROM | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | Reserved |
5-4 | TEST_CLADATAROM | R/W | 0h | Selects the different modes for CLADATAROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
3-2 | TEST_SECUREROM | R/W | 0h | Selects the different modes for SECUREROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
1-0 | TEST_BOOTROM | R/W | 0h | Selects the different modes for BOOTROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
ROM_FORCE_ERROR is shown in Figure 3-273 and described in Table 3-289.
Return to the Summary Table.
ROM Force Error register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FORCE_CLADATAROM_ERROR | FORCE_SECUREROM_ERROR | FORCE_BOOTROM_ERROR | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-3 | RESERVED | R | 0h | Reserved |
2 | FORCE_CLADATAROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
1 | FORCE_SECUREROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
0 | FORCE_BOOTROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
PERI_MEM_TEST_LOCK is shown in Figure 3-274 and described in Table 3-290.
Return to the Summary Table.
Peripheral Memory Test Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_PERI_MEM_TEST_CONTROL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-1 | RESERVED | R | 0h | Reserved |
0 | LOCK_PERI_MEM_TEST_CONTROL | R/W | 0h | Locks write access to register PERI_MEM_TEST_CONTROL 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
PERI_MEM_TEST_CONTROL is shown in Figure 3-275 and described in Table 3-291.
Return to the Summary Table.
Peripheral Memory Test control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EtherCAT_MEM_FORCE_ERROR | EtherCAT_TEST_ENABLE | RESERVED | RESERVED | RESERVED | RESERVED | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | Reserved |
5 | EtherCAT_MEM_FORCE_ERROR | R/W | 0h | Force error bit 0 : No effect 1 : Parity bit going to Parity checker module of EtherCAT is inverted to introduce parity Error Reset type: SYSRSn |
4 | EtherCAT_TEST_ENABLE | R/W | 0h | Selects EtherCAT test mode 0 : EtherCAT test mode disabled, Error on EtherCAT memory read access will generate NMI 1 : EtherCAT test mode enabled, Error on EtherCAT memory read access will NOT generate NMI, used for diagnostics Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |