SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 41-12 lists the memory-mapped registers for the CM_MEMCFG_REGS registers. All register offset addresses not listed in Table 41-12 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CxLOCK | C RAM Config Lock Register | Go | |
4h | CxTEST | C RAM TEST Register | Lock_Protection | Go |
8h | CxINIT | C RAM Init Register | Lock_Protection | Go |
Ch | CxINITDONE | C RAM Initialization Status Register | Go | |
20h | CMMSGxLOCK | CM Messae RAM Config Lock Register | Go | |
24h | CMMSGxTEST | CM Messae RAM TEST Register | Lock_Protection | Go |
28h | CMMSGxINIT | CM Messae RAM Init Register | Lock_Protection | Go |
2Ch | CMMSGxINITDONE | CM Messae RAM Initialization Status Register | Go | |
40h | SxGROUP1_LOCK | Group1 S and E RAM Config Lock Register | Go | |
44h | SxGROUP1_TEST | Group1 S and E RAM TEST Register | Lock_Protection | Go |
48h | SxGROUP1_INIT | Group1 S and E RAM Init Register | Lock_Protection | Go |
4Ch | SxGROUP1_INITDONE | Group1 S and E RAM Initialization Status Register | Go | |
80h | ROM_LOCK | ROM Config Lock Register | Go | |
84h | ROM_TEST | ROM TEST Register | Lock_Protection | Go |
88h | ROM_FORCE_ERROR | ROM Force Error register | Lock_Protection | Go |
A0h | PERI_MEM_TEST_LOCK | Peripheral Memory Test Lock Register | Go | |
A4h | PERI_MEM_TEST_CONTROL | Peripheral Memory Test control Register | Lock_Protection | Go |
Complex bit access types are encoded to fit into small table cells. Table 41-13 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CxLOCK is shown in Figure 41-17 and described in Table 41-14.
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C RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_C1 | LOCK_C0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1 | LOCK_C1 | R/W | 0h | Locks write access to initialization and test control fields of C1 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
0 | LOCK_C0 | R/W | 0h | Locks write access to initialization and test control fields of C0 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
CxTEST is shown in Figure 41-18 and described in Table 41-15.
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C RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_C1 | TEST_C0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3-2 | TEST_C1 | R/W | 0h | Selects the different modes for C1 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
1-0 | TEST_C0 | R/W | 0h | Selects the different modes for C0 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
CxINIT is shown in Figure 41-19 and described in Table 41-16.
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C RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_C1 | INIT_C0 | |||||
R-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1 | INIT_C1 | R-0/W1S | 0h | RAM Initialization control for C1 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
0 | INIT_C0 | R-0/W1S | 0h | RAM Initialization control for C0 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
CxINITDONE is shown in Figure 41-20 and described in Table 41-17.
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C RAM Initialization Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_C1 | INITDONE_C0 | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1 | INITDONE_C1 | R | 0h | RAM Initialization status for C1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
0 | INITDONE_C0 | R | 0h | RAM Initialization status for C0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
CMMSGxLOCK is shown in Figure 41-21 and described in Table 41-18.
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CM Messae RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_CMTOCPU2MSGRAM1 | LOCK_CMTOCPU2MSGRAM0 | LOCK_CMTOCPU1MSGRAM1 | LOCK_CMTOCPU1MSGRAM0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | LOCK_CMTOCPU2MSGRAM1 | R/W | 0h | Locks write access to initialization and test control fields of Message RAM CMTOCPU2MSGRAM1 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
2 | LOCK_CMTOCPU2MSGRAM0 | R/W | 0h | Locks write access to initialization and test control fields of Message RAM CMTOCPU2MSGRAM0 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
1 | LOCK_CMTOCPU1MSGRAM1 | R/W | 0h | Locks write access to initialization and test control fields of Message RAM CMTOCPU1MSGRAM1 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
0 | LOCK_CMTOCPU1MSGRAM0 | R/W | 0h | Locks write access to initialization and test control fields of Message RAM CMTOCPU1MSGRAM0 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
CMMSGxTEST is shown in Figure 41-22 and described in Table 41-19.
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CM Messae RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_CMTOCPU2MSGRAM1 | TEST_CMTOCPU2MSGRAM0 | TEST_CMTOCPU1MSGRAM1 | TEST_CMTOCPU1MSGRAM0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7-6 | TEST_CMTOCPU2MSGRAM1 | R/W | 0h | Selects the different modes for Message RAM CMTOCPU2MSGRAM1 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
5-4 | TEST_CMTOCPU2MSGRAM0 | R/W | 0h | Selects the different modes for Message RAM CMTOCPU2MSGRAM0 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
3-2 | TEST_CMTOCPU1MSGRAM1 | R/W | 0h | Selects the different modes for Message RAM CMTOCPU1MSGRAM1 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
1-0 | TEST_CMTOCPU1MSGRAM0 | R/W | 0h | Selects the different modes for Message RAM CMTOCPU1MSGRAM0 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
CMMSGxINIT is shown in Figure 41-23 and described in Table 41-20.
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CM Messae RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_CMTOCPU2MSGRAM1 | INIT_CMTOCPU2MSGRAM0 | INIT_CMTOCPU1MSGRAM1 | INIT_CMTOCPU1MSGRAM0 | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | INIT_CMTOCPU2MSGRAM1 | R-0/W1S | 0h | RAM Initialization control for Message RAM CMTOCPU2MSGRAM1 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
2 | INIT_CMTOCPU2MSGRAM0 | R-0/W1S | 0h | RAM Initialization control for Message RAM CMTOCPU2MSGRAM0 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
1 | INIT_CMTOCPU1MSGRAM1 | R-0/W1S | 0h | RAM Initialization control for Message RAM CMTOCPU1MSGRAM1 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
0 | INIT_CMTOCPU1MSGRAM0 | R-0/W1S | 0h | RAM Initialization control for Message RAM CMTOCPU1MSGRAM0 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
CMMSGxINITDONE is shown in Figure 41-24 and described in Table 41-21.
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CM Messae RAM Initialization Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_CMTOCPU2MSGRAM1 | INITDONE_CMTOCPU2MSGRAM0 | INITDONE_CMTOCPU1MSGRAM1 | INITDONE_CMTOCPU1MSGRAM0 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | INITDONE_CMTOCPU2MSGRAM1 | R | 0h | RAM Initialization status for Message RAM CMTOCPU2MSGRAM1 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
2 | INITDONE_CMTOCPU2MSGRAM0 | R | 0h | RAM Initialization status for Message RAM CMTOCPU2MSGRAM0 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
1 | INITDONE_CMTOCPU1MSGRAM1 | R | 0h | RAM Initialization status for Message RAM CMTOCPU1MSGRAM1 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
0 | INITDONE_CMTOCPU1MSGRAM0 | R | 0h | RAM Initialization status for Message RAM CMTOCPU1MSGRAM0 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
SxGROUP1_LOCK is shown in Figure 41-25 and described in Table 41-22.
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Group1 S and E RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_E0 | LOCK_S3 | LOCK_S2 | LOCK_S1 | LOCK_S0 | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-5 | RESERVED | R | 0h | Reserved |
4 | LOCK_E0 | R/W | 0h | Locks write access to initialization and test control fields of E0 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
3 | LOCK_S3 | R/W | 0h | Locks write access to initialization and test control fields of S3 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
2 | LOCK_S2 | R/W | 0h | Locks write access to initialization and test control fields of S2 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
1 | LOCK_S1 | R/W | 0h | Locks write access to initialization and test control fields of S1 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
0 | LOCK_S0 | R/W | 0h | Locks write access to initialization and test control fields of S0 RAM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
SxGROUP1_TEST is shown in Figure 41-26 and described in Table 41-23.
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Group1 S and E RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEST_E0 | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_S3 | TEST_S2 | TEST_S1 | TEST_S0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | 0h | Reserved |
9-8 | TEST_E0 | R/W | 0h | Selects the different modes for E0 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
7-6 | TEST_S3 | R/W | 0h | Selects the different modes for S3 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
5-4 | TEST_S2 | R/W | 0h | Selects the different modes for S2 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
3-2 | TEST_S1 | R/W | 0h | Selects the different modes for S1 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
1-0 | TEST_S0 | R/W | 0h | Selects the different modes for S0 RAM: 00: Functional Mode. 01: Test mode to introduce Error in Data. Write updates only Data, ECC/Parity bits are not updated. 10: Test mode to introduce errors in ECC or Parity bits. ECC or Parity bits are visible on same memory map instead of Data bits. 11: Same as '00' but NMI is not generated on errors, used for diagnostics. Reset type: CM.RESETn |
SxGROUP1_INIT is shown in Figure 41-27 and described in Table 41-24.
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Group1 S and E RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_E0 | INIT_S3 | INIT_S2 | INIT_S1 | INIT_S0 | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-5 | RESERVED | R | 0h | Reserved |
4 | INIT_E0 | R-0/W1S | 0h | RAM Initialization control for E0 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
3 | INIT_S3 | R-0/W1S | 0h | RAM Initialization control for S3 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
2 | INIT_S2 | R-0/W1S | 0h | RAM Initialization control for S2 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
1 | INIT_S1 | R-0/W1S | 0h | RAM Initialization control for S1 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
0 | INIT_S0 | R-0/W1S | 0h | RAM Initialization control for S0 RAM: 0: None. 1: Start RAM Initialization. Reset type: CM.RESETn |
SxGROUP1_INITDONE is shown in Figure 41-28 and described in Table 41-25.
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Group1 S and E RAM Initialization Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_E0 | INITDONE_S3 | INITDONE_S2 | INITDONE_S1 | INITDONE_S0 | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-5 | RESERVED | R | 0h | Reserved |
4 | INITDONE_E0 | R | 0h | RAM Initialization status for E0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
3 | INITDONE_S3 | R | 0h | RAM Initialization status for S3 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
2 | INITDONE_S2 | R | 0h | RAM Initialization status for S2 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
1 | INITDONE_S1 | R | 0h | RAM Initialization status for S1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
0 | INITDONE_S0 | R | 0h | RAM Initialization status for S0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: CM.RESETn |
ROM_LOCK is shown in Figure 41-29 and described in Table 41-26.
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ROM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_BOOTROM | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | LOCK_BOOTROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of BOOTROM 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
ROM_TEST is shown in Figure 41-30 and described in Table 41-27.
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ROM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_BOOTROM | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | Reserved |
1-0 | TEST_BOOTROM | R/W | 0h | Selects the different modes for BOOTROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: CM.RESETn |
ROM_FORCE_ERROR is shown in Figure 41-31 and described in Table 41-28.
Return to the Summary Table.
ROM Force Error register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FORCE_BOOTROM_ERROR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | FORCE_BOOTROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: CM.RESETn |
PERI_MEM_TEST_LOCK is shown in Figure 41-32 and described in Table 41-29.
Return to the Summary Table.
Peripheral Memory Test Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_PERI_MEM_TEST_CONTROL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | LOCK_PERI_MEM_TEST_CONTROL | R/W | 0h | Locks write access to register PERI_MEM_TEST_CONTROL 0: Write access allowed 1: Write access blocked Reset type: CM.RESETn |
PERI_MEM_TEST_CONTROL is shown in Figure 41-33 and described in Table 41-30.
Return to the Summary Table.
Peripheral Memory Test control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EtherCAT_MEM_FORCE_ERROR | EtherCAT_TEST_ENABLE | RESERVED | RESERVED | EMAC_MEM_FORCE_ERROR | EMAC_TEST_ENABLE | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | Reserved |
5 | EtherCAT_MEM_FORCE_ERROR | R/W | 0h | Force error bit 0 : No effect 1 : Parity bit going to Parity checker module of EtherCAT is inverted to introduce parity Error Reset type: CM.RESETn |
4 | EtherCAT_TEST_ENABLE | R/W | 0h | Selects EtherCAT test mode 0 : EtherCAT test mode disabled, Error on EtherCAT memory read access will generate NMI 1 : EtherCAT test mode enabled, Error on EtherCAT memory read access will NOT generate NMI, used for diagnostics Reset type: CM.RESETn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | EMAC_MEM_FORCE_ERROR | R/W | 0h | Force error bit 0 : No effect 1 : Parity bit going to Parity checker module of EMAC is inverted to introduce parity Error Reset type: CM.RESETn |
0 | EMAC_TEST_ENABLE | R/W | 0h | Selects EMAC test mode 0 : EMAC test mode disabled, Error on EMAC memory read access will generate NMI 1 : EMAC test mode enabled, Error on EMAC memory read access will NOT generate NMI, used for diagnostics Reset type: CM.RESETn |