SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 31-38 lists the memory-mapped registers for the ESCSS_CONFIG_REGS registers. All register offset addresses not listed in Table 31-38 should be considered as reserved locations and the register contents should not be modified.
Offset (x8) | Offset (x16) | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|---|
0h | 0h | ESCSS_CONFIG_LOCK | EtherCATSS Configuration Lock | Go | |
4h | 2h | ESCSS_MISC_IO_CONFIG | RESET_IN, EEPROM IO connections select | LOCK | Go |
8h | 4h | ESCSS_PHY_IO_CONFIG | Control Register of ESCSS | Go | |
Ch | 6h | ESCSS_SYNC_IO_CONFIG | SYNC Signals IO configurations | LOCK | Go |
10h | 8h | ESCSS_LATCH_IO_CONFIG | LATCH inputs IO pad select | LOCK | Go |
14h | Ah | ESCSS_GPIN_SEL | GPIN Select between IO PAD & tieoff | LOCK | Go |
1Ch | Eh | ESCSS_GPOUT_SEL | GPOUT IO pad connect select | LOCK | Go |
24h | 12h | ESCSS_LED_CONFIG | Selection of LED o/p connect to IO pad | LOCK | Go |
28h | 14h | ESCSS_MISC_CONFIG | Miscelleneous Configuration | LOCK | Go |
Complex bit access types are encoded to fit into small table cells. Table 31-39 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value |
ESCSS_CONFIG_LOCK is shown in Figure 31-39 and described in Table 31-40.
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Lock bit for EtherCAT configuration registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WRITE_KEY | |||||||
R-0/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IO_CONFIG_ENABLE | RESERVED | LOCK_ENABLE | ||||
R-0-0h | R/W-0h | R-0-0h | R/WSonce-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | WRITE_KEY | R-0/W | 0h | The key value should be 0xa5 for the writes to bit 0 take effect. Writes of other values will be ignored. Reset type: ECAT.XRSn |
7-5 | RESERVED | R-0 | 0h | Reserved |
4 | IO_CONFIG_ENABLE | R/W | 0h | This bit enables the IO configurations allowing the EtherCAT ports to take effect. Till this bit is written EtherCAT ports are not connected to the IO pad. Enable takes effect when this bit is set to 1. Changing IO selections or IO configurations after this bit is set can have unpredictable IO behavior on the device IOs. Reset type: ECAT.XRSn |
3-1 | RESERVED | R-0 | 0h | Reserved |
0 | LOCK_ENABLE | R/WSonce | 0h | This bit enables locking the contents of all the EtherCAT configuration registers. The lock takes effect when this bit is set to 1. This bit can be set only once after ecatXRSN and gets reset after the next ecatXRSN. Reset type: ECAT.XRSn |
ESCSS_MISC_IO_CONFIG is shown in Figure 31-40 and described in Table 31-41.
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Condiguration of RESET_IN, EEPROM I2C connections
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WRITE_KEY | |||||||
R-0/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEPROM_I2C_IO_EN | RESETIN_GPIO_EN | |||||
R-0-0h | R/W-1h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | WRITE_KEY | R-0/W | 0h | The key value should be 0xa5 for the writes to this register to take effect. Writes of other values will be ignored. Reset type: ECAT.XRSn |
7-2 | RESERVED | R-0 | 0h | Reserved |
1 | EEPROM_I2C_IO_EN | R/W | 1h | Enables connecting EtherCAT I2C connections to IOPAD for EEPROM control 0: EEPROM I2C Connections are not connected to IOPAD. 1: EEPROM I2C connections are driving the IOPAD connections. Reset type: ECAT.XRSn |
0 | RESETIN_GPIO_EN | R/W | 0h | Acts as enabled to receive the Reset input from GPIO pad. 0: RESET_IN GPIO pad is not enabled, only SW & PMM resets affect EtherCAT reset 1: RESET_IN GPIO pad input is connected in reset input cone. Reset type: ECAT.XRSn |
ESCSS_PHY_IO_CONFIG is shown in Figure 31-41 and described in Table 31-42.
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PHY Type, clock source type select
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WRITE_KEY | |||||||
R-0/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_CLK_AUTO_COMP | RESERVED | PHY_PORT_CNT | RESERVED | |||
R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | WRITE_KEY | R-0/W | 0h | The key value should be 0xa5 for the writes to bit 0 take effect. Writes of other values will be ignored. Reset type: ECAT.XRSn |
7 | RESERVED | R/W | 0h | Reserved |
6 | TX_CLK_AUTO_COMP | R/W | 1h | This setting is used to allocate the IO pad for TX_CLK for doing the Auto compensation for the samlping of TXEN & TXDATA. 0 : Manual Compensation using CLK_IN no TX_CLK Pad, IP input is tied to '0'. 1: Auto Compensation based on sampling of TX_CLK. Pad is allocated. Reset type: ECAT.XRSn |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | PHY_PORT_CNT | R/W | 1h | Indicates the number of PHY ports selected for operation inaddition to Port0 which is default (information only, doesn't change configuration) 00-One port operation (Port0) 01-Two port operation(Port0,Port1) 10-Three port operation(Port0,Port1,Port2) : Reserved 11-Four port operation(Port0,Port1,Port2,Port3): Reserved Programming reserved configuration causes selection of Reset value. Reset type: ECAT.XRSn |
1-0 | RESERVED | R/W | 0h | Reserved |
ESCSS_SYNC_IO_CONFIG is shown in Figure 31-42 and described in Table 31-43.
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SYNC0/1 IO configurations including enable & Pad Select
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WRITE_KEY | |||||||
R-0/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC1_GPIO_EN | RESERVED | RESERVED | SYNC0_GPIO_EN | RESERVED | RESERVED | ||
R/W-1h | R-0-0h | R/W-0h | R/W-1h | R-0-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | WRITE_KEY | R-0/W | 0h | The key value should be 0xa5 for the writes to bit 0 take effect. Writes of other values will be ignored. Reset type: ECAT.XRSn |
7 | SYNC1_GPIO_EN | R/W | 1h | Enables the direct mux between Sync1 output of EtherCAT & other GPIO functions. Reset type: ECAT.XRSn |
6 | RESERVED | R-0 | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3 | SYNC0_GPIO_EN | R/W | 1h | Enables the direct mux between Sync0 output of EtherCAT & other GPIO functions. Reset type: ECAT.XRSn |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | RESERVED | R/W | 0h | Reserved |
ESCSS_LATCH_IO_CONFIG is shown in Figure 31-43 and described in Table 31-44.
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LATCH0/1 IO configurations including enable & Pad Select
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WRITE_KEY | |||||||
R-0/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LATCH1_GPIO_EN | RESERVED | RESERVED | LATCH0_GPIO_EN | RESERVED | RESERVED | ||
R/W-1h | R-0-0h | R/W-0h | R/W-1h | R-0-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | WRITE_KEY | R-0/W | 0h | The key value should be 0xa5 for the writes to bit 0 take effect. Writes of other values will be ignored. Reset type: ECAT.XRSn |
7 | LATCH1_GPIO_EN | R/W | 1h | Enables the direct mux between LATCH1 input from IOPAD & other GPIO functions to the EtherCATSS input Reset type: ECAT.XRSn |
6 | RESERVED | R-0 | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3 | LATCH0_GPIO_EN | R/W | 1h | Enables the direct mux between LATCH0 input from IOPAD & other GPIO functions to the EtherCATSS input Reset type: ECAT.XRSn |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | RESERVED | R/W | 0h | Reserved |
ESCSS_GPIN_SEL is shown in Figure 31-44 and described in Table 31-45.
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Register to configure each GPI input is connected to IO-pad or not.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIN_SEL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GPIN_SEL | R/W | 0h | Allows bit-wise selection of the GPIN be connected from GPIO PAD. Once those are not driven by GPIO, will be driven from register writable from local Host. 0: No connection to GPIO PAD, but connects to ESCSS_GPIN_DAT. 1: Mux Select the GPIN from the dedicated IO PAD. This acts as Mux select for input from GPIO over tieoff. Reset type: ECAT.XRSn |
ESCSS_GPOUT_SEL is shown in Figure 31-45 and described in Table 31-46.
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Register to configure each GPO to be connected to IO-pad or not.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPOUT_SEL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GPOUT_SEL | R/W | 0h | Allows bit-wise selection for GPOUT connection to IO PAD. hence acts as direct mux select between GPO & other non-EtherCAT functions. 0: GPO is not connected to dedicated IO instead non-EtherCAT function is connected. 1: Connect the GPOUT to the dedicated IO pad through output buffer. Reset type: ECAT.XRSn |
ESCSS_LED_CONFIG is shown in Figure 31-46 and described in Table 31-47.
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Register to select of LED o/p is connected to IO-PAD
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RUN | ERR | STATE | RESERVED | RESERVED | |
R/W-0h | R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R-0 | 0h | Reserved |
4 | RUN | R/W | 0h | Acts as Mux select to enable RUN LED function directly onto output pad. 0: The non-EtherCAT function is selected on the IO 1: RUN LED is selected to be output on the IO This selection assumes both buffer input and buffer enable connection as required. Reset type: ECAT.XRSn |
3 | ERR | R/W | 0h | Acts as Mux select to enable ERR LED function directly onto output pad. 0: The non-EtherCAT function is selected on the IO 1: ERR LED is selected to be output on the IO This selection assumes both buffer input and buffer enable connection as required. Reset type: ECAT.XRSn |
2 | STATE | R/W | 0h | Acts as Mux select to enable STATE LED function directly onto output pad. 0: The non-EtherCAT function is selected on the IO 1: STATE LED is selected to be output on the IO This selection assumes both buffer input and buffer enable connection as required. Reset type: ECAT.XRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
ESCSS_MISC_CONFIG is shown in Figure 31-47 and described in Table 31-48.
Return to the Summary Table.
Configuration info for the MII interface containing TX_SHIFT compensation values, PHY Address offset, EEPROM SIZE etc.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PHY_ADDR | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_ADDR | PDI_EMULATION | EEPROM_SIZE | TX1_SHIFT_CONFIG | TX0_SHIFT_CONFIG | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R-0 | 0h | Reserved |
10-6 | PHY_ADDR | R/W | 0h | These bits will be hooked up to the PHY_OFFSET[4:0] input of the EtherCAT IP. Reset type: ECAT.XRSn |
5 | PDI_EMULATION | R/W | 0h | This bit will be hooked up to the PDI_EMULATION input of the EtherCAT IP. Reset type: ECAT.XRSn |
4 | EEPROM_SIZE | R/W | 0h | This bit will be hooked up to the EEPROM_SIZE input of the EtherCAT IP . This is set to 0 for EEPROMs of size 16K bits or lower. This is set to 1 for EEPROMs of size above 16K bits. Reset type: ECAT.XRSn |
3-2 | TX1_SHIFT_CONFIG | R/W | 0h | Two bit TX_SHIFT configuration in terms of 10ns counts for port0. This is the shift added to TX_ENA & TX_DATA to match delay of PHY TX_CLK w.r.t. device internal clock. Reset type: ECAT.XRSn |
1-0 | TX0_SHIFT_CONFIG | R/W | 0h | Two bit TX_SHIFT configuration in terms of 10ns counts for port0. This is the shift added to TX_ENA & TX_DATA to match delay of PHY TX_CLK w.r.t. device internal clock. Reset type: ECAT.XRSn |