SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 12-51 lists the memory-mapped registers for the EMIF1_CONFIG_REGS registers. All register offset addresses not listed in Table 12-51 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | EMIF1LOCK | EMIF1 Config Lock Register | EALLOW | Go |
2h | EMIF1COMMIT | EMIF1 Config Lock Commit Register | EALLOW | Go |
4h | EMIF1MSEL | EMIF1 Master Sel Register | EALLOW | Go |
8h | EMIF1ACCPROT0 | EMIF1 Config Register 0 | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 12-52 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
EMIF1LOCK is shown in Figure 12-38 and described in Table 12-53.
Return to the Summary Table.
EMIF1 Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_EMIF1 | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | LOCK_EMIF1 | R/W | 0h | Locks the write to access protection and master select fields for EMIF1: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
EMIF1COMMIT is shown in Figure 12-39 and described in Table 12-54.
Return to the Summary Table.
EMIF1 Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_EMIF1 | ||||||
R-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | COMMIT_EMIF1 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for EMIF1: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in EMIF1LOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
EMIF1MSEL is shown in Figure 12-40 and described in Table 12-55.
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EMIF1 Master Sel Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
KEY | |||||||
R-0/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED | MSEL_EMIF1 | |||||
R-0/W-0h | R-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | KEY | R-0/W | 0h | Writing the value 0x93A5CE7 will allow the writing of the EMIF1Mselect bits, else writes are ignored. Reads will return 0. Reset type: CPU1.SYSRSn |
3-2 | RESERVED | R | 0h | Reserved |
1-0 | MSEL_EMIF1 | R/W | 0h | Master Select for EMIF1: 00: CPU1 is master but not grabbed. CPU2 can grab the master ownership by changing this value to '10'. 01: CPU1 is master. 10: CPU2 is master. 11: CPU1 is master but not grabbed. CPU2 can grab the master ownership by changing this value to '10'. Reset type: CPU1.SYSRSn |
EMIF1ACCPROT0 is shown in Figure 12-41 and described in Table 12-56.
Return to the Summary Table.
EMIF1 Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_EMIF1 | CPUWRPROT_EMIF1 | FETCHPROT_EMIF1 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_EMIF1 | R/W | 0h | DMA WR Protection For EMIF1: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_EMIF1 | R/W | 0h | CPU WR Protection For EMIF1: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_EMIF1 | R/W | 0h | Fetch Protection For EMIF1: 0: CPU Fetches are allowed. 1: CPU Fetches are blocked. Reset type: SYSRSn |