SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 13-3 lists the memory-mapped registers for the FLASH_CTRL_REGS registers. All register offset addresses not listed in Table 13-3 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | FRDCNTL | Flash Read Control Register | EALLOW | Go |
1Eh | FBAC | Flash Bank Access Control Register | EALLOW | Go |
20h | FBFALLBACK | Flash Bank Fallback Power Register | EALLOW | Go |
22h | FBPRDY | Flash Bank Pump Ready Register | EALLOW | Go |
24h | FPAC1 | Flash Pump Access Control Register 1 | EALLOW | Go |
2Ah | FMSTAT | Flash Module Status Register | EALLOW | Go |
180h | FRD_INTF_CTRL | Flash Read Interface Control Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 13-4 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
FRDCNTL is shown in Figure 13-6 and described in Table 13-5.
Return to the Summary Table.
Flash Read Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RWAIT | RESERVED | |||||||||||||
R-0h | R/W-3h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | RESERVED | R | 0h | Reserved |
11-8 | RWAIT | R/W | 3h | Random read waitstate These bits indicate how many waitstates are added to a flash read access. The RWAIT value can be set anywhere from 0 to 0xF. For a flash access, data is returned in RWAIT+1 SYSCLK cycles. Note: The required wait states for each SYSCLK frequency can be found in the device data manual. Note: Following table summarizes the effect of RWAIT on accessing OTP space. There are secutity related overides to RWAIT behavior, refer to security spec for these details. RWAIT Value | Data returned after 0 | 1 cycle 1 to F | RWAIT + 2 cycles Reset type: SYSRSn |
7-0 | RESERVED | R | 0h | Reserved |
FBAC is shown in Figure 13-7 and described in Table 13-6.
Return to the Summary Table.
Flash Bank Access Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BAGP | RESERVED | |||||||||||||||||||||||||||||
R-0h | R/W-0h | R/W-15h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | BAGP | R/W | 0h | Bank Active Grace Period. These bits contain the starting count value for the BAGP down counter. Any access to a given bank causes its BAGP counter to reload the BAGP value for that bank. After the last access to this flash bank, the down counter delays from 0 to 255 prescaled SYSCLK clock cycles before putting the bank into one of the fallback power modes as determined by the FBFALLBACK register. This value must be greater than 1 when the fallback mode is not ACTIVE. Note: The prescaled clock used for the BAGP down counter is a clock divided by 16 from input SYSCLK. Reset type: SYSRSn |
7-0 | RESERVED | R/W | 15h | Reserved |
FBFALLBACK is shown in Figure 13-8 and described in Table 13-7.
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Flash Bank Fallback Power Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BNKPWR0 | ||||||
R-0h | R/W-3h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1-0 | BNKPWR0 | R/W | 3h | Bank Power Mode Control 00 Sleep (Sense amplifiers and sense reference disabled) 01 Standby (Sense amplifiers disabled, but sense reference enabled) 10 Reserved 11 Active (Both sense amplifiers and sense reference enabled) Note: If the bank and pump are not in active mode and an access is made, the value of this register is automatically changed to active. Reset type: SYSRSn |
FBPRDY is shown in Figure 13-9 and described in Table 13-8.
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Flash Bank Pump Ready Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PUMPRDY | RESERVED | ||||||
R-1h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BANKRDY | ||||||
R-0h | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | PUMPRDY | R | 1h | Pump Ready. This is a read-only bit which allows software to determine if the pump is ready for flash access before attempting the actual access. If an access is made to a bank when the pump is not ready, wait states are asserted until it becomes ready. 0 Pump is not ready. 1 Pump is ready, in active power state. Reset type: SYSRSn |
14-1 | RESERVED | R | 0h | Reserved |
0 | BANKRDY | R | 1h | Bank Ready. This is a read-only register which allows software to determine if the bank is ready for Flash access before the access is attempted. Note: The user should wait for both the pump and the bank to be ready before attempting an access. 0 Bank is not ready. 1 Bank is in active power mode and is ready for access. Reset type: SYSRSn |
FPAC1 is shown in Figure 13-10 and described in Table 13-9.
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Flash Pump Access Control Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PSLEEP | ||||||
R-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PSLEEP | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PMPPWR | ||||||
R-0h | R/W-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-16 | PSLEEP | R/W | X | Pump sleep. These bits contain the starting count value for the charge pump sleep down counter. While the charge pump is in sleep mode, the power mode management logic holds the charge pump sleep counter at this value. When the charge pump exits sleep power mode, the down counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles before putting the charge pump into active power mode. Note: The pump sleep down counter uses the same prescaled clock as Bank sleep down counter which is divided by 2 of input SYSCLK. HW Reset Value for CPU1-FMC = 0xA0 SW Reset Value for CPU1-FMC = 0xA41 HW & SW Reset Value for CPU2-FMC= 0x834 Reset type: SYSRSn |
15-1 | RESERVED | R | 0h | Reserved |
0 | PMPPWR | R/W | 1h | Flash Charge Pump Fallback Power Mode. This bit selects what power mode the charge pump enters after the pump active grace period (PAGP) counter has timed out. 0 Sleep (all pump circuits disabled) 1 Active (all pump circuits active) Note for devices with multiple flash banks: As the pump is shared between flash banks, if an access is made either bank, the value of this bit changes to 1 (active). Reset type: SYSRSn |
FMSTAT is shown in Figure 13-11 and described in Table 13-10.
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Flash Module Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | PGV | RESERVED | EV | RESERVED | Busy |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERS | PGM | INVDAT | CSTAT | VOLTSTAT | ESUSP | PSUSP | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17 | RESERVED | R | 0h | Reserved |
16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | PGV | R | 0h | When set, indicates that a word is not successfully programmed after the maximum allowed number of program pulses are given for program operation. Reset type: SYSRSn |
11 | RESERVED | R | 0h | Reserved |
10 | EV | R | 0h | When set, indicates that a sector is not successfully erased after the maximum allowed number of erase pulses are given for erase operation. During Erase verify command, this flag is set immediately if a bit is found to be 0. Reset type: SYSRSn |
9 | RESERVED | R | 0h | Reserved |
8 | Busy | R | 0h | When set, this bit indicates that a program, erase, or suspend operation is being processed. Reset type: SYSRSn |
7 | ERS | R | 0h | When set, this bit indicates that the flash module is actively performing an erase operation. This bit is set when erasing starts and is cleared when erasing is complete. It is also cleared when the erase is suspended and set when the erase resumes. Reset type: SYSRSn |
6 | PGM | R | 0h | When set, this bit indicates that the flash module is currently performing a program operation. This bit is set when programming starts and i |