SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 3-61 lists the memory-mapped registers for the CM_CONF_REGS registers. All register offset addresses not listed in Table 3-61 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CMRESCTL | CM Reset Control Register | EALLOW | Go |
2h | CMTOCPU1NMICTL | CM To CPU1 NMI Control register | EALLOW | Go |
4h | CMTOCPU1INTCTL | CM To CPU1 interrupt Control register | EALLOW | Go |
20h | PALLOCATE0 | CM Peripheral Allocation Register. | EALLOW | Go |
3FEh | CM_CONF_REGS_LOCK | CM Configuration Registers Lock | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-62 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CMRESCTL is shown in Figure 3-61 and described in Table 3-63.
Return to the Summary Table.
Software reset of CM.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTS | RESET | |||||
R-0h | R-0h | R/W-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored Reset type: CPU1.SYSRSn |
15-2 | RESERVED | R | 0h | Reserved |
1 | RESETSTS | R | 0h | 0: CM is under reset 1: CM is out of reset. Reset type: CPU1.SYSRSn |
0 | RESET | R/W | 1h | 1: Asserts reset to CM. 0: De-asserts reset to CM. Software Note: This bit should be kept high until RESETSTS bit of CMRSTCTL register goes low. Reset type: CPU1.SYSRSn |
CMTOCPU1NMICTL is shown in Figure 3-62 and described in Table 3-64.
Return to the Summary Table.
CM To CPU1 NMI Control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMNMIWDRST | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CMNMIWDRST | R/W | 0h | 0: NMI to CPU1 is not fired on a CMNMIWDRST to CM4. 1: NMI to CPU1 is fired on a CMNMIWDRST to CM4. Reset type: XRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
CMTOCPU1INTCTL is shown in Figure 3-63 and described in Table 3-65.
Return to the Summary Table.
CM To CPU1 interrupt Control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMNMIWDRST | SYSRESETREQ | VECTRESET | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CMNMIWDRST | R/W | 0h | 0: Interrupt to CPU1 is not fired on a CMNMIWDRST to CM4. 1: Interrupt to CPU1 is fired on a CMNMIWDRST to CM4. Reset type: XRSn |
1 | SYSRESETREQ | R/W | 0h | 0: Interrupt to CPU1 is not fired on a SYSRESETREQ to CM4. 1: Interrupt to CPU1 is fired on a SYSRESETREQ to CM4. Reset type: XRSn |
0 | VECTRESET | R/W | 0h | 0: Interrupt to CPU1 is not fired on a VECTRESET to CM4. 1: Interrupt to CPU1 is fired on a VECTRESET to CM4. Reset type: XRSn |
PALLOCATE0 is shown in Figure 3-64 and described in Table 3-66.
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CM Peripheral Allocation Register for shared peripherals.
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the PALLOCATEx register must be configured before the PCLKCRx register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCAN_A | CAN_B | CAN_A | ETHERCAT | USB_A | ||
R-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | MCAN_A | R/W | 1h | 0: MCAN_A is allocated to C28x CPU1, CM accesses to MCAN_A will be ignored and interrupts from MCAN_A will not be generated to CM. 1: MCAN_A is allocated to CM, C28x CPU1 accesses to MCAN_A will be ignored and interrupts from MCAN_A will not be generated to C28x CPU1. Note:CPU2 does not have access to MCAN_A. Reset type: XRSn |
3 | CAN_B | R/W | 0h | 0: CAN_B is allocated to C28x CPU1 or CPU2 (Mapping to CPU1 or CPU2 is determined by CPUSELx.CAN_B bit setting), CM accesses to CAN_B will be ignored and interrupts from CAN_B will not be generated to CM. 1: CAN_B is allocated to CM, C28x CPU1/2 accesses to CAN_B will be ignored and interrupts from CAN_B will not be generated to C28x CPU1/2. Reset type: XRSn |
2 | CAN_A | R/W | 0h | 0: CAN_A is allocated to C28x CPU1 or CPU2 (Mapping to CPU1 or CPU2 is determined by CPUSELx.CAN_A bit setting), CM accesses to CAN_A will be ignored and interrupts from CAN_A will not be generated to CM. 1: CAN_A is allocated to CM, C28x CPU1/2 accesses to CAN_A will be ignored and interrupts from CAN_A will not be generated to C28x CPU1/2. Reset type: XRSn |
1 | ETHERCAT | R/W | 0h | 0: ETHERCAT is allocated to C28x CPU1, CM accesses to ETHERCAT will be ignored and interrupts from ETHERCAT will not be generated to CM. 1: ETHERCAT is allocated to CM, C28x CPU1 accesses to ETHERCAT will be ignored and interrupts from ETHERCAT will not be generated to C28x CPU1. Note:CPU2 does not have access to ETHERCAT. Reset type: XRSn |
0 | USB_A | R/W | 0h | 0: USB_A is allocated to C28x CPU1, CM accesses to USB_A will be ignored and interrupts from USB_A will not be generated to CM. 1: USB_A is allocated to CM, C28x CPU1 accesses to USB_A will be ignored and interrupts from USB_A will not be generated to C28x CPU1. Note:CPU2 does not have access to USB_A. Reset type: XRSn |
CM_CONF_REGS_LOCK is shown in Figure 3-65 and described in Table 3-67.
Return to the Summary Table.
CM Configuration Registers Lock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK | ||||||
R-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | LOCK | R/WSonce | 0h | 0: Allows write to the following registers 1: Writes to following registers are ignored. 1. PALLOCATE0 2. RAMALLOCATE 3. CMTOCPU1NMICTL 4. CMTOCPU1INTCTL Reset type: XRSn |