SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 14-24 lists the memory-mapped registers for the ERAD_COUNTER_REGS registers. All register offset addresses not listed in Table 14-24 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CTM_CNTL | Counter Control Register | EALLOW | Go |
1h | CTM_STATUS | Counter Status Register | EALLOW | Go |
2h | CTM_REF | Counter Reference Register | EALLOW | Go |
4h | CTM_COUNT | Counter Current Value Register | EALLOW | Go |
6h | CTM_MAX_COUNT | Counter Max Count Value Register | EALLOW | Go |
8h | CTM_INPUT_SEL | Counter Input Select Register | EALLOW | Go |
9h | CTM_CLEAR | Counter Clear Register | EALLOW | Go |
Ah | CTM_INPUT_SEL_2 | Counter Input Select Extension Register | EALLOW | Go |
Bh | CTM_INPUT_COND | Counter Input Conditioning Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 14-25 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CTM_CNTL is shown in Figure 14-23 and described in Table 14-26.
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Counter Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CNT_INP_SEL_EN | RST_EN | RESERVED | START_STOP_CUMULATIVE | |||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTOSINT | STOP | RESERVED | RST_ON_MATCH | EVENT_MODE | START_STOP_MODE | RESERVED | |
R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11 | CNT_INP_SEL_EN | R/W | 0h | 0 = Disable using the input_select register for the count input. The counter will always count CPU cycles. 1 = Enable using the input_select register for the count input. The counter will count the event selected by the count input register. Reset type: ERAD_RESET |
10 | RST_EN | R/W | 0h | This bit decides if the reset input is enabled or not. Setting this to 1 will cause the counter to reset to zero whenever the selected reset input goes active high. No event will be generated when the counter is reset. Setting this bit to 0 will cause the counter to ignore the reset inputs. Reset type: ERAD_RESET |
9 | RESERVED | R | 0h | Reserved |
8 | START_STOP_CUMULATIVE | R/W | 0h | This bit decides whether the counter counts to give the cumulative cycle count for 'n' number of successive start stop events or clears the counter on very stop event to record the MAX_COUNT across successive start stop sequences. 0 When in START_STOP mode counter gets cleared on every stop event and MAX_COUNT records the max value 1 When in START_STOP mode counter keeps counting between successive start stop events to generate a cumulative count w/o clearing the counter on any stop events. MAX_COUNT register is invalid when this bit is set. Reset type: ERAD_RESET |
7 | RTOSINT | R/W | 0h | This bit decides whether the counter module will generate RTOSINTn interrupt when count value matches the reference. Note that the event outputs will always be generated regardless of the state of this bit. 0 The counter unit will not cause any action towards the CPU. 1 The counter unit will assert RTOSINTn when the count value matches the reference value. Reset type: ERAD_RESET |
6 | STOP | R/W | 0h | This bit decides whether the counter module will generate a watchpoint to the CPU when the count value matches the reference. Note that the event outputs will always be generated regardless of the state of this bit. 0 The counter unit will not generate a watchpoint. 1 The counter unit will assert ANASTOP when the count value matches the reference. Reset type: ERAD_RESET |
5 | RESERVED | R | 0h | Reserved |
4 | RST_ON_MATCH | R/W | 0h | This bit is used to decide whether the counter will reset to zero once it reaches the reference value. 0 Counter will stay at the reference value and the counter will go to COMPLETED state and further counting will be stopped. 1 The counter will reset to zero once it reaches the match value and will stay enabled. Reset type: ERAD_RESET |
3 | EVENT_MODE | R/W | 0h | This bit is used to decide whether the counter will count the level of the event or the edge of the event. 0 Counter will increment the count as long as the count input is active high. 1 The counter will count only on the rising edge of the count input. Reset type: ERAD_RESET |
2 | START_STOP_MODE | R/W | 0h | This bit is used to decide whether the counter will count in the START_STOP mode or not. 0 Normal count mode. The counter will not depend on the START and STOP events 1 This is the START-STOP mode of the counter. The counter will start counting only after the START input has been asserted. It will continue to count the selected event till the STOP event is seen. Reset type: ERAD_RESET |
1-0 | RESERVED | R | 0h | Reserved |
CTM_STATUS is shown in Figure 14-24 and described in Table 14-27.
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Counter Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
STATUS | MODULE_ID | ||||||
R-0h | R-4h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODULE_ID | OVERFLOW | EVENT_FIRED | |||||
R-4h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | STATUS | R | 0h | Counter unit status, 00 Idle 10 Enabled 11 Completed Reset type: ERAD_RESET |
11-2 | MODULE_ID | R | 4h | These bits are always a constant representing a unique identification for the trigger unit. Reset type: ERAD_RESET |
1 | OVERFLOW | R | 0h | This is a sticky bit which gets set every time the counter overflows and wraps around after reaching 0xffffffff.This bit will get cleared by writing a '1' to bit 9 of the CTM_CNTL register. Reset type: ERAD_RESET |
0 | EVENT_FIRED | R | 0h | This is a sticky bit which gets set every time the CTM unit generates a match event. This will be used by software to figure out whether this CTM module fired an event or not. This bit will get cleared by writing a '1' to bit 9 of the CTM_CNTL register. Reset type: ERAD_RESET |
CTM_REF is shown in Figure 14-25 and described in Table 14-28.
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Counter Reference Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REF | R/W | 0h | This register contains the counter reference value for comparison. The counter will generate an event if the count value matches the reference register (considering both upper and lower half of the register). This register is writable by CPU only if application owns the unit and if EALLOW is set. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored. Refrence match is enabled only when a non zero value is programmed on one of the REF register. Reset type: ERAD_RESET |
CTM_COUNT is shown in Figure 14-26 and described in Table 14-29.
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Counter Current Value Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h | This register contains the current count value. The counter will generate an event if the count value matches the reference register (considering both upper and lower half of the register). This register is writable by CPU only if application owns the unit and if EALLOW is set. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored. Reset type: ERAD_RESET |
CTM_MAX_COUNT is shown in Figure 14-27 and described in Table 14-30.
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Counter Max Count Value Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAX_COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAX_COUNT | R/W | 0h | This register contains the maximum recorded counter value. This is relevant only in the Start Stop mode of operation. This register is writable by CPU only if application owns the unit and if EALLOW is set. Otherwise, the writes are ignored. The register is writable by the debugger only if the debugger owns this unit. Otherwise, the writes are ignored. Reset type: ERAD_RESET |
CTM_INPUT_SEL is shown in Figure 14-28 and described in Table 14-31.
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Counter Input Select Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STA_INP_SEL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNT_INP_SEL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14-8 | STA_INP_SEL | R/W | 0h | These bits decide which of the inputs will be selected as the START event for the counter. These inputs will be hooked up to the event outputs from the breakpoint module, counter module and to other system events. The usage of these bits are relevant only in the START_STOP mode of counting. Reset type: ERAD_RESET |
7 | RESERVED | R | 0h | Reserved |
6-0 | CNT_INP_SEL | R/W | 0h | These bits decide which of the inputs will be selected to enable counting. These inputs will be hooked up to the event outputs from the breakpoint module, counter module and to other system events Reset type: ERAD_RESET |
CTM_CLEAR is shown in Figure 14-29 and described in Table 14-32.
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Counter Clear Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OVERFLOW_CLEAR | EVENT_CLEAR | |||||
R-0h | R-0/W-0h | R-0/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R | 0h | Reserved |
1 | OVERFLOW_CLEAR | R-0/W | 0h | Clear OVERFLOW: 0 No action. 1 A write with this bit set to 1 will clear the sticky OVERFLOW bit in the CTM_STATUS register. Reads of this bit position will always return a 0. Reset type: ERAD_RESET |
0 | EVENT_CLEAR | R-0/W | 0h | Clear EVENT_FIRED: 0 No action. 1 A write with this bit set to 1 will clear the sticky EVENT_FIRED bit in the CTM_STATUS register and bring the Breakpoint Module statemachine status back to IDLE. Reads of this bit position will always return a 0. Reset type: ERAD_RESET |
CTM_INPUT_SEL_2 is shown in Figure 14-30 and described in Table 14-33.
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Counter Input Select Extension Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RST_INP_SEL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STO_INP_SEL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14-8 | RST_INP_SEL | R/W | 0h | These bits decide are used to select the event input that will be used as the reset input. These bits matter only if the Enable Reset bit is set to 1. Reset type: ERAD_RESET |
7 | RESERVED | R | 0h | Reserved |
6-0 | STO_INP_SEL | R/W | 0h | These bits decide which of the inputs will be selected as the STOP event for the counter. These inputs will be hooked up to the event outputs from the breakpoint module, counter module and to other system events. The usage of these bits are relevant only in the START_STOP mode of counting. Reset type: ERAD_RESET |
CTM_INPUT_COND is shown in Figure 14-31 and described in Table 14-34.
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Counter Input Conditioning Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RST_INP_SYNCH | RST_INP_INV | RESERVED | STO_INP_SYNCH | STO_INP_INV | ||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STA_INP_SYNCH | STA_INP_INV | RESERVED | CTM_INP_SYNCH | CTM_INP_INV | ||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13 | RST_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for the selected Reset input Reset type: ERAD_RESET |
12 | RST_INP_INV | R/W | 0h | Invert the Selected Reset input Reset type: ERAD_RESET |
11-10 | RESERVED | R | 0h | Reserved |
9 | STO_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for the selected Stop input Reset type: ERAD_RESET |
8 | STO_INP_INV | R/W | 0h | Invert the Selected Stop input Reset type: ERAD_RESET |
7-6 | RESERVED | R | 0h | Reserved |
5 | STA_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for the selected Start input Reset type: ERAD_RESET |
4 | STA_INP_INV | R/W | 0h | Invert the Selected Start input Reset type: ERAD_RESET |
3-2 | RESERVED | R | 0h | Reserved |
1 | CTM_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for the selected Counter input Reset type: ERAD_RESET |
0 | CTM_INP_INV | R/W | 0h | Invert the Selected Counter input Reset type: ERAD_RESET |