SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 3-365 lists the memory-mapped registers for the SYS_STATUS_REGS registers. All register offset addresses not listed in Table 3-365 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CM_STATUS_INT_FLG | Status of interrupts due to multiple sources of Cortex-M4 reset. | Go | |
2h | CM_STATUS_INT_CLR | CM_STATUS_INT_FLG clear register | Go | |
4h | CM_STATUS_INT_SET | CM_STATUS_INT_FLG set register | EALLOW | Go |
6h | CM_STATUS_MASK | CM_STATUS_MASK register | EALLOW | Go |
10h | SYS_ERR_INT_FLG | Status of interrupts due to multiple different errors in the system. | Go | |
12h | SYS_ERR_INT_CLR | SYS_ERR_INT_FLG clear register | Go | |
14h | SYS_ERR_INT_SET | SYS_ERR_INT_FLG set register | EALLOW | Go |
16h | SYS_ERR_MASK | SYS_ERR_MASK register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-366 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CM_STATUS_INT_FLG is shown in Figure 3-337 and described in Table 3-367.
Return to the Summary Table.
Status of interrupts due to multiple sources of Cortex-M4 reset.
Note: This register is present only on CPU1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMVECTRESET | CMSYSRESETREQ | CMNMIWDRST | GINT | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CMVECTRESET | R | 0h | 0:CMVECTRESET has not caused a reset of CM 1:CMVECTRESET had caused a reset of CM, an interrupt will be fired if GINT flag is not set. Reset type: SYSRSn |
2 | CMSYSRESETREQ | R | 0h | 0:CMSYSRESETREQ has not caused a reset of CM 1:CMSYSRESETREQ had caused a reset of CM, an interrupt will be fired if GINT flag is not set. Reset type: SYSRSn |
1 | CMNMIWDRST | R | 0h | 0:CMNMIWDRST has not caused a reset of CM 1:CMNMIWDRST had caused a reset of CM, an interrupt will be fired if GINT flag is not set. Reset type: SYSRSn |
0 | GINT | R | 0h | Global Interrupt flag: 0: On any of the flags of CM_STATUS_INT_FLG register being set, CM_STATUS_INT is pulsed and GINT flag would be set 1: No further interrupts would be fired until GINT flag is cleared Reset type: SYSRSn |
CM_STATUS_INT_CLR is shown in Figure 3-338 and described in Table 3-368.
Return to the Summary Table.
CM_STATUS_INT_FLG clear register
Note: This register is present only on CPU1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMVECTRESET | CMSYSRESETREQ | CMNMIWDRST | GINT | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CMVECTRESET | R-0/W1S | 0h | 0: No effect 1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be cleared. Reset type: SYSRSn |
2 | CMSYSRESETREQ | R-0/W1S | 0h | 0: No effect 1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be cleared. Reset type: SYSRSn |
1 | CMNMIWDRST | R-0/W1S | 0h | 0: No effect 1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be cleared. Reset type: SYSRSn |
0 | GINT | R-0/W1S | 0h | 0: No effect 1: GINT flag of CM_STATUS_INT_FLG reister will be cleared. Reset type: SYSRSn |
CM_STATUS_INT_SET is shown in Figure 3-339 and described in Table 3-369.
Return to the Summary Table.
CM_STATUS_INT_FLG set register
Note: This register is present only on CPU1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMVECTRESET | CMSYSRESETREQ | CMNMIWDRST | RESERVED | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
15-4 | RESERVED | R | 0h | Reserved |
3 | CMVECTRESET | R-0/W1S | 0h | 0: No effect 1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be set. Reset type: SYSRSn |
2 | CMSYSRESETREQ | R-0/W1S | 0h | 0: No effect 1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be set. Reset type: SYSRSn |
1 | CMNMIWDRST | R-0/W1S | 0h | 0: No effect 1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be set. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
CM_STATUS_MASK is shown in Figure 3-340 and described in Table 3-370.
Return to the Summary Table.
CM_STATUS_MASK register
Note: This register is present only on CPU1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMVECTRESET | CMSYSRESETREQ | CMNMIWDRST | RESERVED | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
15-4 | RESERVED | R | 0h | Reserved |
3 | CMVECTRESET | R/W | 0h | 0: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be set on a hardware event. 1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
2 | CMSYSRESETREQ | R/W | 0h | 0: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be set on a hardware event. 1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
1 | CMNMIWDRST | R/W | 0h | 0: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be set on a hardware event. 1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
SYS_ERR_INT_FLG is shown in Figure 3-341 and described in Table 3-371.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DCC2 | DCC1 | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCC0 | AUX_PLL_SLIP_NOTSUPPORTED | SYS_PLL_SLIP_NOTSUPPORTED | RAM_ACC_VIOL | FLASH_CORRECTABLE_ERR | RAM_CORRECTABLE_ERR | EMIF_ERR | GINT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | DCC2 | R | 0h | 0: DCC2 has not fired an interrupt. 1: DCC2 has fired an interrupt Reset type: SYSRSn |
8 | DCC1 | R | 0h | 0: DCC1 has not fired an interrupt. 1: DCC1 has fired an interrupt Reset type: SYSRSn |
7 | DCC0 | R | 0h | 0: DCC0 has not fired an interrupt. 1: DCC0 has fired an interrupt Reset type: SYSRSn |
6 | AUX_PLL_SLIP_NOTSUPPORTED | R | 0h | RESERVED: This bit is reserved and the value read should be ignored. Reset type: SYSRSn |
5 | SYS_PLL_SLIP_NOTSUPPORTED | R | 0h | RESERVED: This bit is reserved and the value read should be ignored. Reset type: SYSRSn |
4 | RAM_ACC_VIOL | R | 0h | 0: None of the Masters have violated the set protection rules 1: At least one of the master accesses has violated one or more of the access protection rules Reset type: SYSRSn |
3 | FLASH_CORRECTABLE_ERR | R | 0h | 0: Number of correctable errors detected has not exceeded the set threshold in FLASH. 1:Number of correctable errors detected has exceeded the set threshold in FLASH. Reset type: SYSRSn |
2 | RAM_CORRECTABLE_ERR | R | 0h | 0: Number of correctable errors detected has not exceeded the set threshold in any of the RAMs. 1:Number of correctable errors detected has exceeded the set threshold in atleast one of the RAMs. Reset type: SYSRSn |
1 | EMIF_ERR | R | 0h | 0: EMIF error has not occurred. 1: EMIF error has occurred. Reset type: SYSRSn |
0 | GINT | R | 0h | Global Interrupt flag: 0: On any of the flags of SYS_ERR_INT_FLG register being set, SYS_ERR_INT is pulsed and GINT flag would be set 1: No further interrupts would be fired until GINT flag is cleared Reset type: SYSRSn |
SYS_ERR_INT_CLR is shown in Figure 3-342 and described in Table 3-372.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DCC2 | DCC1 | |||||
R-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCC0 | AUX_PLL_SLIP_NOTSUPPORTED | SYS_PLL_SLIP_NOTSUPPORTED | RAM_ACC_VIOL | FLASH_CORRECTABLE_ERR | RAM_CORRECTABLE_ERR | EMIF_ERR | GINT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | DCC2 | R-0/W1S | 0h | 0: No effect 1: DCC2 flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
8 | DCC1 | R-0/W1S | 0h | 0: No effect 1: DCC1 flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
7 | DCC0 | R-0/W1S | 0h | 0: No effect 1: DCC0 flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
6 | AUX_PLL_SLIP_NOTSUPPORTED | R-0/W1S | 0h | RESERVED: This bit is reserved and the value set should always be '0' Reset type: SYSRSn |
5 | SYS_PLL_SLIP_NOTSUPPORTED | R-0/W1S | 0h | RESERVED: This bit is reserved and the value set should always be '0' Reset type: SYSRSn |
4 | RAM_ACC_VIOL | R-0/W1S | 0h | 0: No effect 1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
3 | FLASH_CORRECTABLE_ERR | R-0/W1S | 0h | 0: No effect 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
2 | RAM_CORRECTABLE_ERR | R-0/W1S | 0h | 0: No effect 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
1 | EMIF_ERR | R-0/W1S | 0h | 0: No effect 1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
0 | GINT | R-0/W1S | 0h | 0: No effect 1: GINT flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
SYS_ERR_INT_SET is shown in Figure 3-343 and described in Table 3-373.
Return to the Summary Table.
SYS_ERR_INT_FLG set register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DCC2 | DCC1 | |||||
R-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCC0 | AUX_PLL_SLIP_NOTSUPPORTED | SYS_PLL_SLIP_NOTSUPPORTED | RAM_ACC_VIOL | FLASH_CORRECTABLE_ERR | RAM_CORRECTABLE_ERR | EMIF_ERR | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | DCC2 | R-0/W1S | 0h | 0: No effect 1: DCC2 flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
8 | DCC1 | R-0/W1S | 0h | 0: No effect 1: DCC1 flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
7 | DCC0 | R-0/W1S | 0h | 0: No effect 1: DCC0 flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
6 | AUX_PLL_SLIP_NOTSUPPORTED | R-0/W1S | 0h | RESERVED: This bit is reserved and the value set should always be '0' Reset type: SYSRSn |
5 | SYS_PLL_SLIP_NOTSUPPORTED | R-0/W1S | 0h | RESERVED: This bit is reserved and the value set should always be '0' Reset type: SYSRSn |
4 | RAM_ACC_VIOL | R-0/W1S | 0h | 0: No effect 1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
3 | FLASH_CORRECTABLE_ERR | R-0/W1S | 0h | 0: No effect 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
2 | RAM_CORRECTABLE_ERR | R-0/W1S | 0h | 0: No effect 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
1 | EMIF_ERR | R-0/W1S | 0h | 0: No effect 1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
SYS_ERR_MASK is shown in Figure 3-344 and described in Table 3-374.
Return to the Summary Table.
SYS_ERR_MASK register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DCC2 | DCC1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCC0 | AUX_PLL_SLIP | SYS_PLL_SLIP | RAM_ACC_VIOL | FLASH_CORRECTABLE_ERR | RAM_CORRECTABLE_ERR | EMIF_ERR | RESERVED |
R/W-0h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R/W | 0h | A value of 0xa5a5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | DCC2 | R/W | 0h | 0: DCC2 flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: DCC2 flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
8 | DCC1 | R/W | 0h | 0: DCC1 flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: DCC1 flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
7 | DCC0 | R/W | 0h | 0: DCC0 flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: DCC0 flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
6 | AUX_PLL_SLIP | R/W | 1h | RESERVED: This bit is reserved and the value set should always be '1' Note: This bit must always be set to 1. Reset type: SYSRSn |
5 | SYS_PLL_SLIP | R/W | 1h | RESERVED: This bit is reserved and the value set should always be '1' Note: This bit must always be set to 1. Reset type: SYSRSn |
4 | RAM_ACC_VIOL | R/W | 0h | 0: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
3 | FLASH_CORRECTABLE_ERR | R/W | 0h | 0: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
2 | RAM_CORRECTABLE_ERR | R/W | 0h | 0: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
1 | EMIF_ERR | R/W | 0h | 0: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |