SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 46-4 lists the memory-mapped registers for the CM_I2C_REGS registers. All register offset addresses not listed in Table 46-4 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | I2CMSA | I2C Master Slave Address | Go | |
4h | I2CMCS | I2C Master Control/Status | Go | |
8h | I2CMDR | I2C Master Data | Go | |
Ch | I2CMTPR | I2C Master Timer Period | Go | |
10h | I2CMIMR | I2C Master Interrupt Mask | Go | |
14h | I2CMRIS | I2C Master Raw Interrupt Status | Go | |
18h | I2CMMIS | I2C Master Masked Interrupt Status | Go | |
1Ch | I2CMICR | I2C Master Interrupt Clear | Go | |
20h | I2CMCR | I2C Master Configuration | Go | |
24h | I2CMCLKOCNT | I2C Master Clock Low Timeout Count | Go | |
2Ch | I2CMBMON | I2C Master Bus Monitor | Go | |
30h | I2CMBLEN | I2C Master Burst Length | Go | |
34h | I2CMBCNT | I2C Master Burst Count | Go | |
800h | I2CSOAR | I2C Slave Own Address | Go | |
804h | I2CSCSR | I2C Slave Control/Status | Go | |
808h | I2CSDR | I2C Slave Data | Go | |
80Ch | I2CSIMR | I2C Slave Interrupt Mask | Go | |
810h | I2CSRIS | I2C Slave Raw Interrupt Status | Go | |
814h | I2CSMIS | I2C Slave Masked Interrupt Status | Go | |
818h | I2CSICR | I2C Slave Interrupt Clear | Go | |
81Ch | I2CSOAR2 | I2C Slave Own Address 2 | Go | |
820h | I2CSACKCTL | I2C Slave ACK Control | Go | |
F00h | I2CFIFODATARX | I2C FIFO Data RX | Go | |
F04h | I2CFIFOCTL | I2C FIFO Control | Go | |
F08h | I2CFIFOSTATUS | I2C FIFO Status | Go | |
FC0h | I2CPP | I2C Peripheral Properties | Go | |
FC4h | I2CPC | I2C Peripheral Configuration | Go |
Complex bit access types are encoded to fit into small table cells. Table 46-5 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
RC | R C | Read to Clear |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
I2CMSA is shown in Figure 46-16 and described in Table 46-6.
Return to the Summary Table.
I2C Master Slave Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SA | RS | |||||||||||||
R-0h | R/W-0h | R/W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-1 | SA | R/W | 0h | I2C Slave Address This field specifies bits A6 through A0 of the slave address. Reset type: PER.RESET |
0 | RS | R/W | 0h | Receive/Send The RS bit specifies if the next master operation is a Receive (High) or Transmit (Low). Value Description 0 Transmit 1 Receive Reset type: PER.RESET |
I2CMCS is shown in Figure 46-17 and described in Table 46-7.
Return to the Summary Table.
I2C Master Control/Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ACTDMARX | ACTDMATX | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKTO | BUSBSY | IDLE | ARBLST | DATACK | ADRACK | ERROR | BUSY |
R-0h | R-0h | R-1h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ACTDMARX | R | 0h | DMA RX Active Status Value Description 0 DMA RX is not active 1 DMA RX is active. Reset type: PER.RESET |
30 | ACTDMATX | R | 0h | DMA TX Active Status Value Description 0 DMA TX is not active 1 DMA TX is active. Reset type: PER.RESET |
29-8 | RESERVED | R | 0h | Reserved |
7 | CLKTO | R | 0h | Clock Timeout Error Value Description 0 No clock timeout error. 1 The clock timeout error has occurred. This bit is cleared when the master sends a STOP condition or if the I2C master is reset. Reset type: PER.RESET |
6 | BUSBSY | R | 0h | Bus Busy Value Description 0 The I2C bus is idle. 1 The I2C bus is busy. The bit changes based on the START and STOP conditions. Reset type: PER.RESET |
5 | IDLE | R | 1h | I2C Idle Value Description 0 The I2C controller is not idle. 1 The I2C controller is idle. Reset type: PER.RESET |
4 | ARBLST | R | 0h | Arbitration Lost Value Description 0 The I2C controller won arbitration. 1 The I2C controller lost arbitration. Reset type: PER.RESET |
3 | DATACK | R | 0h | Acknowledge Data Value Description 0 The transmitted data was acknowledged 1 The transmitted data was not acknowledged. Reset type: PER.RESET |
2 | ADRACK | R | 0h | Acknowledge Address Value Description 0 The transmitted address was acknowledged 1 The transmitted address was not acknowledged. Reset type: PER.RESET |
1 | ERROR | R | 0h | Error Value Description 0 No error was detected on the last operation. 1 An error occurred on the last operation. The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. Reset type: PER.RESET |
0 | BUSY | R | 0h | I2C Busy Value Description 0 The controller is idle. 1 The controller is busy. When the BUSY bit is set, the other status bits are not valid. Reset type: PER.RESET |
I2CMDR is shown in Figure 46-18 and described in Table 46-8.
Return to the Summary Table.
I2C Master Data
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R/W | 0h | This byte contains the data transferred during a transaction. Reset type: PER.RESET |
I2CMTPR is shown in Figure 46-19 and described in Table 46-9.
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I2C Master Timer Period
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PULSEL | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HS | TPR | |||||||||||||
R-0h | R-0/W-0h | R/W-1h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | PULSEL | R/W | 1h | Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of system clocks. Value Description 0x0 Reserved (Invalid configuration) 0x1 1 clock 0x2 2 clocks 0x3 3 clocks 0x4 4 clocks 0x5 8 clocks 0x6 16 clocks Reset type: PER.RESET |
15-8 | RESERVED | R | 0h | Reserved |
7 | HS | R-0/W | 0h | High-Speed Enable Value Description 0 The SCL Clock Period set by TPR applies to Standard mode (100 Kbps), Fast-mode (400 Kbps), or Fast-mode plus (1 Mbps). 1 The SCL Clock Period set by TPR applies to High-speed mode (3.33 Mbps). Reset type: PER.RESET |
6-0 | TPR | R/W | 1h | Timer Period This field is used in the equation to configure SCL_PERIOD: SCL_PERIOD = 2 X (1 + TPR) X ( SCL_LP + SCL_HP) X CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the system clock period in ns. Reset type: PER.RESET |
I2CMIMR is shown in Figure 46-20 and described in Table 46-10.
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I2C Master Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFIM | TXFEIM | RXIM | TXIM | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARBLOSTIM | STOPIM | STARTIM | NACKIM | DMATXIM | DMARXIM | CLKIM | IM |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RXFFIM | R/W | 0h | Receive FIFO Full Interrupt Mask Value Description 0 The RXFFRIS interrupt is suppressed and not sent to the interrupt controller. 1 The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
10 | TXFEIM | R/W | 0h | Transmit FIFO Empty Interrupt Mask The TXFEIM interrupt mask bit in the I2CMIMR register should be clear (masking the TXFE interrupt) when the master is performing an RX Burst from the RXFIFO and should be unmasked before starting a TX FIFO transfers. Value Description 0 The TXFERIS interrupt is suppressed and not sent to the interrupt controller. 1 The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
9 | RXIM | R/W | 0h | Receive FIFO Request Interrupt Mask Value Description 0 The RXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
8 | TXIM | R/W | 0h | Transmit FIFO Request Interrupt Mask Value Description 0 The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
7 | ARBLOSTIM | R/W | 0h | Arbitration Lost Interrupt Mask Value Description 0 The ARBLOSTRIS interrupt is suppressed and not sent to the interrupt controller. 1 The Arbitration Lost interrupt is sent to the interrupt controller when the ARBLOSTRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
6 | STOPIM | R/W | 0h | STOP Detection Interrupt Mask Value Description 0 The STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1 The STOP detection interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
5 | STARTIM | R/W | 0h | START Detection Interrupt Mask Value Description 0 The STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1 The START detection interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
4 | NACKIM | R/W | 0h | Address/Data NACK Interrupt Mask Value Description 0 The NACKRIS interrupt is suppressed and not sent to the interrupt controller. 1 The address/data NACK interrupt is sent to the interrupt controller when the NACKRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
3 | DMATXIM | R/W | 0h | Transmit DMA Interrupt Mask Value Description 0 The DMATXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
2 | DMARXIM | R/W | 0h | Receive DMA Interrupt Mask Value Description 0 The DMARXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
1 | CLKIM | R/W | 0h | Clock Timeout Interrupt Mask Value Description 0 The CLKRIS interrupt is suppressed and not sent to the interrupt controller. 1 The clock timeout interrupt is sent to the interrupt controller when the CLKRIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
0 | IM | R/W | 0h | Master Interrupt Mask Value Description 0 The RIS interrupt is suppressed and not sent to the interrupt controller. 1 The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set. Reset type: PER.RESET |
I2CMRIS is shown in Figure 46-21 and described in Table 46-11.
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I2C Master Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFRIS | TXFERIS | RXRIS | TXRIS | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARBLOSTRIS | STOPRIS | STARTRIS | NACKRIS | DMATXRIS | DMARXRIS | CLKRIS | RIS |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RXFFRIS | R | 0h | Receive FIFO Full Raw Interrupt Status Value Description 0 No interrupt 1 The Receive FIFO Full interrupt is pending. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register. Reset type: PER.RESET |
10 | TXFERIS | R | 0h | Transmit FIFO Empty Raw Interrupt Status Value Description 0 No interrupt 1 The Transmit FIFO Empty interrupt is pending. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register. Note that if we clear the TXFERIS interrupt (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation. Reset type: PER.RESET |
9 | RXRIS | R | 0h | Receive FIFO Request Raw Interrupt Status Value Description 0 No interrupt 1 The trigger level for the RX FIFO has been reached or there is data in the FIFO and the burst count is zero. Thus, a RX FIFO request interrupt is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register. Reset type: PER.RESET |
8 | TXRIS | R | 0h | Transmit Request Raw Interrupt Status Value Description 0 No interrupt 1 The trigger level for the TX FIFO has been reached and more data is needed to complete the burst. Thus, a TX FIFO request interrupt is pending. This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register. Reset type: PER.RESET |
7 | ARBLOSTRIS | R | 0h | Arbitration Lost Raw Interrupt Status Value Description 0 No interrupt 1 The Arbitration Lost interrupt is pending. This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. Reset type: PER.RESET |
6 | STOPRIS | R | 0h | STOP Detection Raw Interrupt Status Value Description 0 No interrupt 1 The STOP Detection interrupt is pending. This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register. Reset type: PER.RESET |
5 | STARTRIS | R | 0h | START Detection Raw Interrupt Status Value Description 0 No interrupt 1 The START Detection interrupt is pending. This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register. Reset type: PER.RESET |
4 | NACKRIS | R | 0h | Address/Data NACK Raw Interrupt Status Value Description 0 No interrupt 1 The address/data NACK interrupt is pending. This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register. Reset type: PER.RESET |
3 | DMATXRIS | R | 0h | Transmit DMA Raw Interrupt Status Value Description 0 No interrupt. 1 The transmit DMA complete interrupt is pending. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register. Reset type: PER.RESET |
2 | DMARXRIS | R | 0h | Receive DMA Raw Interrupt Status Value Description 0 No interrupt. 1 The receive DMA complete interrupt is pending. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register. Reset type: PER.RESET |
1 | CLKRIS | R | 0h | Clock Timeout Raw Interrupt Status Value Description 0 No interrupt. 1 The clock timeout interrupt is pending. This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. Reset type: PER.RESET |
0 | RIS | R | 0h | Master Raw Interrupt Status This interrupt includes: Master transaction completed Next byte transfer request Value Description 0 No interrupt. 1 A master interrupt is pending. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. Reset type: PER.RESET |
I2CMMIS is shown in Figure 46-22 and described in Table 46-12.
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I2C Master Masked Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFMIS | TXFEMIS | RXMIS | TXMIS | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARBLOSTMIS | STOPMIS | STARTMIS | NACKMIS | DMATXMIS | DMARXMIS | CLKMIS | MIS |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RXFFMIS | R | 0h | Receive FIFO Full Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Receive FIFO Full interrupt was signaled and is pending. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register. Reset type: PER.RESET |
10 | TXFEMIS | R | 0h | Transmit FIFO Empty Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Transmit FIFO Empty interrupt was signaled and is pending. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register. Reset type: PER.RESET |
9 | RXMIS | R | 0h | Receive FIFO Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Receive FIFO Request interrupt was signaled and is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register. Reset type: PER.RESET |
8 | TXMIS | R | 0h | Transmit Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Transmit FIFO Request interrupt was signaled and is pending. This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register. Reset type: PER.RESET |
7 | ARBLOSTMIS | R | 0h | Arbitration Lost Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Arbitration Lost interrupt was signaled and is pending. This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. Reset type: PER.RESET |
6 | STOPMIS | R | 0h | STOP Detection Interrupt Mask Value Description 0 No interrupt. 1 An unmasked STOP Detection interrupt was signaled and is pending. This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register. Reset type: PER.RESET |
5 | STARTMIS | R | 0h | START Detection Interrupt Mask Value Description 0 No interrupt. 1 An unmasked START Detection interrupt was signaled and is pending. This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register. Reset type: PER.RESET |
4 | NACKMIS | R | 0h | Address/Data NACK Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Address/Data NACK interrupt was signaled and is pending. This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register. Reset type: PER.RESET |
3 | DMATXMIS | R | 0h | Transmit DMA Interrupt Status Value Description 0 No interrupt. 1 An unmasked transmit DMA complete interrupt was signaled and is pending. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register. Reset type: PER.RESET |
2 | DMARXMIS | R | 0h | Receive DMA Interrupt Status Value Description 0 No interrupt. 1 An unmasked receive DMA complete interrupt was signaled and is pending. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register. Reset type: PER.RESET |
1 | CLKMIS | R | 0h | Clock Timeout Masked Interrupt Status Value Description 0 No interrupt. 1 An unmasked clock timeout interrupt was signaled and is pending. This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. Reset type: PER.RESET |
0 | MIS | R | 0h | Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked master interrupt was signaled and is pending. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. Reset type: PER.RESET |
I2CMICR is shown in Figure 46-23 and described in Table 46-13.
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I2C Master Interrupt Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFIC | TXFEIC | RXIC | TXIC | |||
R-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARBLOSTIC | STOPIC | STARTIC | NACKIC | DMATXIC | DMARXIC | CLKIC | IC |
R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RXFFIC | R-0/W | 0h | Receive FIFO Full Interrupt Clear Writing a 1 to this bit clears the RXFFIS bit in the I2CMRIS register and the RXFFMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
10 | TXFEIC | R-0/W | 0h | Transmit FIFO Empty Interrupt Clear Writing a 1 to this bit clears the TXFERIS bit in the I2CMRIS register and the TXFEMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
9 | RXIC | R-0/W | 0h | Receive FIFO Request Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the I2CMRIS register and the RXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
8 | TXIC | R-0/W | 0h | Transmit FIFO Request Interrupt Clear Writing a 1 to this bit clears the TXRIS bit in the I2CMRIS register and the TXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
7 | ARBLOSTIC | R-0/W | 0h | Arbitration Lost Interrupt Clear Writing a 1 to this bit clears the ARBLOSTRIS bit in the I2CMRIS register and the ARBLOSTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
6 | STOPIC | R-0/W | 0h | STOP Detection Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CMRIS register and the STOPMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
5 | STARTIC | R-0/W | 0h | START Detection Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
4 | NACKIC | R-0/W | 0h | Address/Data NACK Interrupt Clear Writing a 1 to this bit clears the NACKRIS bit in the I2CMRIS register and the NACKMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
3 | DMATXIC | R-0/W | 0h | Transmit DMA Interrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the I2CMRIS register and the DMATXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
2 | DMARXIC | R-0/W | 0h | Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the I2CMRIS register and the DMARXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
1 | CLKIC | R-0/W | 0h | Clock Timeout Interrupt Clear Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and the CLKMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
0 | IC | R-0/W | 0h | Master Interrupt Clear Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
I2CMCR is shown in Figure 46-24 and described in Table 46-14.
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I2C Master Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SFE | MFE | RESERVED | LPBK | |||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | SFE | R/W | 0h | I2C Slave Function Enable Value Description 0 Slave mode is disabled. 1 Slave mode is enabled. Reset type: PER.RESET |
4 | MFE | R/W | 0h | I2C Master Function Enable Value Description 0 Master mode is disabled. 1 Master mode is enabled. Reset type: PER.RESET |
3-1 | RESERVED | R | 0h | Reserved |
0 | LPBK | R/W | 0h | I2C Loopback Value Description 0 Normal operation. 1 The controller in a test mode loopback configuration. Reset type: PER.RESET |
I2CMCLKOCNT is shown in Figure 46-25 and described in Table 46-15.
Return to the Summary Table.
I2C Master Clock Low Timeout Count
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNTL | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | CNTL | R/W | 0h | I2C Master Count This field contains the upper 8 bits of a 12-bit counter for the clock low timeout count. The value of CNTL must be greater than 0x1. Reset type: PER.RESET |
I2CMBMON is shown in Figure 46-26 and described in Table 46-16.
Return to the Summary Table.
I2C Master Bus Monitor
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDA | SCL | |||||||||||||
R-0h | R-1h | R-1h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | SDA | R | 1h | I2C SDA Status Value Description 0 The I2CSDA signal is low. 1 The I2CSDA signal is high. Reset type: PER.RESET |
0 | SCL | R | 1h | I2C SCL Status Value Description 0 The I2CSCL signal is low. 1 The I2CSCL signal is high. Reset type: PER.RESET |
I2CMBLEN is shown in Figure 46-27 and described in Table 46-17.
Return to the Summary Table.
I2C Master Burst Length
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNTL | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | CNTL | R/W | 0h | I2C Burst Length This field contains the programmed length of bytes of the Burst Transaction. If BURST is enabled this register must be set to a non-zero value otherwise an error will occur. Reset type: PER.RESET |
I2CMBCNT is shown in Figure 46-28 and described in Table 46-18.
Return to the Summary Table.
I2C Master Burst Count
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNTL | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | CNTL | R | 0h | I2C Master Burst Count This field contains the current count-down value of the BURST transaction. Reset type: PER.RESET |
I2CSOAR is shown in Figure 46-29 and described in Table 46-19.
Return to the Summary Table.
I2C Slave Own Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OAR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6-0 | OAR | R/W | 0h | I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. Reset type: PER.RESET |
I2CSCSR is shown in Figure 46-30 and described in Table 46-20.
Return to the Summary Table.
I2C Slave Control/Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ACTDMARX | ACTDMATX | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | QCMDRW | QCMDST | OAR2SEL | FBR | TREQ | RREQ | |
R-0h | RC-0h | RC-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ACTDMARX | R | 0h | DMA RX Active Status Value Description 0 DMA RX is not active 1 DMA RX is active. Reset type: PER.RESET |
30 | ACTDMATX | R | 0h | DMA TX Active Status Value Description 0 DMA TX is not active 1 DMA TX is active. Reset type: PER.RESET |
29-6 | RESERVED | R | 0h | Reserved |
5 | QCMDRW | RC | 0h | Quick Command Read / Write Value Description 0 Quick command was a write 1 Quick command was a read This bit only has meaning when the QCMDST bit is set. Reset type: PER.RESET |
4 | QCMDST | RC | 0h | Quick Command Status Value Description 0 The last transaction was a normal transaction or a transaction has not occurred. 1 The last transaction was a Quick Command transaction. Reset type: PER.RESET |
3 | OAR2SEL | R | 0h | OAR2 Address Matched Value Description 0 Either the address is not matched or the match is in legacy mode. 1 OAR2 address matched and ACKed by the slave. This bit gets reevaluated after every address comparison. Reset type: PER.RESET |
2 | FBR | R | 0h | First Byte Received Value Description 0 The first byte has not been received. 1 The first byte following the slave's own address has been received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register. This bit is not used for slave transmit operations. Reset type: PER.RESET |
1 | TREQ | R | 0h | Transmit Request Value Description 0 No outstanding transmit request. 1 The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register. Reset type: PER.RESET |
0 | RREQ | R | 0h | Receive Request Value Description 0 No outstanding receive data. 1 The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register. Reset type: PER.RESET |
I2CSDR is shown in Figure 46-31 and described in Table 46-21.
Return to the Summary Table.
I2C Slave Data
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R/W | 0h | Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. Reset type: PER.RESET |
I2CSIMR is shown in Figure 46-32 and described in Table 46-22.
Return to the Summary Table.
I2C Slave Interrupt Mask
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFIM | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFEIM | RXIM | TXIM | DMATXIM | DMARXIM | STOPIM | STARTIM | DATAIM |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | RXFFIM | R/W | 0h | Receive FIFO Full Interrupt Mask Value Description 0 The RXFFRIS interrupt is suppressed and not sent to the interrupt controller. 1 The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
7 | TXFEIM | R/W | 0h | Transmit FIFO Empty Interrupt Mask Value Description 0 The TXFERIS interrupt is suppressed and not sent to the interrupt controller. 1 The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
6 | RXIM | R/W | 0h | Receive FIFO Request Interrupt Mask Value Description 0 The RXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
5 | TXIM | R/W | 0h | Transmit FIFO Request Interrupt Mask Value Description 0 The TXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
4 | DMATXIM | R/W | 0h | Transmit DMA Interrupt Mask Value Description 0 The DMATXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
3 | DMARXIM | R/W | 0h | Receive DMA Interrupt Mask Value Description 0 The DMARXRIS interrupt is suppressed and not sent to the interrupt controller. 1 The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
2 | STOPIM | R/W | 0h | Stop Condition Interrupt Mask Value Description 0 The STOPRIS interrupt is suppressed and not sent to the interrupt controller. 1 The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
1 | STARTIM | R/W | 0h | Start Condition Interrupt Mask Value Description 0 The STARTRIS interrupt is suppressed and not sent to the interrupt controller. 1 The START condition interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
0 | DATAIM | R/W | 0h | Data Interrupt Mask Value Description 0 The DATARIS interrupt is suppressed and not sent to the interrupt controller. 1 Data interrupt sent to interrupt controller when DATARIS bit in the I2CSRIS register is set. Reset type: PER.RESET |
I2CSRIS is shown in Figure 46-33 and described in Table 46-23.
Return to the Summary Table.
I2C Slave Raw Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFRIS | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFERIS | RXRIS | TXRIS | DMATXRIS | DMARXRIS | STOPRIS | STARTRIS | DATARIS |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | RXFFRIS | R | 0h | Receive FIFO Full Raw Interrupt Status Value Description 0 No interrupt 1 The Receive FIFO Full interrupt is pending. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register. Reset type: PER.RESET |
7 | TXFERIS | R | 0h | Transmit FIFO Empty Raw Interrupt Status Value Description 0 No interrupt 1 The Transmit FIFO Empty interrupt is pending. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register. Note that if the TXFERIS interrupt is cleared (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation. Reset type: PER.RESET |
6 | RXRIS | R | 0h | Receive FIFO Request Raw Interrupt Status Value Description 0 No interrupt 1 The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register. Reset type: PER.RESET |
5 | TXRIS | R | 0h | Transmit Request Raw Interrupt Status Value Description 0 No interrupt 1 The trigger value for the FIFO has been reached and a TX FIFO Request interrupt is pending. This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register. Reset type: PER.RESET |
4 | DMATXRIS | R | 0h | Transmit DMA Raw Interrupt Status Value Description 0 No interrupt. 1 A transmit DMA complete interrupt is pending. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register. Reset type: PER.RESET |
3 | DMARXRIS | R | 0h | Receive DMA Raw Interrupt Status Value Description 0 No interrupt. 1 A receive DMA complete interrupt is pending. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register. Reset type: PER.RESET |
2 | STOPRIS | R | 0h | Stop Condition Raw Interrupt Status Value Description 0 No interrupt. 1 A STOP condition interrupt is pending. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. Reset type: PER.RESET |
1 | STARTRIS | R | 0h | Start Condition Raw Interrupt Status Value Description 0 No interrupt. 1 A START condition interrupt is pending. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. Reset type: PER.RESET |
0 | DATARIS | R | 0h | Data Raw Interrupt Status This interrupt encompasses the following: Slave transaction received Slave transaction requested Next byte transfer request Value Description 0 No interrupt. 1 Slave Interrupt is pending. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. Reset type: PER.RESET |
I2CSMIS is shown in Figure 46-34 and described in Table 46-24.
Return to the Summary Table.
I2C Slave Masked Interrupt Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFMIS | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFEMIS | RXMIS | TXMIS | DMATXMIS | DMARXMIS | STOPMIS | STARTMIS | DATAMIS |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | RXFFMIS | R | 0h | Receive FIFO Full Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Receive FIFO Full interrupt was signaled and is pending. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register. Reset type: PER.RESET |
7 | TXFEMIS | R | 0h | Transmit FIFO Empty Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Transmit FIFO Empty interrupt was signaled and is pending. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register. Reset type: PER.RESET |
6 | RXMIS | R | 0h | Receive FIFO Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Receive FIFO Request interrupt was signaled and is pending. This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register. Reset type: PER.RESET |
5 | TXMIS | R | 0h | Transmit FIFO Request Interrupt Mask Value Description 0 No interrupt. 1 An unmasked Transmit FIFO Request interrupt was signaled and is pending. This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register. Reset type: PER.RESET |
4 | DMATXMIS | R | 0h | Transmit DMA Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked transmit DMA complete interrupt was signaled is pending. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register. Reset type: PER.RESET |
3 | DMARXMIS | R | 0h | Receive DMA Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked receive DMA complete interrupt was signaled is pending. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register. Reset type: PER.RESET |
2 | STOPMIS | R | 0h | Stop Condition Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked STOP condition interrupt was signaled is pending. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. Reset type: PER.RESET |
1 | STARTMIS | R | 0h | Start Condition Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked START condition interrupt was signaled is pending. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. Reset type: PER.RESET |
0 | DATAMIS | R | 0h | Data Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked slave data interrupt was signaled is pending. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. Reset type: PER.RESET |
I2CSICR is shown in Figure 46-35 and described in Table 46-25.
Return to the Summary Table.
I2C Slave Interrupt Clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFIC | ||||||
R-0h | R-0/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFEIC | RXIC | TXIC | DMATXIC | DMARXIC | STOPIC | STARTIC | DATAIC |
R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | RXFFIC | R-0/W | 0h | Receive FIFO Full Interrupt Mask Writing a 1 to this bit clears the RXFFIS bit in the I2CSRIS register and the RXFFMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
7 | TXFEIC | R-0/W | 0h | Transmit FIFO Empty Interrupt Mask Writing a 1 to this bit clears the TXFERIS bit in the I2CSRIS register and the TXFEMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
6 | RXIC | R-0/W | 0h | Receive Request Interrupt Mask Writing a 1 to this bit clears the RXRIS bit in the I2CSRIS register and the RXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
5 | TXIC | R-0/W | 0h | Transmit Request Interrupt Mask Writing a 1 to this bit clears the TXRIS bit in the I2CSRIS register and the TXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
4 | DMATXIC | R-0/W | 0h | Transmit DMA Interrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the I2CSRIS register and the DMATXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
3 | DMARXIC | R-0/W | 0h | Receive DMA Interrupt Clear Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
2 | STOPIC | R-0/W | 0h | Stop Condition Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
1 | STARTIC | R-0/W | 0h | Start Condition Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
0 | DATAIC | R-0/W | 0h | Data Interrupt Clear Writing a 1 to this bit clears the DATARIS bit in the I2CSRIS register and the DATMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. Reset type: PER.RESET |
I2CSOAR2 is shown in Figure 46-36 and described in Table 46-26.
Return to the Summary Table.
I2C Slave Own Address 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OAR2EN | OAR2 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7 | OAR2EN | R/W | 0h | I2C Slave Own Address 2 Enable Value Description 0 The alternate address is disabled. 1 Enables the use of the alternate address in the OAR2 field. Reset type: PER.RESET |
6-0 | OAR2 | R/W | 0h | I2C Slave Own Address 2 This field specifies the alternate OAR2 address. Reset type: PER.RESET |
I2CSACKCTL is shown in Figure 46-37 and described in Table 46-27.
Return to the Summary Table.
I2C Slave ACK Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACKOVAL | ACKOEN | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | ACKOVAL | R/W | 0h | I2C Slave ACK Override Value Value Description 0 An ACK is sent indicating valid data or command. 1 A NACK is sent indicating invalid data or command. Reset type: PER.RESET |
0 | ACKOEN | R/W | 0h | I2C Slave ACK Override Enable Value Description 0 A response in not provided. 1 An ACK or NACK is sent according to the value written to the ACKOVAL bit. Reset type: PER.RESET |
I2CFIFODATARX is shown in Figure 46-38 and described in Table 46-28.
Return to the Summary Table.
I2C FIFO Data RX
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R | 0h | I2C RX FIFO Read Data Byte This field contains the current byte being read in the RX FIFO stack. Reset type: PER.RESET |
I2CFIFOCTL is shown in Figure 46-39 and described in Table 46-29.
Return to the Summary Table.
I2C FIFO Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RXASGNMT | RXFLUSH | DMARXENA | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RXTRIG | ||||||
R-0h | R/W-4h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXASGNMT | TXFLUSH | DMATXENA | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXTRIG | ||||||
R-0h | R/W-4h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RXASGNMT | R/W | 0h | RX Control Assignment Value Description 0 RX FIFO is assigned to Master 1 RX FIFO is assigned to Slave Reset type: PER.RESET |
30 | RXFLUSH | R/W | 0h | RX FIFO Flush Setting this bit will Flush the RX FIFO. This bit will self-clear when the flush has completed. Reset type: PER.RESET |
29 | DMARXENA | R/W | 0h | DMA RX Channel Enable Value Description 0 DMA RX channel disabled 1 DMA RX channel enabled Reset type: PER.RESET |
28-19 | RESERVED | R | 0h | Reserved |
18-16 | RXTRIG | R/W | 4h | RX FIFO Trigger Indicates at what fill level the RX FIFO will generate a trigger. Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. Value Description 0x0 Trigger when RX FIFO contains no bytes 0x1 Trigger when Rx FIFO contains 1 or more bytes 0x2 Trigger when Rx FIFO contains 2 or more bytes 0x3 Trigger when Rx FIFO contains 3 or more bytes 0x4 Trigger when Rx FIFO contains 4 or more bytes 0x5 Trigger when Rx FIFO contains 5 or more bytes 0x6 Trigger when Rx FIFO contains 6 or more bytes 0x7 Trigger when Rx FIFO contains 7 or more bytes. Reset type: PER.RESET |
15 | TXASGNMT | R/W | 0h | TX Control Assignment Value Description 0 TX FIFO is assigned to Master 1 TX FIFO is assigned to Slave Reset type: PER.RESET |
14 | TXFLUSH | R/W | 0h | TX FIFO Flush Setting this bit will Flush the TX FIFO. This bit will self-clear when the flush has completed. Reset type: PER.RESET |
13 | DMATXENA | R/W | 0h | DMA TX Channel Enable Value Description 0 DMA TX channel disabled 1 DMA TX channel enabled Reset type: PER.RESET |
12-3 | RESERVED | R | 0h | Reserved |
2-0 | TXTRIG | R/W | 4h | TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. Value Description 0x0 Trigger when the TX FIFO is empty. 0x1 Trigger when TX FIFO contains ≤ 1 byte 0x2 Trigger when TX FIFO contains ≤ 2 bytes 0x3 Trigger when TX FIFO ≤ 3 bytes 0x4 Trigger when FIFO ≤ 4 bytes 0x5 Trigger when FIFO ≤ 5 bytes 0x6 Trigger when FIFO ≤ 6 bytes 0x7 Trigger when FIFO ≤ 7 bytes Reset type: PER.RESET |
I2CFIFOSTATUS is shown in Figure 46-40 and described in Table 46-30.
Return to the Summary Table.
I2C FIFO Status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RXABVTRIG | RXFF | RXFE | ||||
R-0h | R-0h | R-0h | R-1h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXBLWTRIG | TXFF | TXFE | ||||
R-0h | R-1h | R-0h | R-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18 | RXABVTRIG | R | 0h | RX FIFO Above Trigger Level Value Description 0 The number of bytes in RX FIFO is below the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register 1 The number of bytes in the RX FIFO is above the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register Reset type: PER.RESET |
17 | RXFF | R | 0h | RX FIFO Full Value Description 0 The RX FIFO is not full. 1 The RX FIFO is full. Reset type: PER.RESET |
16 | RXFE | R | 1h | RX FIFO Empty Value Description 0 The RX FIFO is not empty. 1 The RX FIFO is empty. Reset type: PER.RESET |
15-3 | RESERVED | R | 0h | Reserved |
2 | TXBLWTRIG | R | 1h | TX FIFO Below Trigger Level Value Description 0 The number of bytes in TX FIFO is above the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register 1 The number of bytes in the TX FIFO is below the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register Reset type: PER.RESET |
1 | TXFF | R | 0h | TX FIFO Full Value Description 0 The TX FIFO is not full. 1 The TX FIFO is full. Reset type: PER.RESET |
0 | TXFE | R | 1h | TX FIFO Empty Value Description 0 The TX FIFO is not empty. 1 The TX FIFO is empty. Reset type: PER.RESET |
I2CPP is shown in Figure 46-41 and described in Table 46-31.
Return to the Summary Table.
I2C Peripheral Properties
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HS | ||||||||||||||
R-0h | R-1h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | HS | R | 1h | High-Speed Capable Value Description 0 The interface is capable of Standard, Fast, or Fast mode plus operation. 1 The interface is capable of High-Speed operation. Reset type: PER.RESET |
I2CPC is shown in Figure 46-42 and described in Table 46-32.
Return to the Summary Table.
I2C Peripheral Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HS | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | HS | R/W | 1h | High-Speed Capable Value Description 0 The interface is set to Standard, Fast or Fast mode plus operation. 1 The interface is set to High-Speed operation. Note that this encoding may only be used if the HS bit in the I2CPP register is set. Otherwise, this encoding is not available. Reset type: PER.RESET |