SPRUII0F May   2019  â€“ June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C28x SYSTEM RESOURCES
    1. 1.1 Technical Reference Manual Overview
  4. 2 C2000â„¢ Microcontrollers Software Support
    1. 2.1 Introduction
    2. 2.2 C2000Ware Structure
    3. 2.3 Documentation
    4. 2.4 Devices
    5. 2.5 Libraries
    6. 2.6 Code Composer Studioâ„¢ Integrated Development Environment (IDE)
    7. 2.7 SysConfig and PinMUX Tool
  5. 3 C28x System Control and Interrupts
    1. 3.1  C28x System Control Introduction
      1. 3.1.1 SYSCTL Related Collateral
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRSn)
      3. 3.3.3  Simulate External Reset
      4. 3.3.4  Power-On Reset (POR)
      5. 3.3.5  Debugger Reset (SYSRS)
      6. 3.3.6  Simulate CPU1 Reset
      7. 3.3.7  Watchdog Reset (WDRS)
      8. 3.3.8  NMI Watchdog Reset (NMIWDRS)
      9. 3.3.9  Secure Code Copy Reset (SCCRESET)
      10. 3.3.10 ESC Reset Output
      11. 3.3.11 Test Reset (TRST)
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 System Error and CM Status Interrupts
      7. 3.4.7 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1  Missing Clock Detection
        2. 3.5.3.2  RAM Uncorrectable Error
        3. 3.5.3.3  Flash Uncorrectable ECC Error
        4. 3.5.3.4  ROM Uncorrectable Error
        5. 3.5.3.5  NMI Vector Fetch Mismatch
        6. 3.5.3.6  CPU2 Watchdog or NMI Watchdog Reset
        7. 3.5.3.7  CM NMI Watchdog Reset
        8. 3.5.3.8  EtherCAT Reset out
        9. 3.5.3.9  CRC Fail
        10. 3.5.3.10 ERAD NMI
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check
      3. 3.6.3 NMIWDs
      4. 3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection
      5. 3.6.5 ECC Enabled Flash Memory
      6. 3.6.6 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 External Clock Output (XCLKOUT)
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 PLL/AUXPLL
        1. 3.7.6.1 Choosing PLL Settings
        2. 3.7.6.2 System Clock Setup
        3. 3.7.6.3 USB Auxiliary Clock Setup
        4. 3.7.6.4 SYS PLL / AUX PLL Bypass
      7. 3.7.7 Clock (OSCCLK) Failure Detection
        1. 3.7.7.1 Missing Clock Detection Logic
    8. 3.8  Clock Configuration Semaphore
    9. 3.9  32-Bit CPU Timers 0/1/2
    10. 3.10 Watchdog Timers
      1. 3.10.1 Servicing the Watchdog Timer
      2. 3.10.2 Minimum Window Check
      3. 3.10.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.10.4 Watchdog Operation in Low-Power Modes
      5. 3.10.5 Emulation Considerations
    11. 3.11 Low-Power Modes
      1. 3.11.1 IDLE
      2. 3.11.2 STANDBY
    12. 3.12 Memory Controller Module
      1. 3.12.1 Functional Description
        1. 3.12.1.1  Dedicated RAM (Dx RAM)
        2. 3.12.1.2  Local Shared RAM (LSx RAM)
        3. 3.12.1.3  Global Shared RAM (GSx RAM)
        4. 3.12.1.4  CPU Message RAM (CPU MSG RAM)
        5. 3.12.1.5  CLA Message RAM (CLA MSGRAM)
        6. 3.12.1.6  CLA-DMA MSG RAM
        7. 3.12.1.7  Access Arbitration
        8. 3.12.1.8  Access Protection
          1. 3.12.1.8.1 CPU Fetch Protection
          2. 3.12.1.8.2 CPU Write Protection
          3. 3.12.1.8.3 CPU Read Protection
          4. 3.12.1.8.4 CLA Fetch Protection
          5. 3.12.1.8.5 CLA Write Protection
          6. 3.12.1.8.6 CLA Read Protection
          7. 3.12.1.8.7 DMA Write Protection
        9. 3.12.1.9  Memory Error Detection, Correction and Error Handling
          1. 3.12.1.9.1 Error Detection and Correction
          2. 3.12.1.9.2 Error Handling
        10. 3.12.1.10 Application Test Hooks for Error Detection and Correction
        11. 3.12.1.11 ROM Test
        12. 3.12.1.12 RAM Initialization
    13. 3.13 JTAG
      1. 3.13.1 JTAG Noise and TAP_STATUS
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 Software
      1. 3.15.1 SYSCTL Examples
        1. 3.15.1.1 Missing clock detection (MCD)
        2. 3.15.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.15.2 MEMCFG Examples
        1. 3.15.2.1 Correctable & Uncorrectable Memory Error Handling
        2. 3.15.2.2 Shared RAM Management (CPU1) - C28X_DUAL
        3. 3.15.2.3 Shared RAM Management (CPU2) - C28X_DUAL
        4. 3.15.2.4 Demonstrate memconfig diagnostics and error handling. - CM
        5. 3.15.2.5 Shared RAM Management (CPU1) - C28X_DUAL
        6. 3.15.2.6 Shared RAM Management (CPU2) - C28X_DUAL
      3. 3.15.3 NMI Examples
        1. 3.15.3.1 NMI handling - C28X_DUAL
        2. 3.15.3.2 Watchdog Reset - C28X_DUAL
        3. 3.15.3.3 NMI handling - C28X_DUAL
        4. 3.15.3.4 Watchdog Reset - C28X_DUAL
      4. 3.15.4 TIMER Examples
        1. 3.15.4.1 CPU Timers
        2. 3.15.4.2 CPU Timers - CM
        3. 3.15.4.3 CPU Timers
      5. 3.15.5 WATCHDOG Examples
        1. 3.15.5.1 Watchdog
        2. 3.15.5.2 Windowed watchdog expiry with NMI handling - CM
    16. 3.16 System Control Registers
      1. 3.16.1  SYSCTRL Base Address Table (C28)
      2. 3.16.2  ACCESS_PROTECTION_REGS Registers
      3. 3.16.3  CLK_CFG_REGS Registers
      4. 3.16.4  CM_CONF_REGS Registers
      5. 3.16.5  CPU_SYS_REGS Registers
      6. 3.16.6  CPU_ID_REGS Registers
      7. 3.16.7  CPU1_PERIPH_AC_REGS Registers
      8. 3.16.8  CPUTIMER_REGS Registers
      9. 3.16.9  DEV_CFG_REGS Registers
      10. 3.16.10 DMA_CLA_SRC_SEL_REGS Registers
      11. 3.16.11 MEM_CFG_REGS Registers
      12. 3.16.12 MEMORY_ERROR_REGS Registers
      13. 3.16.13 NMI_INTRUPT_REGS Registers
      14. 3.16.14 PIE_CTRL_REGS Registers
      15. 3.16.15 ROM_PREFETCH_REGS Registers
      16. 3.16.16 ROM_WAIT_STATE_REGS Registers
      17. 3.16.17 SYNC_SOC_REGS Registers
      18. 3.16.18 SYS_STATUS_REGS Registers
      19. 3.16.19 TEST_ERROR_REGS Registers
      20. 3.16.20 UID_REGS Registers
      21. 3.16.21 WD_REGS Registers
      22. 3.16.22 XINT_REGS Registers
      23. 3.16.23 Register to Driverlib Function Mapping
        1. 3.16.23.1 ASYSCTL Registers to Driverlib Functions
        2. 3.16.23.2 CPUTIMER Registers to Driverlib Functions
        3. 3.16.23.3 DCSM Registers to Driverlib Functions
        4. 3.16.23.4 MEMCFG Registers to Driverlib Functions
        5. 3.16.23.5 NMI Registers to Driverlib Functions
        6. 3.16.23.6 PIE Registers to Driverlib Functions
        7. 3.16.23.7 SYSCTL Registers to Driverlib Functions
        8. 3.16.23.8 WWD Registers to Driverlib Functions
        9. 3.16.23.9 XINT Registers to Driverlib Functions
  6. 4 C28x Processor
    1. 4.1 Introduction
    2. 4.2 C28X Related Collateral
    3. 4.3 Features
    4. 4.4 Floating-Point Unit
    5. 4.5 Trigonometric Math Unit (TMU)
    6. 4.6 VCRC Unit
  7. 5 ROM Code and Peripheral Booting
    1. 5.1 Introduction
      1. 5.1.1 ROM Related Collateral
    2. 5.2 Device Boot Sequence
    3. 5.3 Device Boot Modes
    4. 5.4 Device Boot Configurations
      1. 5.4.1 Configuring Boot Mode Pins for CPU1
      2. 5.4.2 Configuring Boot Mode Table Options for CPU1
      3. 5.4.3 Boot Mode Example Use Cases
        1. 5.4.3.1 Zero Boot Mode Select Pins
        2. 5.4.3.2 One Boot Mode Select Pin
        3. 5.4.3.3 Three Boot Mode Select Pins
    5. 5.5 Device Boot Flow Diagrams
      1. 5.5.1 CPU1 Boot Flow
      2. 5.5.2 CPU2 Boot Flow
      3. 5.5.3 Connectivity Manager (CM) Boot Flow
    6. 5.6 Device Reset and Exception Handling
      1. 5.6.1 Reset Causes and Handling
      2. 5.6.2 Exceptions and Interrupts Handling
    7. 5.7 Boot ROM Description
      1. 5.7.1  CPU1 Boot ROM Configuration Registers
        1. 5.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 5.7.2  Booting CPU2 and CM
        1. 5.7.2.1 Boot Up Procedure
        2. 5.7.2.2 IPCBOOTMODE Details
        3. 5.7.2.3 Error IPC Command Table
      3. 5.7.3  Entry Points
      4. 5.7.4  Wait Points
      5. 5.7.5  Memory Maps
        1. 5.7.5.1 Boot ROM Memory Maps
        2. 5.7.5.2 CLA Data ROM Memory Maps
        3. 5.7.5.3 Reserved RAM Memory Maps
      6. 5.7.6  ROM Tables
      7. 5.7.7  Boot Modes and Loaders
        1. 5.7.7.1 Boot Modes
          1. 5.7.7.1.1 Wait Boot
          2. 5.7.7.1.2 Flash Boot
          3. 5.7.7.1.3 Secure Flash Boot
            1. 5.7.7.1.3.1 Secure Flash CPU1 Linker File Example
          4. 5.7.7.1.4 RAM Boot
          5. 5.7.7.1.5 User OTP Boot
          6. 5.7.7.1.6 IPC Message Copy to RAM Boot
        2. 5.7.7.2 Bootloaders
          1. 5.7.7.2.1 SCI Boot Mode
          2. 5.7.7.2.2 SPI Boot Mode
          3. 5.7.7.2.3 I2C Boot Mode
          4. 5.7.7.2.4 Parallel Boot Mode
          5. 5.7.7.2.5 CAN Boot Mode
          6. 5.7.7.2.6 USB Boot Mode
      8. 5.7.8  GPIO Assignments for CPU1
      9. 5.7.9  Secure ROM Function APIs
      10. 5.7.10 Clock Initializations
      11. 5.7.11 Boot Status information
        1. 5.7.11.1 CPU1 Booting Status
        2. 5.7.11.2 CPU2 Booting Status
        3. 5.7.11.3 CM Booting Status
        4. 5.7.11.4 Boot Mode and MPOST (Memory Power On Self-Test) Status
      12. 5.7.12 ROM Version
    8. 5.8 Application Notes for Using the Bootloaders
      1. 5.8.1 Boot Data Stream Structure
        1. 5.8.1.1 Bootloader Data Stream Structure
          1. 5.8.1.1.1 Data Stream Structure 8-bit
      2. 5.8.2 The C2000 Hex Utility
        1. 5.8.2.1 HEX2000.exe Command Syntax
    9. 5.9 Software
      1. 5.9.1 BOOT Examples
        1. 5.9.1.1 CM Secure Flash Boot
        2. 5.9.1.2 CPU1 Secure Flash Boot
        3. 5.9.1.3 CPU2 Secure Flash Boot
  8. 6 Dual Code Security Module (DCSM)
    1. 6.1 Introduction
      1. 6.1.1 DCSM Related Collateral
    2. 6.2 Functional Description
      1. 6.2.1 CSM Passwords
      2. 6.2.2 Emulation Code Security Logic (ECSL)
      3. 6.2.3 CPU Secure Logic
      4. 6.2.4 Execute-Only Protection
      5. 6.2.5 Password Lock
      6. 6.2.6 JTAGLOCK
      7. 6.2.7 Link Pointer and Zone Select
      8. 6.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 6.3 Flash and OTP Erase/Program
    4. 6.4 Secure Copy Code
    5. 6.5 SecureCRC
    6. 6.6 CSM Impact on Other On-Chip Resources
    7. 6.7 Incorporating Code Security in User Applications
      1. 6.7.1 Environments That Require Security Unlocking
      2. 6.7.2 CSM Password Match Flow
      3. 6.7.3 C Code Example to Unsecure C28x Zone1
      4. 6.7.4 C Code Example to Resecure C28x Zone1
      5. 6.7.5 Environments That Require ECSL Unlocking
      6. 6.7.6 ECSL Password Match Flow
      7. 6.7.7 ECSL Disable Considerations for any Zone
        1. 6.7.7.1 C Code Example to Disable ECSL for C28x-Zone1
      8. 6.7.8 Device Unique ID
    8. 6.8 Software
      1. 6.8.1 DCSM Examples
        1. 6.8.1.1 Empty DCSM Tool Example
        2. 6.8.1.2 DCSM Memory Access control by master CPU1 - C28X_CM
        3. 6.8.1.3 DCSM Memory Access by CPU2 - C28X_DUAL
        4. 6.8.1.4 DCSM Memory Access control by CPU1 - C28X_DUAL
        5. 6.8.1.5 DCSM Memory partitioning Example
        6. 6.8.1.6 DCSM Memory Access by CM - C28X_CM
    9. 6.9 DCSM Registers
      1. 6.9.1 DCSM Base Address Table (C28)
      2. 6.9.2 CM DCSM Base Address Table (CM)
      3. 6.9.3 DCSM_Z1_REGS Registers
      4. 6.9.4 DCSM_Z2_REGS Registers
      5. 6.9.5 DCSM_COMMON_REGS Registers
      6. 6.9.6 DCSM_Z1_OTP Registers
      7. 6.9.7 DCSM_Z2_OTP Registers
  9. 7 Background CRC-32 (BGCRC)
    1. 7.1 Introduction
      1. 7.1.1 BGCRC Related Collateral
      2. 7.1.2 Features
      3. 7.1.3 Block Diagram
      4. 7.1.4 Memory Wait States and Memory Map
    2. 7.2 Functional Description
      1. 7.2.1 Data Read Unit
      2. 7.2.2 CRC-32 Compute Unit
      3. 7.2.3 CRC Notification Unit
        1. 7.2.3.1 CPU Interrupt, CLA Task and NMI
      4. 7.2.4 Operating Modes
        1. 7.2.4.1 CRC Mode
        2. 7.2.4.2 Scrub Mode
      5. 7.2.5 BGCRC Watchdog
      6. 7.2.6 Hardware and Software Faults Protection
    3. 7.3 Application of the BGCRC
      1. 7.3.1 Software Configuration
      2. 7.3.2 Decision on Error Response Severity
      3. 7.3.3 Decision of Controller for CLA_CRC
      4. 7.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 7.3.5 BGCRC Execution
      6. 7.3.6 Debug/Error Response for BGCRC Errors
      7. 7.3.7 BGCRC Golden CRC-32 Value Computation
    4. 7.4 Software
      1. 7.4.1 BGCRC Examples
        1. 7.4.1.1 BGCRC CPU Interrupt Example
        2. 7.4.1.2 BGCRC Example with Watchdog and Lock
        3. 7.4.1.3 CLA-BGCRC Example in CRC mode
        4. 7.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 7.5 BGCRC Registers
      1. 7.5.1 BGCRC Base Address Table (C28)
      2. 7.5.2 BGCRC_REGS Registers
      3. 7.5.3 BGCRC Registers to Driverlib Functions
  10. 8 Control Law Accelerator (CLA)
    1. 8.1 Introduction
      1. 8.1.1 Features
      2. 8.1.2 CLA Related Collateral
      3. 8.1.3 Block Diagram
    2. 8.2 CLA Interface
      1. 8.2.1 CLA Memory
      2. 8.2.2 CLA Memory Bus
      3. 8.2.3 Shared Peripherals and EALLOW Protection
      4. 8.2.4 CLA Tasks and Interrupt Vectors
      5. 8.2.5 CLA Software Interrupt to CPU
    3. 8.3 CLA, DMA, and CPU Arbitration
      1. 8.3.1 CLA Message RAM
      2. 8.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 8.4 CLA Configuration and Debug
      1. 8.4.1 Building a CLA Application
      2. 8.4.2 Typical CLA Initialization Sequence
      3. 8.4.3 Debugging CLA Code
        1. 8.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 8.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)
      4. 8.4.4 CLA Illegal Opcode Behavior
      5. 8.4.5 Resetting the CLA
    5. 8.5 Pipeline
      1. 8.5.1 Pipeline Overview
      2. 8.5.2 CLA Pipeline Alignment
        1. 8.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       379
        3. 8.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       381
        5. 8.5.2.3 ADC Early Interrupt to CLA Response
      3. 8.5.3 Parallel Instructions
        1. 8.5.3.1 Math Operation with Parallel Load
        2. 8.5.3.2 Multiply with Parallel Add
      4. 8.5.4 CLA Task Execution Latency
    6. 8.6 Software
      1. 8.6.1 CLA Examples
        1. 8.6.1.1  CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 8.6.1.2  CLA arcsine(x) using a lookup table (cla_asin_cpu01) - C28X_DUAL
        3. 8.6.1.3  CLA Arcsine Example. - C28X_DUAL
        4. 8.6.1.4  CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        5. 8.6.1.5  CLA 2 Pole 2 Zero Infinite Impulse Response Filter (cla_iir2p2z_cpu01) - C28X_DUAL
        6. 8.6.1.6  CLA 2-pole 2-zero IIR Filter Example for F2837xD. - C28X_DUAL
        7. 8.6.1.7  CLA background nesting task
        8. 8.6.1.8  Controlling PWM output using CLA
        9. 8.6.1.9  Just-in-time ADC sampling with CLA
        10. 8.6.1.10 Optimal offloading of control algorithms to CLA
        11. 8.6.1.11 Handling shared resources across C28x and CLA
    7. 8.7 Instruction Set
      1. 8.7.1 Instruction Descriptions
      2. 8.7.2 Addressing Modes and Encoding
      3. 8.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest {, CNDF}
        11.       MCCNDD 16BitDest {, CNDF}
        12.       MCLRC BGINTM
        13.       MCMP32 MRa, MRb
        14.       MCMPF32 MRa, MRb
        15.       MCMPF32 MRa, #16FHi
        16.       MDEBUGSTOP
        17.       MDEBUGSTOP1
        18.       MEALLOW
        19.       MEDIS
        20.       MEINVF32 MRa, MRb
        21.       MEISQRTF32 MRa, MRb
        22.       MF32TOI16 MRa, MRb
        23.       MF32TOI16R MRa, MRb
        24.       MF32TOI32 MRa, MRb
        25.       MF32TOUI16 MRa, MRb
        26.       MF32TOUI16R MRa, MRb
        27.       MF32TOUI32 MRa, MRb
        28.       MFRACF32 MRa, MRb
        29.       MI16TOF32 MRa, MRb
        30.       MI16TOF32 MRa, mem16
        31.       MI32TOF32 MRa, mem32
        32.       MI32TOF32 MRa, MRb
        33.       MLSL32 MRa, #SHIFT
        34.       MLSR32 MRa, #SHIFT
        35.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        36.       MMAXF32 MRa, MRb
        37.       MMAXF32 MRa, #16FHi
        38.       MMINF32 MRa, MRb
        39.       MMINF32 MRa, #16FHi
        40.       MMOV16 MARx, MRa, #16I
        41.       MMOV16 MARx, mem16
        42.       MMOV16 mem16, MARx
        43.       MMOV16 mem16, MRa
        44.       MMOV32 mem32, MRa
        45.       MMOV32 mem32, MSTF
        46.       MMOV32 MRa, mem32 {, CNDF}
        47.       MMOV32 MRa, MRb {, CNDF}
        48.       MMOV32 MSTF, mem32
        49.       MMOVD32 MRa, mem32
        50.       MMOVF32 MRa, #32F
        51.       MMOVI16 MARx, #16I
        52.       MMOVI32 MRa, #32FHex
        53.       MMOVIZ MRa, #16FHi
        54.       MMOVZ16 MRa, mem16
        55.       MMOVXI MRa, #16FLoHex
        56.       MMPYF32 MRa, MRb, MRc
        57.       MMPYF32 MRa, #16FHi, MRb
        58.       MMPYF32 MRa, MRb, #16FHi
        59.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        60.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        61.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        62.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        63.       MNEGF32 MRa, MRb{, CNDF}
        64.       MNOP
        65.       MOR32 MRa, MRb, MRc
        66.       MRCNDD {CNDF}
        67.       MSETC BGINTM
        68.       MSETFLG FLAG, VALUE
        69.       MSTOP
        70.       MSUB32 MRa, MRb, MRc
        71.       MSUBF32 MRa, MRb, MRc
        72.       MSUBF32 MRa, #16FHi, MRb
        73.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        74.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        75.       MSWAPF MRa, MRb {, CNDF}
        76.       MTESTTF CNDF
        77.       MUI16TOF32 MRa, mem16
        78.       MUI16TOF32 MRa, MRb
        79.       MUI32TOF32 MRa, mem32
        80.       MUI32TOF32 MRa, MRb
        81.       MXOR32 MRa, MRb, MRc
    8. 8.8 CLA Registers
      1. 8.8.1 CLA Base Address Table (C28)
      2. 8.8.2 CLA_ONLY_REGS Registers
      3. 8.8.3 CLA_SOFTINT_REGS Registers
      4. 8.8.4 CLA_REGS Registers
      5. 8.8.5 CLA Registers to Driverlib Functions
  11. 9 Configurable Logic Block (CLB)
    1. 9.1  Introduction
      1. 9.1.1 CLB Related Collateral
    2. 9.2  Description
      1. 9.2.1 CLB Clock
    3. 9.3  CLB Input/Output Connection
      1. 9.3.1 Overview
      2. 9.3.2 CLB Input Selection
      3. 9.3.3 CLB Output Selection
      4. 9.3.4 CLB Output Signal Multiplexer
    4. 9.4  CLB Tile
      1. 9.4.1 Static Switch Block
      2. 9.4.2 Counter Block
        1. 9.4.2.1 Counter Description
        2. 9.4.2.2 Counter Operation
        3. 9.4.2.3 Serializer Mode
        4. 9.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 9.4.3 FSM Block
      4. 9.4.4 LUT4 Block
      5. 9.4.5 Output LUT Block
      6. 9.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 9.4.7 High Level Controller (HLC)
        1. 9.4.7.1 High Level Controller Events
        2. 9.4.7.2 High Level Controller Instructions
        3. 9.4.7.3 <Src> and <Dest>
        4. 9.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 9.5  CPU Interface
      1. 9.5.1 Register Description
      2. 9.5.2 Non-Memory Mapped Registers
    6. 9.6  DMA Access
    7. 9.7  CLB Data Export Through SPI RX Buffer
    8. 9.8  CLB Pipeline Mode
    9. 9.9  Software
      1. 9.9.1 CLB Examples
        1. 9.9.1.1  CLB Empty Project
        2. 9.9.1.2  CLB Combinational Logic
        3. 9.9.1.3  CLB GPIO Input Filter
        4. 9.9.1.4  CLB Auxilary PWM
        5. 9.9.1.5  CLB PWM Protection
        6. 9.9.1.6  CLB Event Window
        7. 9.9.1.7  CLB Signal Generator
        8. 9.9.1.8  CLB State Machine
        9. 9.9.1.9  CLB External Signal AND Gate
        10. 9.9.1.10 CLB Timer
        11. 9.9.1.11 CLB Timer Two States
        12. 9.9.1.12 CLB Interrupt Tag
        13. 9.9.1.13 CLB Output Intersect
        14. 9.9.1.14 CLB PUSH PULL
        15. 9.9.1.15 CLB Multi Tile
        16. 9.9.1.16 CLB Tile to Tile Delay
        17. 9.9.1.17 CLB based One-shot PWM
        18. 9.9.1.18 CLB AOC Control
        19. 9.9.1.19 CLB AOC Release Control
        20. 9.9.1.20 CLB XBARs
        21. 9.9.1.21 CLB AOC Control
        22. 9.9.1.22 CLB Serializer
        23. 9.9.1.23 CLB LFSR
        24. 9.9.1.24 CLB Lock Output Mask
        25. 9.9.1.25 CLB INPUT Pipeline Mode
        26. 9.9.1.26 CLB Clocking and PIPELINE Mode
        27. 9.9.1.27 CLB SPI Data Export
        28. 9.9.1.28 CLB SPI Data Export DMA
        29. 9.9.1.29 CLB Trip Zone Timestamp
        30. 9.9.1.30 CLB CRC
    10. 9.10 CLB Registers
      1. 9.10.1 CLB Base Address Table (C28)
      2. 9.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 9.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 9.10.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 9.10.5 CLB Registers to Driverlib Functions
  12. 10Dual-Clock Comparator (DCC)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Module Operation
      1. 10.2.1 Configuring DCC Counters
      2. 10.2.2 Single-Shot Measurement Mode
      3. 10.2.3 Continuous Monitoring Mode
      4. 10.2.4 Error Conditions
    3. 10.3 Interrupts
    4. 10.4 Software
      1. 10.4.1 DCC Examples
        1. 10.4.1.1 DCC Single shot Clock verification
        2. 10.4.1.2 DCC Single shot Clock measurement
        3. 10.4.1.3 DCC Continuous clock monitoring
        4. 10.4.1.4 DCC Continuous clock monitoring
        5. 10.4.1.5 DCC Detection of clock failure
    5. 10.5 DCC Registers
      1. 10.5.1 DCC Base Address Table (C28)
      2. 10.5.2 DCC_REGS Registers
      3. 10.5.3 DCC Registers to Driverlib Functions
  13. 11Direct Memory Access (DMA)
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Architecture
      1. 11.2.1 Peripheral Interrupt Event Trigger Sources
      2. 11.2.2 DMA Bus
    3. 11.3 Address Pointer and Transfer Control
    4. 11.4 Pipeline Timing and Throughput
    5. 11.5 CPU and CLA Arbitration
    6. 11.6 Channel Priority
      1. 11.6.1 Round-Robin Mode
      2. 11.6.2 Channel 1 High-Priority Mode
    7. 11.7 Overrun Detection Feature
    8. 11.8 Software
      1. 11.8.1 DMA Examples
        1. 11.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 11.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 11.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 11.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
        5. 11.8.1.5 DMA Transfer Shared Peripheral - C28X_DUAL
    9. 11.9 DMA Registers
      1. 11.9.1 DMA Base Address Table (C28)
      2. 11.9.2 DMA_REGS Registers
      3. 11.9.3 DMA_CH_REGS Registers
      4. 11.9.4 DMA Registers to Driverlib Functions
  14. 12External Memory Interface (EMIF)
    1. 12.1 Introduction
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 EMIF Related Collateral
      3. 12.1.3 Features
        1. 12.1.3.1 Asynchronous Memory Support
        2. 12.1.3.2 Synchronous DRAM Memory Support
      4. 12.1.4 Functional Block Diagram
      5. 12.1.5 Configuring Device Pins
    2. 12.2 EMIF Module Architecture
      1. 12.2.1  EMIF Clock Control
      2. 12.2.2  EMIF Requests
      3. 12.2.3  EMIF Signal Descriptions
      4. 12.2.4  EMIF Signal Multiplexing Control
      5. 12.2.5  SDRAM Controller and Interface
        1. 12.2.5.1  SDRAM Commands
        2. 12.2.5.2  Interfacing to SDRAM
        3. 12.2.5.3  SDRAM Configuration Registers
        4. 12.2.5.4  SDRAM Auto-Initialization Sequence
        5. 12.2.5.5  SDRAM Configuration Procedure
        6. 12.2.5.6  EMIF Refresh Controller
          1. 12.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 12.2.5.7  Self-Refresh Mode
        8. 12.2.5.8  Power-Down Mode
        9. 12.2.5.9  SDRAM Read Operation
        10. 12.2.5.10 SDRAM Write Operations
        11. 12.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 12.2.6  Asynchronous Controller and Interface
        1. 12.2.6.1 Interfacing to Asynchronous Memory
        2. 12.2.6.2 Accessing Larger Asynchronous Memories
        3. 12.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 12.2.6.4 Read and Write Operations in Normal Mode
          1. 12.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 12.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 12.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 12.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 12.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 12.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 12.2.7  Data Bus Parking
      8. 12.2.8  Reset and Initialization Considerations
      9. 12.2.9  Interrupt Support
        1. 12.2.9.1 Interrupt Events
      10. 12.2.10 DMA Event Support
      11. 12.2.11 EMIF Signal Multiplexing
      12. 12.2.12 Memory Map
      13. 12.2.13 Priority and Arbitration
      14. 12.2.14 System Considerations
        1. 12.2.14.1 Asynchronous Request Times
      15. 12.2.15 Power Management
        1. 12.2.15.1 Power Management Using Self-Refresh Mode
        2. 12.2.15.2 Power Management Using Power Down Mode
      16. 12.2.16 Emulation Considerations
    3. 12.3 Example Configuration
      1. 12.3.1 Hardware Interface
      2. 12.3.2 Software Configuration
        1. 12.3.2.1 Configuring the SDRAM Interface
          1. 12.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 12.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 12.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 12.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 12.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 12.3.2.2 Configuring the Flash Interface
          1. 12.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 12.4 Software
      1. 12.4.1 EMIF Examples
        1. 12.4.1.1  Pin setup for EMIF module accessing ASRAM.
        2. 12.4.1.2  EMIF1 ASYNC module accessing 16bit ASRAM.
        3. 12.4.1.3  EMIF1 ASYNC module accessing 16bit ASRAM through CPU1 and CPU2. - C28X_DUAL
        4. 12.4.1.4  EMIF1 ASYNC module accessing 16bit ASRAM trhough CPU1 and CPU2. - C28X_DUAL
        5. 12.4.1.5  EMIF1 module accessing 16bit ASRAM as code memory.
        6. 12.4.1.6  EMIF1 module accessing 16bit SDRAM using memcpy_fast_far().
        7. 12.4.1.7  EMIF1 module accessing 16bit SDRAM then puts into Self Refresh mode before entering Low Power Mode.
        8. 12.4.1.8  EMIF1 module accessing 32bit SDRAM using DMA.
        9. 12.4.1.9  EMIF1 module accessing 16bit SDRAM using alternate address mapping.
        10. 12.4.1.10 EMIF1 ASYNC module accessing 16bit ASRAM HIC FSI
        11. 12.4.1.11 EMIF1 ASYNC module accessing 8bit HIC controller.
    5. 12.5 EMIF Registers
      1. 12.5.1 EMIF Base Address Table (C28)
      2. 12.5.2 EMIF_REGS Registers
      3. 12.5.3 EMIF1_CONFIG_REGS Registers
      4. 12.5.4 EMIF2_CONFIG_REGS Registers
      5. 12.5.5 EMIF Registers to Driverlib Functions
  15. 13Flash Module
    1. 13.1  Introduction to Flash and OTP Memory
      1. 13.1.1 FLASH Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Flash Tools
      4. 13.1.4 Default Flash Configuration
    2. 13.2  Flash Bank, OTP, and Pump
    3. 13.3  Flash Module Controller (FMC)
    4. 13.4  Flash and OTP Memory Power-Down Modes and Wakeup
    5. 13.5  Active Grace Period
    6. 13.6  Flash and OTP Memory Performance
    7. 13.7  Flash Read Interface
      1. 13.7.1 C28x-FMC (CPU1-FMC and CPU2-FMC) Flash Read Interface
        1. 13.7.1.1 Standard Read Mode
        2. 13.7.1.2 Prefetch Mode
          1. 13.7.1.2.1 Data Cache
      2. 13.7.2 M4-FMC (CM-FMC) Flash Read Interface
        1. 13.7.2.1 Standard Read Mode
        2. 13.7.2.2 Cache Mode
          1. 13.7.2.2.1 Program Cache
          2. 13.7.2.2.2 Data Cache
    8. 13.8  Flash Erase and Program
      1. 13.8.1 Erase
      2. 13.8.2 Program
      3. 13.8.3 Verify
    9. 13.9  Error Correction Code (ECC) Protection
      1. 13.9.1 Single-Bit Data Error
      2. 13.9.2 Uncorrectable Error
      3. 13.9.3 SECDED Logic Correctness Check
    10. 13.10 Reserved Locations Within Flash and OTP Memory
    11. 13.11 Migrating an Application from RAM to Flash
    12. 13.12 Procedure to Change the Flash Control Registers
    13. 13.13 Flash Pump Ownership Semaphore
    14. 13.14 Software
      1. 13.14.1 FLASH Examples
        1. 13.14.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - CM
        2. 13.14.1.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        3. 13.14.1.3 Flash ECC Test Mode
        4. 13.14.1.4 Flash ECC Test Mode - CM
    15. 13.15 Flash Registers
      1. 13.15.1 FLASH Base Address Table (C28)
      2. 13.15.2 CM FLASH Base Address Table (CM)
      3. 13.15.3 FLASH_CTRL_REGS Registers
      4. 13.15.4 FLASH_ECC_REGS Registers
      5. 13.15.5 CM_FLASH_CTRL_REGS Registers
      6. 13.15.6 CM_FLASH_ECC_REGS Registers
      7. 13.15.7 FLASH_PUMP_SEMAPHORE_REGS Registers
      8. 13.15.8 FLASH Registers to Driverlib Functions
  16. 14Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 14.1 Introduction
      1. 14.1.1 ERAD Related Collateral
    2. 14.2 Enhanced Bus Comparator Unit
      1. 14.2.1 Enhanced Bus Comparator Unit Operations
      2. 14.2.2 Event Masking and Exporting
    3. 14.3 System Event Counter Unit
      1. 14.3.1 System Event Counter Modes
        1. 14.3.1.1 Counting Active Levels Versus Edges
        2. 14.3.1.2 Max Mode
        3. 14.3.1.3 Cumulative Mode
        4. 14.3.1.4 Input Signal Selection
      2. 14.3.2 Reset on Event
      3. 14.3.3 Operation Conditions
    4. 14.4 ERAD Ownership, Initialization and Reset
    5. 14.5 ERAD Programming Sequence
      1. 14.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 14.5.2 Timer and Counter Programming Sequence
    6. 14.6 Cyclic Redundancy Check Unit
      1. 14.6.1 CRC Unit Qualifier
      2. 14.6.2 CRC Unit Programming Sequence
    7. 14.7 Program Counter Trace
      1. 14.7.1 Functional Block Diagram
      2. 14.7.2 Trace Qualification Modes
      3. 14.7.3 Trace Memory
      4. 14.7.4 Trace Input Signal Conditioning
      5. 14.7.5 PC Trace Software Operation
      6. 14.7.6 Trace Operation in Debug Mode
    8. 14.8 Software
      1. 14.8.1 ERAD Examples
        1. 14.8.1.1  ERAD Profiling Interrupts
        2. 14.8.1.2  ERAD Profile Function
        3. 14.8.1.3  ERAD Profile Function
        4. 14.8.1.4  ERAD HWBP Monitor Program Counter
        5. 14.8.1.5  ERAD HWBP Monitor Program Counter
        6. 14.8.1.6  ERAD Profile Function
        7. 14.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 14.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 14.8.1.9  ERAD Stack Overflow
        10. 14.8.1.10 ERAD Profile Interrupts CLA
        11. 14.8.1.11 ERAD Profiling Interrupts
        12. 14.8.1.12 ERAD Profiling Interrupts
        13. 14.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 14.8.1.14 ERAD INTERRUPT ORDER
        15. 14.8.1.15 ERAD AND CLB
        16. 14.8.1.16 ERAD PWM PROTECTION
    9. 14.9 ERAD Registers
      1. 14.9.1 ERAD Base Address Table (C28)
      2. 14.9.2 ERAD_GLOBAL_REGS Registers
      3. 14.9.3 ERAD_HWBP_REGS Registers
      4. 14.9.4 ERAD_COUNTER_REGS Registers
      5. 14.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 14.9.6 ERAD_CRC_REGS Registers
      7. 14.9.7 ERAD Registers to Driverlib Functions
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital General-Purpose I/O Control
    4. 15.4  Input Qualification
      1. 15.4.1 No Synchronization (Asynchronous Input)
      2. 15.4.2 Synchronization to SYSCLKOUT Only
      3. 15.4.3 Qualification Using a Sampling Window
    5. 15.5  USB Signals
    6. 15.6  SPI Signals
    7. 15.7  GPIO and Peripheral Muxing
      1. 15.7.1 GPIO Muxing
      2. 15.7.2 Peripheral Muxing
    8. 15.8  Internal Pullup Configuration Requirements
    9. 15.9  Software
      1. 15.9.1 GPIO Examples
        1. 15.9.1.1 Device GPIO Setup
        2. 15.9.1.2 Device GPIO Toggle
        3. 15.9.1.3 Device GPIO Interrupt
      2. 15.9.2 LED Examples
        1. 15.9.2.1 LED Blinky Example (CM) - C28X_CM
        2. 15.9.2.2 LED Blinky Example - C28X_DUAL
        3. 15.9.2.3 LED Blinky Example - C28X_CM
        4. 15.9.2.4 LED Blinky Example with DCSM
        5. 15.9.2.5 LED Blinky Example - C28X_DUAL
    10. 15.10 GPIO Registers
      1. 15.10.1 GPIO Base Address Table (C28)
      2. 15.10.2 CM GPIO Base Address Table (CM)
      3. 15.10.3 GPIO_CTRL_REGS Registers
      4. 15.10.4 GPIO_DATA_REGS Registers
      5. 15.10.5 GPIO_DATA_READ_REGS Registers
      6. 15.10.6 CM_GPIO_DATA_REGS Registers
      7. 15.10.7 CM_GPIO_DATA_READ_REGS Registers
      8. 15.10.8 GPIO Registers to Driverlib Functions
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 Message RAMs
    3. 16.3 IPC Flags and Interrupts
    4. 16.4 IPC Command Registers
    5. 16.5 Free-Running Counter
    6. 16.6 IPC Communication Protocol
    7. 16.7 Software
      1. 16.7.1 IPC Examples
        1. 16.7.1.1  IPC basic message passing example with interrupt - C28X_CM
        2. 16.7.1.2  IPC basic message passing example with interrupt - C28X_CM
        3. 16.7.1.3  IPC basic message passing example with interrupt - C28X_DUAL
        4. 16.7.1.4  IPC basic message passing example with interrupt - C28X_DUAL
        5. 16.7.1.5  IPC message passing example with interrupt and message queue - C28X_CM
        6. 16.7.1.6  IPC message passing example with interrupt and message queue - C28X_CM
        7. 16.7.1.7  IPC message passing example with interrupt and message queue - C28X_DUAL
        8. 16.7.1.8  IPC message passing example with interrupt and message queue - C28X_DUAL
        9. 16.7.1.9  IPC basic message passing example with interrupt - C28X_DUAL
        10. 16.7.1.10 IPC basic message passing example with interrupt - C28X_DUAL
        11. 16.7.1.11 IPC message passing example with interrupt and message queue - C28X_DUAL
        12. 16.7.1.12 IPC message passing example with interrupt and message queue - C28X_DUAL
    8. 16.8 IPC Registers
      1. 16.8.1 IPC Base Address Table (C28)
      2. 16.8.2 CM IPC Base Address Table (CM)
      3. 16.8.3 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      4. 16.8.4 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      5. 16.8.5 CPU1TOCM_IPC_REGS_CPU1VIEW Registers
      6. 16.8.6 CPU1TOCM_IPC_REGS_CMVIEW Registers
      7. 16.8.7 CPU2TOCM_IPC_REGS_CPU2VIEW Registers
      8. 16.8.8 CPU2TOCM_IPC_REGS_CMVIEW Registers
      9. 16.8.9 IPC Registers to Driverlib Functions
  19. 17Crossbar (X-BAR)
    1. 17.1 Input X-BAR and CLB Input X-BAR
      1. 17.1.1 CLB Input X-BAR
    2. 17.2 ePWM, CLB, and GPIO Output X-BAR
      1. 17.2.1 ePWM X-BAR
        1. 17.2.1.1 ePWM X-BAR Architecture
      2. 17.2.2 CLB X-BAR
        1. 17.2.2.1 CLB X-BAR Architecture
      3. 17.2.3 GPIO Output X-BAR
        1. 17.2.3.1 GPIO Output X-BAR Architecture
      4. 17.2.4 CLB Output X-BAR
        1. 17.2.4.1 CLB Output X-BAR Architecture
      5. 17.2.5 X-BAR Flags
    3. 17.3 XBAR Registers
      1. 17.3.1 XBAR Base Address Table (C28)
      2. 17.3.2 INPUT_XBAR_REGS Registers
      3. 17.3.3 XBAR_REGS Registers
      4. 17.3.4 EPWM_XBAR_REGS Registers
      5. 17.3.5 CLB_XBAR_REGS Registers
      6. 17.3.6 OUTPUT_XBAR_REGS Registers
      7. 17.3.7 Register to Driverlib Function Mapping
        1. 17.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 17.3.7.2 XBAR Registers to Driverlib Functions
        3. 17.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 17.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 17.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  20. 18â–º ANALOG PERIPHERALS
    1. 18.1 Technical Reference Manual Overview
  21. 19Analog Subsystem
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 Optimizing Power-Up Time
    3. 19.3 Analog Subsystem Registers
      1. 19.3.1 ASBSYS Base Address Table (C28)
      2. 19.3.2 ANALOG_SUBSYS_REGS Registers
  22. 20Analog-to-Digital Converter (ADC)
    1. 20.1  Introduction
      1. 20.1.1 ADC Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Block Diagram
    2. 20.2  ADC Configurability
      1. 20.2.1 Clock Configuration
      2. 20.2.2 Resolution
      3. 20.2.3 Voltage Reference
        1. 20.2.3.1 External Reference Mode
      4. 20.2.4 Signal Mode
      5. 20.2.5 Expected Conversion Results
      6. 20.2.6 Interpreting Conversion Results
    3. 20.3  SOC Principle of Operation
      1. 20.3.1 SOC Configuration
      2. 20.3.2 Trigger Operation
      3. 20.3.3 ADC Acquisition (Sample and Hold) Window
      4. 20.3.4 ADC Input Models
      5. 20.3.5 Channel Selection
    4. 20.4  SOC Configuration Examples
      1. 20.4.1 Single Conversion from ePWM Trigger
      2. 20.4.2 Oversampled Conversion from ePWM Trigger
      3. 20.4.3 Multiple Conversions from CPU Timer Trigger
      4. 20.4.4 Software Triggering of SOCs
    5. 20.5  ADC Conversion Priority
    6. 20.6  Burst Mode
      1. 20.6.1 Burst Mode Example
      2. 20.6.2 Burst Mode Priority Example
    7. 20.7  EOC and Interrupt Operation
      1. 20.7.1 Interrupt Overflow
      2. 20.7.2 Continue to Interrupt Mode
      3. 20.7.3 Early Interrupt Configuration Mode
    8. 20.8  Post-Processing Blocks
      1. 20.8.1 PPB Offset Correction
      2. 20.8.2 PPB Error Calculation
      3. 20.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 20.8.4 PPB Sample Delay Capture
    9. 20.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 20.9.1 Implementation
      2. 20.9.2 Detecting an Open Input Pin
      3. 20.9.3 Detecting a Shorted Input Pin
    10. 20.10 Power-Up Sequence
    11. 20.11 ADC Calibration
      1. 20.11.1 ADC Zero Offset Calibration
      2. 20.11.2 ADC Calibration Routines in OTP Memory
    12. 20.12 ADC Timings
      1. 20.12.1 ADC Timing Diagrams
    13. 20.13 Additional Information
      1. 20.13.1 Ensuring Synchronous Operation
        1. 20.13.1.1 Basic Synchronous Operation
        2. 20.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 20.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 20.13.1.4 Synchronous Operation with Different Resolutions
        5. 20.13.1.5 Non-overlapping Conversions
      2. 20.13.2 Choosing an Acquisition Window Duration
      3. 20.13.3 Achieving Simultaneous Sampling
      4. 20.13.4 Result Register Mapping
      5. 20.13.5 Internal Temperature Sensor
      6. 20.13.6 Designing an External Reference Circuit
    14. 20.14 Software
      1. 20.14.1 ADC Examples
        1. 20.14.1.1  ADC Software Triggering
        2. 20.14.1.2  ADC ePWM Triggering
        3. 20.14.1.3  ADC Temperature Sensor Conversion
        4. 20.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 20.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 20.14.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 20.14.1.7  ADC PPB Offset (adc_ppb_offset)
        8. 20.14.1.8  ADC PPB Limits (adc_ppb_limits)
        9. 20.14.1.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 20.14.1.10 ADC ePWM Triggering Multiple SOC
        11. 20.14.1.11 ADC Burst Mode
        12. 20.14.1.12 ADC Burst Mode Oversampling
        13. 20.14.1.13 ADC SOC Oversampling
        14. 20.14.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
        15. 20.14.1.15 ADC High Priority SOC (adc_high_priority_soc)
        16. 20.14.1.16 ADC Interleaved Averaging in Software
        17. 20.14.1.17 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 20.15 ADC Registers
      1. 20.15.1 ADC Base Address Table (C28)
      2. 20.15.2 ADC_REGS Registers
      3. 20.15.3 ADC_RESULT_REGS Registers
      4. 20.15.4 ADC Registers to Driverlib Functions
  23. 21Buffered Digital-to-Analog Converter (DAC)
    1. 21.1 Introduction
      1. 21.1.1 DAC Related Collateral
      2. 21.1.2 Features
      3. 21.1.3 Block Diagram
    2. 21.2 Using the DAC
      1. 21.2.1 Initialization Sequence
      2. 21.2.2 DAC Offset Adjustment
      3. 21.2.3 EPWMSYNCPER Signal
    3. 21.3 Lock Registers
    4. 21.4 Software
      1. 21.4.1 DAC Examples
        1. 21.4.1.1 Buffered DAC Enable
        2. 21.4.1.2 Buffered DAC Random
        3. 21.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 21.5 DAC Registers
      1. 21.5.1 DAC Base Address Table (C28)
      2. 21.5.2 DAC_REGS Registers
      3. 21.5.3 DAC Registers to Driverlib Functions
  24. 22Comparator Subsystem (CMPSS)
    1. 22.1 Introduction
      1. 22.1.1 CMPSS Related Collateral
      2. 22.1.2 Features
      3. 22.1.3 Block Diagram
    2. 22.2 Comparator
    3. 22.3 Reference DAC
    4. 22.4 Ramp Generator
      1. 22.4.1 Ramp Generator Overview
      2. 22.4.2 Ramp Generator Behavior
      3. 22.4.3 Ramp Generator Behavior at Corner Cases
    5. 22.5 Digital Filter
      1. 22.5.1 Filter Initialization Sequence
    6. 22.6 Using the CMPSS
      1. 22.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 22.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 22.6.3 Calibrating the CMPSS
      4. 22.6.4 Enabling and Disabling the CMPSS Clock
    7. 22.7 Software
      1. 22.7.1 CMPSS Examples
        1. 22.7.1.1 CMPSS Asynchronous Trip
        2. 22.7.1.2 CMPSS Digital Filter Configuration
    8. 22.8 CMPSS Registers
      1. 22.8.1 CMPSS Base Address Table (C28)
      2. 22.8.2 CMPSS_REGS Registers
      3. 22.8.3 CMPSS Registers to Driverlib Functions
  25. 23â–º CONTROL PERIPHERALS
    1. 23.1 Technical Reference Manual Overview
  26. 24Enhanced Capture (eCAP)
    1. 24.1 Introduction
      1. 24.1.1 Features
      2. 24.1.2 ECAP Related Collateral
    2. 24.2 Description
    3. 24.3 Configuring Device Pins for the eCAP
    4. 24.4 Capture and APWM Operating Mode
    5. 24.5 Capture Mode Description
      1. 24.5.1  Event Prescaler
      2. 24.5.2  Edge Polarity Select and Qualifier
      3. 24.5.3  Continuous/One-Shot Control
      4. 24.5.4  32-Bit Counter and Phase Control
      5. 24.5.5  CAP1-CAP4 Registers
      6. 24.5.6  eCAP Synchronization
        1. 24.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 24.5.7  Interrupt Control
      8. 24.5.8  DMA Interrupt
      9. 24.5.9  Shadow Load and Lockout Control
      10. 24.5.10 APWM Mode Operation
    6. 24.6 Application of the eCAP Module
      1. 24.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 24.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 24.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 24.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 24.7 Application of the APWM Mode
      1. 24.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 24.8 Software
      1. 24.8.1 ECAP Examples
        1. 24.8.1.1 eCAP APWM Example
        2. 24.8.1.2 eCAP Capture PWM Example
        3. 24.8.1.3 eCAP APWM Phase-shift Example
        4. 24.8.1.4 eCAP Software Sync Example
    9. 24.9 eCAP Registers
      1. 24.9.1 ECAP Base Address Table (C28)
      2. 24.9.2 ECAP_REGS Registers
      3. 24.9.3 ECAP Registers to Driverlib Functions
  27. 25High Resolution Capture (HRCAP)
    1. 25.1 Introduction
      1. 25.1.1 HRCAP Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Description
    2. 25.2 Operational Details
      1. 25.2.1 HRCAP Clocking
      2. 25.2.2 HRCAP Initialization Sequence
      3. 25.2.3 HRCAP Interrupts
      4. 25.2.4 HRCAP Calibration
        1. 25.2.4.1 Applying the Scale Factor
    3. 25.3 Known Exceptions
    4. 25.4 Software
      1. 25.4.1 HRCAP Examples
        1. 25.4.1.1 HRCAP Capture and Calibration Example
    5. 25.5 HRCAP Registers
      1. 25.5.1 HRCAP Base Address Table (C28)
      2. 25.5.2 HRCAP_REGS Registers
      3. 25.5.3 HRCAP Registers to Driverlib Functions
  28. 26Enhanced Pulse Width Modulator (ePWM)
    1. 26.1  Introduction
      1. 26.1.1 EPWM Related Collateral
      2. 26.1.2 Submodule Overview
    2. 26.2  Configuring Device Pins
    3. 26.3  ePWM Modules Overview
    4. 26.4  Time-Base (TB) Submodule
      1. 26.4.1 Purpose of the Time-Base Submodule
      2. 26.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 26.4.3 Calculating PWM Period and Frequency
        1. 26.4.3.1 Time-Base Period Shadow Register
        2. 26.4.3.2 Time-Base Clock Synchronization
        3. 26.4.3.3 Time-Base Counter Synchronization
        4. 26.4.3.4 ePWM SYNC Selection
      4. 26.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 26.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 26.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 26.4.7 Global Load
        1. 26.4.7.1 Global Load Pulse Pre-Scalar
        2. 26.4.7.2 One-Shot Load Mode
        3. 26.4.7.3 One-Shot Sync Mode
    5. 26.5  Counter-Compare (CC) Submodule
      1. 26.5.1 Purpose of the Counter-Compare Submodule
      2. 26.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 26.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 26.5.4 Count Mode Timing Waveforms
    6. 26.6  Action-Qualifier (AQ) Submodule
      1. 26.6.1 Purpose of the Action-Qualifier Submodule
      2. 26.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 26.6.3 Action-Qualifier Event Priority
      4. 26.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 26.6.5 Configuration Requirements for Common Waveforms
    7. 26.7  Dead-Band Generator (DB) Submodule
      1. 26.7.1 Purpose of the Dead-Band Submodule
      2. 26.7.2 Dead-band Submodule Additional Operating Modes
      3. 26.7.3 Operational Highlights for the Dead-Band Submodule
    8. 26.8  PWM Chopper (PC) Submodule
      1. 26.8.1 Purpose of the PWM Chopper Submodule
      2. 26.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 26.8.3 Waveforms
        1. 26.8.3.1 One-Shot Pulse
        2. 26.8.3.2 Duty Cycle Control
    9. 26.9  Trip-Zone (TZ) Submodule
      1. 26.9.1 Purpose of the Trip-Zone Submodule
      2. 26.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 26.9.2.1 Trip-Zone Configurations
      3. 26.9.3 Generating Trip Event Interrupts
    10. 26.10 Event-Trigger (ET) Submodule
      1. 26.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 26.11 Digital Compare (DC) Submodule
      1. 26.11.1 Purpose of the Digital Compare Submodule
      2. 26.11.2 Enhanced Trip Action Using CMPSS
      3. 26.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 26.11.4 Operation Highlights of the Digital Compare Submodule
        1. 26.11.4.1 Digital Compare Events
        2. 26.11.4.2 Event Filtering
        3. 26.11.4.3 Valley Switching
    12. 26.12 ePWM Crossbar (X-BAR)
    13. 26.13 Applications to Power Topologies
      1. 26.13.1  Overview of Multiple Modules
      2. 26.13.2  Key Configuration Capabilities
      3. 26.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 26.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 26.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 26.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 26.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 26.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 26.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 26.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 26.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 26.14 Register Lock Protection
    15. 26.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 26.15.1 Operational Description of HRPWM
        1. 26.15.1.1 Controlling the HRPWM Capabilities
        2. 26.15.1.2 HRPWM Source Clock
        3. 26.15.1.3 Configuring the HRPWM
        4. 26.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 26.15.1.5 Principle of Operation
          1. 26.15.1.5.1 Edge Positioning
          2. 26.15.1.5.2 Scaling Considerations
          3. 26.15.1.5.3 Duty Cycle Range Limitation
          4. 26.15.1.5.4 High-Resolution Period
            1. 26.15.1.5.4.1 High-Resolution Period Configuration
        6. 26.15.1.6 Deadband High-Resolution Operation
        7. 26.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 26.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 26.15.1.8.1 #Defines for HRPWM Header Files
          2. 26.15.1.8.2 Implementing a Simple Buck Converter
            1. 26.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 26.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 26.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 26.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 26.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 26.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 26.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 26.15.2.2 Software Usage
          1. 26.15.2.2.1 A Sample of How to Add "Include" Files
          2.        1176
          3. 26.15.2.2.2 Declaring an Element
          4.        1178
          5. 26.15.2.2.3 Initializing With a Scale Factor Value
          6.        1180
          7. 26.15.2.2.4 SFO Function Calls
    16. 26.16 Software
      1. 26.16.1 EPWM Examples
        1. 26.16.1.1  ePWM Trip Zone
        2. 26.16.1.2  ePWM Up Down Count Action Qualifier
        3. 26.16.1.3  ePWM Synchronization
        4. 26.16.1.4  ePWM Digital Compare
        5. 26.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 26.16.1.6  ePWM Valley Switching
        7. 26.16.1.7  ePWM Digital Compare Edge Filter
        8. 26.16.1.8  ePWM Deadband
        9. 26.16.1.9  ePWM DMA
        10. 26.16.1.10 ePWM Chopper
        11. 26.16.1.11 EPWM Configure Signal
        12. 26.16.1.12 Realization of Monoshot mode
        13. 26.16.1.13 EPWM Action Qualifier (epwm_up_aq)
      2. 26.16.2 HRPWM Examples
        1. 26.16.2.1 HRPWM Duty Control with SFO
        2. 26.16.2.2 HRPWM Slider
        3. 26.16.2.3 HRPWM Period Control
        4. 26.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 26.16.2.5 HRPWM Slider Test
        6. 26.16.2.6 HRPWM Duty Up Count
        7. 26.16.2.7 HRPWM Period Up-Down Count
    17. 26.17 ePWM Registers
      1. 26.17.1 EPWM Base Address Table (C28)
      2. 26.17.2 EPWM_REGS Registers
      3. 26.17.3 SYNC_SOC_REGS Registers
      4. 26.17.4 Register to Driverlib Function Mapping
        1. 26.17.4.1 EPWM Registers to Driverlib Functions
        2. 26.17.4.2 HRPWM Registers to Driverlib Functions
  29. 27Enhanced Quadrature Encoder Pulse (eQEP)
    1. 27.1  Introduction
      1. 27.1.1 EQEP Related Collateral
    2. 27.2  Configuring Device Pins
    3. 27.3  Description
      1. 27.3.1 EQEP Inputs
      2. 27.3.2 Functional Description
      3. 27.3.3 eQEP Memory Map
    4. 27.4  Quadrature Decoder Unit (QDU)
      1. 27.4.1 Position Counter Input Modes
        1. 27.4.1.1 Quadrature Count Mode
        2. 27.4.1.2 Direction-Count Mode
        3. 27.4.1.3 Up-Count Mode
        4. 27.4.1.4 Down-Count Mode
      2. 27.4.2 eQEP Input Polarity Selection
      3. 27.4.3 Position-Compare Sync Output
    5. 27.5  Position Counter and Control Unit (PCCU)
      1. 27.5.1 Position Counter Operating Modes
        1. 27.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 27.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 27.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 27.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 27.5.2 Position Counter Latch
        1. 27.5.2.1 Index Event Latch
        2. 27.5.2.2 Strobe Event Latch
      3. 27.5.3 Position Counter Initialization
      4. 27.5.4 eQEP Position-compare Unit
    6. 27.6  eQEP Edge Capture Unit
    7. 27.7  eQEP Watchdog
    8. 27.8  eQEP Unit Timer Base
    9. 27.9  QMA Module
      1. 27.9.1 Modes of Operation
        1. 27.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 27.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 27.9.2 Interrupt and Error Generation
    10. 27.10 eQEP Interrupt Structure
    11. 27.11 Software
      1. 27.11.1 EQEP Examples
        1. 27.11.1.1 Frequency Measurement Using eQEP
        2. 27.11.1.2 Position and Speed Measurement Using eQEP
        3. 27.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 27.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 27.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 27.12 eQEP Registers
      1. 27.12.1 EQEP Base Address Table (C28)
      2. 27.12.2 EQEP_REGS Registers
      3. 27.12.3 EQEP Registers to Driverlib Functions
  30. 28Sigma Delta Filter Module (SDFM)
    1. 28.1  Introduction
      1. 28.1.1 SDFM Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Block Diagram
    2. 28.2  Configuring Device Pins
    3. 28.3  Input Qualification
    4. 28.4  Input Control Unit
    5. 28.5  SDFM Clock Control
    6. 28.6  Sinc Filter
      1. 28.6.1 Data Rate and Latency of the Sinc Filter
    7. 28.7  Data (Primary) Filter Unit
      1. 28.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 28.7.2 Data FIFO
      3. 28.7.3 SDSYNC Event
    8. 28.8  Comparator (Secondary) Filter Unit
      1. 28.8.1 Higher Threshold (HLT) Comparators
      2. 28.8.2 Lower Threshold (LLT) Comparators
      3. 28.8.3 Digital Filter
    9. 28.9  Theoretical SDFM Filter Output
    10. 28.10 Interrupt Unit
      1. 28.10.1 SDFM (SDyERR) Interrupt Sources
      2. 28.10.2 Data Ready (DRINT) Interrupt Sources
    11. 28.11 Software
      1. 28.11.1 SDFM Examples
        1. 28.11.1.1 SDFM Filter Sync CPU
        2. 28.11.1.2 SDFM Filter Sync CLA
        3. 28.11.1.3 SDFM Filter Sync DMA
        4. 28.11.1.4 SDFM PWM Sync
        5. 28.11.1.5 SDFM Type 1 Filter FIFO
        6. 28.11.1.6 SDFM Filter Sync CLA
    12. 28.12 SDFM Registers
      1. 28.12.1 SDFM Base Address Table (C28)
      2. 28.12.2 SDFM_REGS Registers
      3. 28.12.3 SDFM Registers to Driverlib Functions
  31. 29â–º COMMUNICATION PERIPHERALS
    1. 29.1 Technical Reference Manual Overview
  32. 30Controller Area Network (CAN)
    1. 30.1  Introduction
      1. 30.1.1 DCAN Related Collateral
      2. 30.1.2 Features
      3. 30.1.3 Block Diagram
        1. 30.1.3.1 CAN Core
        2. 30.1.3.2 Message Handler
        3. 30.1.3.3 Message RAM
        4. 30.1.3.4 Registers and Message Object Access (IFx)
    2. 30.2  Functional Description
      1. 30.2.1 Configuring Device Pins
      2. 30.2.2 Address/Data Bus Bridge
    3. 30.3  Operating Modes
      1. 30.3.1 Initialization
      2. 30.3.2 CAN Message Transfer (Normal Operation)
        1. 30.3.2.1 Disabled Automatic Retransmission
        2. 30.3.2.2 Auto-Bus-On
      3. 30.3.3 Test Modes
        1. 30.3.3.1 Silent Mode
        2. 30.3.3.2 Loopback Mode
        3. 30.3.3.3 External Loopback Mode
        4. 30.3.3.4 Loopback Combined with Silent Mode
    4. 30.4  Multiple Clock Source
    5. 30.5  Interrupt Functionality
      1. 30.5.1 Message Object Interrupts
      2. 30.5.2 Status Change Interrupts
      3. 30.5.3 Error Interrupts
      4. 30.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 30.5.5 Interrupt Topologies
    6. 30.6  DMA Functionality
    7. 30.7  Parity Check Mechanism
      1. 30.7.1 Behavior on Parity Error
    8. 30.8  Debug Mode
    9. 30.9  Module Initialization
    10. 30.10 Configuration of Message Objects
      1. 30.10.1 Configuration of a Transmit Object for Data Frames
      2. 30.10.2 Configuration of a Transmit Object for Remote Frames
      3. 30.10.3 Configuration of a Single Receive Object for Data Frames
      4. 30.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 30.10.5 Configuration of a FIFO Buffer
    11. 30.11 Message Handling
      1. 30.11.1  Message Handler Overview
      2. 30.11.2  Receive/Transmit Priority
      3. 30.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 30.11.4  Updating a Transmit Object
      5. 30.11.5  Changing a Transmit Object
      6. 30.11.6  Acceptance Filtering of Received Messages
      7. 30.11.7  Reception of Data Frames
      8. 30.11.8  Reception of Remote Frames
      9. 30.11.9  Reading Received Messages
      10. 30.11.10 Requesting New Data for a Receive Object
      11. 30.11.11 Storing Received Messages in FIFO Buffers
      12. 30.11.12 Reading from a FIFO Buffer
    12. 30.12 CAN Bit Timing
      1. 30.12.1 Bit Time and Bit Rate
        1. 30.12.1.1 Synchronization Segment
        2. 30.12.1.2 Propagation Time Segment
        3. 30.12.1.3 Phase Buffer Segments and Synchronization
        4. 30.12.1.4 Oscillator Tolerance Range
      2. 30.12.2 Configuration of the CAN Bit Timing
        1. 30.12.2.1 Calculation of the Bit Timing Parameters
        2. 30.12.2.2 Example for Bit Timing at High Baudrate
        3. 30.12.2.3 Example for Bit Timing at Low Baudrate
    13. 30.13 Message Interface Register Sets
      1. 30.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 30.13.2 Message Interface Register Set 3 (IF3)
    14. 30.14 Message RAM
      1. 30.14.1 Structure of Message Objects
      2. 30.14.2 Addressing Message Objects in RAM
      3. 30.14.3 Message RAM Representation in Debug Mode
    15. 30.15 Software
      1. 30.15.1 CAN Examples
        1. 30.15.1.1  NMI handling - C28X_DUAL
        2. 30.15.1.2  CAN External Loopback
        3. 30.15.1.3  Watchdog Reset - C28X_DUAL
        4. 30.15.1.4  CAN Loopback - CM
        5. 30.15.1.5  CAN External Loopback with Interrupts
        6. 30.15.1.6  CAN External Loopback with Interrupts - C28X_DUAL
        7. 30.15.1.7  CAN External Loopback with Interrupts - CM
        8. 30.15.1.8  CAN-A to CAN-B External Transmit
        9. 30.15.1.9  CAN-A to CAN-B External Transmit - CM
        10. 30.15.1.10 CAN External Loopback with DMA
        11. 30.15.1.11 CAN Transmit and Receive Configurations - CM
        12. 30.15.1.12 CAN Transmit and Receive Configurations
        13. 30.15.1.13 CAN Error Generation Example
        14. 30.15.1.14 CAN Remote Request Loopback
        15. 30.15.1.15 CAN example that illustrates the usage of Mask registers
    16. 30.16 CAN Registers
      1. 30.16.1 CAN Base Address Table (C28)
      2. 30.16.2 CM CAN Base Address Table (CM)
      3. 30.16.3 CAN_REGS Registers
      4. 30.16.4 CAN Registers to Driverlib Functions
  33. 31EtherCAT® Slave Controller (ESC)
    1. 31.1 Introduction
      1. 31.1.1  ECAT Related Collateral
      2. 31.1.2  ESC Features
      3. 31.1.3  ESC Subsystem Integrated Features
      4. 31.1.4  F2838x ESC versus Beckhoff ET1100
      5. 31.1.5  EtherCAT IP Block Diagram
      6. 31.1.6  ESC Functional Blocks
        1. 31.1.6.1  Interface to EtherCAT Master
        2. 31.1.6.2  Process Data Interface
        3. 31.1.6.3  General-Purpose Inputs and Outputs
        4. 31.1.6.4  EtherCAT Processing Unit (EPU)
        5. 31.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 31.1.6.6  Sync Manager
        7. 31.1.6.7  Monitoring
        8. 31.1.6.8  Reset Controller
        9. 31.1.6.9  PHY Management
        10. 31.1.6.10 Distributed Clock (DC)
        11. 31.1.6.11 EEPROM
        12. 31.1.6.12 Status / LEDs
      7. 31.1.7  EtherCAT Physical Layer
        1. 31.1.7.1 MII Interface
        2. 31.1.7.2 PHY Management Interface
          1. 31.1.7.2.1 PHY Address Configuration
          2. 31.1.7.2.2 PHY Reset Signal
          3. 31.1.7.2.3 PHY Clock
      8. 31.1.8  EtherCAT Protocol
      9. 31.1.9  EtherCAT State Machine (ESM)
      10. 31.1.10 More Information on EtherCAT
      11. 31.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 31.2 ESC and ESCSS Description
      1. 31.2.1  ESC RAM Parity and Memory Address Maps
        1. 31.2.1.1 ESC RAM Parity Logic
        2. 31.2.1.2 CPU1 ESC Memory Address Map
        3. 31.2.1.3 CM ESC Memory Address Map
      2. 31.2.2  Local Host Communication
        1. 31.2.2.1 Byte Accessibility Through PDI
        2. 31.2.2.2 Software Details for Operation Across Clock Domains
      3. 31.2.3  Debug Emulation Mode Operation
      4. 31.2.4  ESC SubSystem
        1. 31.2.4.1 CPU1 Bus Interface
        2. 31.2.4.2 CM Bus Interface
      5. 31.2.5  Interrupts and Interrupt Mapping
      6. 31.2.6  Power, Clocks, and Resets
        1. 31.2.6.1 Power
        2. 31.2.6.2 Clocking
        3. 31.2.6.3 Resets
          1. 31.2.6.3.1 Chip-Level Reset
          2. 31.2.6.3.2 EtherCAT Soft Resets
          3. 31.2.6.3.3 Reset Out (RESET_OUT)
      7. 31.2.7  LED Controls
      8. 31.2.8  Slave Node Configuration and EEPROM
      9. 31.2.9  General-Purpose Inputs and Outputs
        1. 31.2.9.1 General-Purpose Inputs
        2. 31.2.9.2 General-Purpose Output
      10. 31.2.10 Distributed Clocks – Sync and Latch
        1. 31.2.10.1 Clock Synchronization
        2. 31.2.10.2 SYNC Signals
          1. 31.2.10.2.1 Seeking Host Intervention
        3. 31.2.10.3 LATCH Signals
          1. 31.2.10.3.1 Timestamping
        4. 31.2.10.4 Device Control and Synchronization
          1. 31.2.10.4.1 Synchronization of PWM
          2. 31.2.10.4.2 ECAP SYNC Inputs
          3. 31.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 31.3 Software Initialization Sequence and Allocating Ownership
    4. 31.4 ESC Configuration Constants
    5. 31.5 EtherCAT IP Registers
      1. 31.5.1 ECAT Base Address Table (C28)
      2. 31.5.2 ESCSS_REGS Registers
      3. 31.5.3 ESCSS_CONFIG_REGS Registers
      4. 31.5.4 ESC_SS Registers to Driverlib Functions
  34. 32Fast Serial Interface (FSI)
    1. 32.1 Introduction
      1. 32.1.1 FSI Related Collateral
      2. 32.1.2 FSI Features
    2. 32.2 System-level Integration
      1. 32.2.1 CPU Interface
      2. 32.2.2 Signal Description
        1. 32.2.2.1 Configuring Device Pins
      3. 32.2.3 FSI Interrupts
        1. 32.2.3.1 Transmitter Interrupts
        2. 32.2.3.2 Receiver Interrupts
        3. 32.2.3.3 Configuring Interrupts
        4. 32.2.3.4 Handling Interrupts
      4. 32.2.4 CLA Task Triggering
      5. 32.2.5 DMA Interface
      6. 32.2.6 External Frame Trigger Mux
    3. 32.3 FSI Functional Description
      1. 32.3.1  Introduction to Operation
      2. 32.3.2  FSI Transmitter Module
        1. 32.3.2.1 Initialization
        2. 32.3.2.2 FSI_TX Clocking
        3. 32.3.2.3 Transmitting Frames
          1. 32.3.2.3.1 Software Triggered Frames
          2. 32.3.2.3.2 Externally Triggered Frames
          3. 32.3.2.3.3 Ping Frame Generation
            1. 32.3.2.3.3.1 Automatic Ping Frames
            2. 32.3.2.3.3.2 Software Triggered Ping Frame
            3. 32.3.2.3.3.3 Externally Triggered Ping Frame
          4. 32.3.2.3.4 Transmitting Frames with DMA
        4. 32.3.2.4 Transmit Buffer Management
        5. 32.3.2.5 CRC Submodule
        6. 32.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 32.3.2.7 Reset
      3. 32.3.3  FSI Receiver Module
        1. 32.3.3.1  Initialization
        2. 32.3.3.2  FSI_RX Clocking
        3. 32.3.3.3  Receiving Frames
          1. 32.3.3.3.1 Receiving Frames with DMA
        4. 32.3.3.4  Ping Frame Watchdog
        5. 32.3.3.5  Frame Watchdog
        6. 32.3.3.6  Delay Line Control
        7. 32.3.3.7  Buffer Management
        8. 32.3.3.8  CRC Submodule
        9. 32.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 32.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 32.3.3.11 FSI_RX Reset
      4. 32.3.4  Frame Format
        1. 32.3.4.1 FSI Frame Phases
        2. 32.3.4.2 Frame Types
          1. 32.3.4.2.1 Ping Frames
          2. 32.3.4.2.2 Error Frames
          3. 32.3.4.2.3 Data Frames
        3. 32.3.4.3 Multi-Lane Transmission
      5. 32.3.5  Flush Sequence
      6. 32.3.6  Internal Loopback
      7. 32.3.7  CRC Generation
      8. 32.3.8  ECC Module
      9. 32.3.9  Tag Matching
      10. 32.3.10 TDM Configurations
      11. 32.3.11 FSI-SPI Compatibility Mode
        1. 32.3.11.1 Available SPI Modes
          1. 32.3.11.1.1 FSITX as SPI Master, Transmit Only
            1. 32.3.11.1.1.1 Initialization
            2. 32.3.11.1.1.2 Operation
          2. 32.3.11.1.2 FSIRX as SPI Slave, Receive Only
            1. 32.3.11.1.2.1 Initialization
            2. 32.3.11.1.2.2 Operation
          3. 32.3.11.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Master
            1. 32.3.11.1.3.1 Initialization
            2. 32.3.11.1.3.2 Operation
    4. 32.4 FSI Programing Guide
      1. 32.4.1 Establishing the Communication Link
        1. 32.4.1.1 Establishing the Communication Link from the Master Device
        2. 32.4.1.2 Establishing the Communication Link from the Slave Device
      2. 32.4.2 Register Protection
      3. 32.4.3 Emulation Mode
    5. 32.5 Software
      1. 32.5.1 FSI Examples
        1. 32.5.1.1  FSI Multi-Rx Tag-Match - C28X_DUAL
        2. 32.5.1.2  FSI Loopback:CPU Control
        3. 32.5.1.3  FSI Multi-Rx Tag-Match - C28X_DUAL
        4. 32.5.1.4  FSI Loopback CLA control
        5. 32.5.1.5  FSI DMA frame transfers:DMA Control
        6. 32.5.1.6  FSI data transfer by external trigger
        7. 32.5.1.7  FSI data transfers upon CPU Timer event
        8. 32.5.1.8  FSI and SPI communication(fsi_ex6_spi_main_tx)
        9. 32.5.1.9  FSI and SPI communication(fsi_ex7_spi_remote_rx)
        10. 32.5.1.10 FSI P2Point Connection:Rx Side
        11. 32.5.1.11 FSI P2Point Connection:Tx Side
        12. 32.5.1.12 FSI star connection topology example. FSI communication using CPU control
        13. 32.5.1.13 FSI daisy chain topology, lead device example
        14. 32.5.1.14 FSI daisy chain topology, node device example
    6. 32.6 FSI Registers
      1. 32.6.1 FSI Base Address Table (C28)
      2. 32.6.2 FSI_TX_REGS Registers
      3. 32.6.3 FSI_RX_REGS Registers
      4. 32.6.4 FSI Registers to Driverlib Functions
  35. 33Inter-Integrated Circuit Module (I2C)
    1. 33.1 Introduction
      1. 33.1.1 I2C Related Collateral
      2. 33.1.2 Features
      3. 33.1.3 Features Not Supported
      4. 33.1.4 Functional Overview
      5. 33.1.5 Clock Generation
      6. 33.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 33.1.6.1 Formula for the Master Clock Period
    2. 33.2 Configuring Device Pins
    3. 33.3 I2C Module Operational Details
      1. 33.3.1  Input and Output Voltage Levels
      2. 33.3.2  Selecting Pullup Resistors
      3. 33.3.3  Data Validity
      4. 33.3.4  Operating Modes
      5. 33.3.5  I2C Module START and STOP Conditions
      6. 33.3.6  Non-repeat Mode versus Repeat Mode
      7. 33.3.7  Serial Data Formats
        1. 33.3.7.1 7-Bit Addressing Format
        2. 33.3.7.2 10-Bit Addressing Format
        3. 33.3.7.3 Free Data Format
        4. 33.3.7.4 Using a Repeated START Condition
      8. 33.3.8  Clock Synchronization
      9. 33.3.9  Arbitration
      10. 33.3.10 Digital Loopback Mode
      11. 33.3.11 NACK Bit Generation
    4. 33.4 Interrupt Requests Generated by the I2C Module
      1. 33.4.1 Basic I2C Interrupt Requests
      2. 33.4.2 I2C FIFO Interrupts
    5. 33.5 Resetting or Disabling the I2C Module
    6. 33.6 Software
      1. 33.6.1 I2C Examples
        1. 33.6.1.1  C28x-I2C Library source file for FIFO interrupts
        2. 33.6.1.2  C28x-I2C Library source file for FIFO using polling
        3. 33.6.1.3  C28x-I2C Library source file for FIFO interrupts
        4. 33.6.1.4  I2C Loopback with Slave Receive Interrupt - CM
        5. 33.6.1.5  I2C Digital Loopback with FIFO Interrupts
        6. 33.6.1.6  I2C EEPROM
        7. 33.6.1.7  I2C Digital External Loopback with FIFO Interrupts
        8. 33.6.1.8  I2C EEPROM
        9. 33.6.1.9  I2C controller target communication using FIFO interrupts
        10. 33.6.1.10 I2C EEPROM
    7. 33.7 I2C Registers
      1. 33.7.1 I2C Base Address Table (C28)
      2. 33.7.2 I2C_REGS Registers
      3. 33.7.3 I2C Registers to Driverlib Functions
  36. 34Multichannel Buffered Serial Port (McBSP)
    1. 34.1  Introduction
      1. 34.1.1 MCBSP Related Collateral
      2. 34.1.2 Features of the McBSPs
      3. 34.1.3 McBSP Pins/Signals
        1. 34.1.3.1 McBSP Generic Block Diagram
    2. 34.2  Configuring Device Pins
    3. 34.3  McBSP Operation
      1. 34.3.1 Data Transfer Process of McBSPs
        1. 34.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
        2. 34.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
      2. 34.3.2 Companding (Compressing and Expanding) Data
        1. 34.3.2.1 Companding Formats
        2. 34.3.2.2 Capability to Compand Internal Data
        3. 34.3.2.3 Reversing Bit Order: Option to Transfer LSB First
      3. 34.3.3 Clocking and Framing Data
        1. 34.3.3.1 Clocking
        2. 34.3.3.2 Serial Words
        3. 34.3.3.3 Frames and Frame Synchronization
        4. 34.3.3.4 Generating Transmit and Receive Interrupts
          1. 34.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
        5. 34.3.3.5 Ignoring Frame-Synchronization Pulses
        6. 34.3.3.6 Frame Frequency
        7. 34.3.3.7 Maximum Frame Frequency
      4. 34.3.4 Frame Phases
        1. 34.3.4.1 Number of Phases, Words, and Bits Per Frame
        2. 34.3.4.2 Single-Phase Frame Example
        3. 34.3.4.3 Dual-Phase Frame Example
        4. 34.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
      5. 34.3.5 McBSP Reception
      6. 34.3.6 McBSP Transmission
      7. 34.3.7 Interrupts and DMA Events Generated by a McBSP
    4. 34.4  McBSP Sample Rate Generator
      1. 34.4.1 Block Diagram
        1. 34.4.1.1 Clock Generation in the Sample Rate Generator
        2. 34.4.1.2 Choosing an Input Clock
        3. 34.4.1.3 Choosing a Polarity for the Input Clock
        4. 34.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
          1. 34.4.1.4.1 CLKG Frequency
        5. 34.4.1.5 Keeping CLKG Synchronized to External MCLKR
      2. 34.4.2 Frame Synchronization Generation in the Sample Rate Generator
        1. 34.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
        2. 34.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
        3. 34.4.2.3 Keeping FSG Synchronized to an External Clock
      3. 34.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
        1. 34.4.3.1 Operating the Transmitter Synchronously with the Receiver
        2. 34.4.3.2 Synchronization Examples
      4. 34.4.4 Reset and Initialization Procedure for the Sample Rate Generator
    5. 34.5  McBSP Exception/Error Conditions
      1. 34.5.1 Types of Errors
      2. 34.5.2 Overrun in the Receiver
        1. 34.5.2.1 Example of Overrun Condition
        2. 34.5.2.2 Example of Preventing Overrun Condition
      3. 34.5.3 Unexpected Receive Frame-Synchronization Pulse
        1. 34.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
        2. 34.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
        3. 34.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
      4. 34.5.4 Overwrite in the Transmitter
        1. 34.5.4.1 Example of Overwrite Condition
        2. 34.5.4.2 Preventing Overwrites
      5. 34.5.5 Underflow in the Transmitter
        1. 34.5.5.1 Example of the Underflow Condition
        2. 34.5.5.2 Example of Preventing Underflow Condition
      6. 34.5.6 Unexpected Transmit Frame-Synchronization Pulse
        1. 34.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
        2. 34.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
        3. 34.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
    6. 34.6  Multichannel Selection Modes
      1. 34.6.1 Channels, Blocks, and Partitions
      2. 34.6.2 Multichannel Selection
      3. 34.6.3 Configuring a Frame for Multichannel Selection
      4. 34.6.4 Using Two Partitions
        1. 34.6.4.1 Assigning Blocks to Partitions A and B
        2. 34.6.4.2 Reassigning Blocks During Reception/Transmission
      5. 34.6.5 Using Eight Partitions
      6. 34.6.6 Receive Multichannel Selection Mode
      7. 34.6.7 Transmit Multichannel Selection Modes
        1. 34.6.7.1 Disabling/Enabling Versus Masking/Unmasking
        2. 34.6.7.2 Activity on McBSP Pins for Different Values of XMCM
      8. 34.6.8 Using Interrupts Between Block Transfers
    7. 34.7  SPI Operation Using the Clock Stop Mode
      1. 34.7.1 SPI Protocol
      2. 34.7.2 Clock Stop Mode
      3. 34.7.3 Enable and Configure the Clock Stop Mode
      4. 34.7.4 Clock Stop Mode Timing Diagrams
      5. 34.7.5 Procedure for Configuring a McBSP for SPI Operation
      6. 34.7.6 McBSP as the SPI Master
      7. 34.7.7 McBSP as an SPI Slave
    8. 34.8  Receiver Configuration
      1. 34.8.1  Programming the McBSP Registers for the Desired Receiver Operation
      2. 34.8.2  Resetting and Enabling the Receiver
        1. 34.8.2.1 Reset Considerations
      3. 34.8.3  Set the Receiver Pins to Operate as McBSP Pins
      4. 34.8.4  Digital Loopback Mode
      5. 34.8.5  Clock Stop Mode
      6. 34.8.6  Receive Multichannel Selection Mode
      7. 34.8.7  Receive Frame Phases
      8. 34.8.8  Receive Word Lengths
        1. 34.8.8.1 Word Length Bits
      9. 34.8.9  Receive Frame Length
        1. 34.8.9.1 Selected Frame Length
      10. 34.8.10 Receive Frame-Synchronization Ignore Function
        1. 34.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
        2. 34.8.10.2 Examples of Effects of RFIG
      11. 34.8.11 Receive Companding Mode
        1. 34.8.11.1 Companding
        2. 34.8.11.2 Format of Expanded Data
        3. 34.8.11.3 Companding Internal Data
        4. 34.8.11.4 Option to Receive LSB First
      12. 34.8.12 Receive Data Delay
        1. 34.8.12.1 Data Delay
        2. 34.8.12.2 0-Bit Data Delay
        3. 34.8.12.3 2-Bit Data Delay
      13. 34.8.13 Receive Sign-Extension and Justification Mode
        1. 34.8.13.1 Sign-Extension and the Justification
      14. 34.8.14 Receive Interrupt Mode
      15. 34.8.15 Receive Frame-Synchronization Mode
        1. 34.8.15.1 Receive Frame-Synchronization Modes
      16. 34.8.16 Receive Frame-Synchronization Polarity
        1. 34.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
        2. 34.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
      17. 34.8.17 Receive Clock Mode
        1. 34.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
      18. 34.8.18 Receive Clock Polarity
        1. 34.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      19. 34.8.19 SRG Clock Divide-Down Value
        1. 34.8.19.1 Sample Rate Generator Clock Divider
      20. 34.8.20 SRG Clock Synchronization Mode
      21. 34.8.21 SRG Clock Mode (Choose an Input Clock)
      22. 34.8.22 SRG Input Clock Polarity
        1. 34.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
    9. 34.9  Transmitter Configuration
      1. 34.9.1  Programming the McBSP Registers for the Desired Transmitter Operation
      2. 34.9.2  Resetting and Enabling the Transmitter
        1. 34.9.2.1 Reset Considerations
      3. 34.9.3  Set the Transmitter Pins to Operate as McBSP Pins
      4. 34.9.4  Digital Loopback Mode
      5. 34.9.5  Clock Stop Mode
      6. 34.9.6  Transmit Multichannel Selection Mode
      7. 34.9.7  XCERs Used in the Transmit Multichannel Selection Mode
      8. 34.9.8  Transmit Frame Phases
      9. 34.9.9  Transmit Word Lengths
        1. 34.9.9.1 Word Length Bits
      10. 34.9.10 Transmit Frame Length
        1. 34.9.10.1 Selected Frame Length
      11. 34.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function
        1. 34.9.11.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
        2. 34.9.11.2 Examples Showing the Effects of XFIG
      12. 34.9.12 Transmit Companding Mode
        1. 34.9.12.1 Companding
        2. 34.9.12.2 Format for Data To Be Compressed
        3. 34.9.12.3 Capability to Compand Internal Data
        4. 34.9.12.4 Option to Transmit LSB First
      13. 34.9.13 Transmit Data Delay
        1. 34.9.13.1 Data Delay
        2. 34.9.13.2 0-Bit Data Delay
        3. 34.9.13.3 2-Bit Data Delay
      14. 34.9.14 Transmit DXENA Mode
      15. 34.9.15 Transmit Interrupt Mode
      16. 34.9.16 Transmit Frame-Synchronization Mode
        1. 34.9.16.1 Other Considerations
      17. 34.9.17 Transmit Frame-Synchronization Polarity
        1. 34.9.17.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      18. 34.9.18 SRG Frame-Synchronization Period and Pulse Width
        1. 34.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
      19. 34.9.19 Transmit Clock Mode
        1. 34.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
        2. 34.9.19.2 Other Considerations
      20. 34.9.20 Transmit Clock Polarity
        1. 34.9.20.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
    10. 34.10 Emulation and Reset Considerations
      1. 34.10.1 McBSP Emulation Mode
      2. 34.10.2 Resetting and Initializing McBSPs
        1. 34.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
        2. 34.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
        3. 34.10.2.3 McBSP Initialization Procedure
        4. 34.10.2.4 Resetting the Transmitter While the Receiver is Running
          1. 34.10.2.4.1 Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
    11. 34.11 Data Packing Examples
      1. 34.11.1 Data Packing Using Frame Length and Word Length
      2. 34.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
    12. 34.12 Interrupt Generation
      1. 34.12.1 McBSP Receive Interrupt Generation
      2. 34.12.2 McBSP Transmit Interrupt Generation
      3. 34.12.3 Error Flags
    13. 34.13 McBSP Modes
    14. 34.14 Special Case: External Device is the Transmit Frame Master
    15. 34.15 Software
      1. 34.15.1 MCBSP Examples
        1. 34.15.1.1 Pin Setup for McBSP module
        2. 34.15.1.2 McBSP loopback example
        3. 34.15.1.3 McBSP loopback with DMA example.
        4. 34.15.1.4 McBSP loopback with interrupts example
        5. 34.15.1.5 McBSP loopback with interrupts example
        6. 34.15.1.6 McBSP loopback example using SPI mode
        7. 34.15.1.7 McBSP external loopback example
        8. 34.15.1.8 McBSP external loopback example using SPI mode
        9. 34.15.1.9 McBSP TDM-8 Test
    16. 34.16 McBSP Registers
      1. 34.16.1 MCBSP Base Address Table (C28)
      2. 34.16.2 McBSP_REGS Registers
      3. 34.16.3 MCBSP Registers to Driverlib Functions
  37. 35Power Management Bus Module (PMBus)
    1. 35.1 Introduction
      1. 35.1.1 PMBUS Related Collateral
      2. 35.1.2 Features
      3. 35.1.3 Block Diagram
    2. 35.2 Configuring Device Pins
    3. 35.3 Slave Mode Operation
      1. 35.3.1 Configuration
      2. 35.3.2 Message Handling
        1. 35.3.2.1  Quick Command
        2. 35.3.2.2  Send Byte
        3. 35.3.2.3  Receive Byte
        4. 35.3.2.4  Write Byte and Write Word
        5. 35.3.2.5  Read Byte and Read Word
        6. 35.3.2.6  Process Call
        7. 35.3.2.7  Block Write
        8. 35.3.2.8  Block Read
        9. 35.3.2.9  Block Write-Block Read Process Call
        10. 35.3.2.10 Alert Response
        11. 35.3.2.11 Extended Command
        12. 35.3.2.12 Group Command
    4. 35.4 Master Mode Operation
      1. 35.4.1 Configuration
      2. 35.4.2 Message Handling
        1. 35.4.2.1  Quick Command
        2. 35.4.2.2  Send Byte
        3. 35.4.2.3  Receive Byte
        4. 35.4.2.4  Write Byte and Write Word
        5. 35.4.2.5  Read Byte and Read Word
        6. 35.4.2.6  Process Call
        7. 35.4.2.7  Block Write
        8. 35.4.2.8  Block Read
        9. 35.4.2.9  Block Write-Block Read Process Call
        10. 35.4.2.10 Alert Response
        11. 35.4.2.11 Extended Command
        12. 35.4.2.12 Group Command
    5. 35.5 PMBus Registers
      1. 35.5.1 PMBUS Base Address Table (C28)
      2. 35.5.2 PMBUS_REGS Registers
      3. 35.5.3 PMBUS Registers to Driverlib Functions
  38. 36Serial Communications Interface (SCI)
    1. 36.1  Introduction
      1. 36.1.1 Features
      2. 36.1.2 SCI Related Collateral
      3. 36.1.3 Block Diagram
    2. 36.2  Architecture
    3. 36.3  SCI Module Signal Summary
    4. 36.4  Configuring Device Pins
    5. 36.5  Multiprocessor and Asynchronous Communication Modes
    6. 36.6  SCI Programmable Data Format
    7. 36.7  SCI Multiprocessor Communication
      1. 36.7.1 Recognizing the Address Byte
      2. 36.7.2 Controlling the SCI TX and RX Features
      3. 36.7.3 Receipt Sequence
    8. 36.8  Idle-Line Multiprocessor Mode
      1. 36.8.1 Idle-Line Mode Steps
      2. 36.8.2 Block Start Signal
      3. 36.8.3 Wake-Up Temporary (WUT) Flag
        1. 36.8.3.1 Sending a Block Start Signal
      4. 36.8.4 Receiver Operation
    9. 36.9  Address-Bit Multiprocessor Mode
      1. 36.9.1 Sending an Address
    10. 36.10 SCI Communication Format
      1. 36.10.1 Receiver Signals in Communication Modes
      2. 36.10.2 Transmitter Signals in Communication Modes
    11. 36.11 SCI Port Interrupts
      1. 36.11.1 Break Detect
    12. 36.12 SCI Baud Rate Calculations
    13. 36.13 SCI Enhanced Features
      1. 36.13.1 SCI FIFO Description
      2. 36.13.2 SCI Auto-Baud
      3. 36.13.3 Autobaud-Detect Sequence
    14. 36.14 Software
      1. 36.14.1 SCI Examples
        1. 36.14.1.1 Tune Baud Rate via UART Example
        2. 36.14.1.2 SCI FIFO Digital Loop Back
        3. 36.14.1.3 Watchdog Reset - C28X_DUAL
        4. 36.14.1.4 NMI handling - C28X_DUAL
        5. 36.14.1.5 SCI Digital Loop Back with Interrupts
        6. 36.14.1.6 SCI Echoback
        7. 36.14.1.7 stdout redirect example
    15. 36.15 SCI Registers
      1. 36.15.1 SCI Base Address Table (C28)
      2. 36.15.2 SCI_REGS Registers
      3. 36.15.3 SCI Registers to Driverlib Functions
  39. 37Serial Peripheral Interface (SPI)
    1. 37.1 Introduction
      1. 37.1.1 Features
      2. 37.1.2 SPI Related Collateral
      3. 37.1.3 Block Diagram
    2. 37.2 System-Level Integration
      1. 37.2.1 SPI Module Signals
      2. 37.2.2 Configuring Device Pins
        1. 37.2.2.1 GPIOs Required for High-Speed Mode
      3. 37.2.3 SPI Interrupts
      4. 37.2.4 DMA Support
    3. 37.3 SPI Operation
      1. 37.3.1  Introduction to Operation
      2. 37.3.2  Master Mode
      3. 37.3.3  Slave Mode
      4. 37.3.4  Data Format
        1. 37.3.4.1 Transmission of Bit from SPIRXBUF
      5. 37.3.5  Baud Rate Selection
        1. 37.3.5.1 Baud Rate Determination
        2. 37.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 37.3.6  SPI Clocking Schemes
      7. 37.3.7  SPI FIFO Description
      8. 37.3.8  SPI DMA Transfers
        1. 37.3.8.1 Transmitting Data Using SPI with DMA
        2. 37.3.8.2 Receiving Data Using SPI with DMA
      9. 37.3.9  SPI High-Speed Mode
      10. 37.3.10 SPI 3-Wire Mode Description
    4. 37.4 Programming Procedure
      1. 37.4.1 Initialization Upon Reset
      2. 37.4.2 Configuring the SPI
      3. 37.4.3 Configuring the SPI for High-Speed Mode
      4. 37.4.4 Data Transfer Example
      5. 37.4.5 SPI 3-Wire Mode Code Examples
        1. 37.4.5.1 3-Wire Master Mode Transmit
        2.       1924
          1. 37.4.5.2.1 3-Wire Master Mode Receive
        3.       1926
          1. 37.4.5.2.1 3-Wire Slave Mode Transmit
        4.       1928
          1. 37.4.5.2.1 3-Wire Slave Mode Receive
      6. 37.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 37.5 Software
      1. 37.5.1 SPI Examples
        1. 37.5.1.1 SPI Digital Loopback
        2. 37.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 37.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 37.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 37.5.1.5 SPI Digital Loopback with DMA
        6. 37.5.1.6 SPI EEPROM
        7. 37.5.1.7 SPI DMA EEPROM
    6. 37.6 SPI Registers
      1. 37.6.1 SPI Base Address Table (C28)
      2. 37.6.2 SPI_REGS Registers
      3. 37.6.3 SPI Registers to Driverlib Functions
  40. 38Universal Serial Bus (USB) Controller
    1. 38.1 Introduction
      1. 38.1.1 Features
      2. 38.1.2 USB Related Collateral
      3. 38.1.3 Block Diagram
        1. 38.1.3.1 Signal Description
        2. 38.1.3.2 VBus Recommendations
    2. 38.2 Functional Description
      1. 38.2.1 Operation as a Device
        1. 38.2.1.1 Control and Configurable Endpoints
          1. 38.2.1.1.1 IN Transactions as a Device
          2. 38.2.1.1.2 Out Transactions as a Device
          3. 38.2.1.1.3 Scheduling
          4. 38.2.1.1.4 Additional Actions
          5. 38.2.1.1.5 Device Mode Suspend
          6. 38.2.1.1.6 Start of Frame
          7. 38.2.1.1.7 USB Reset
          8. 38.2.1.1.8 Connect/Disconnect
      2. 38.2.2 Operation as a Host
        1. 38.2.2.1 Endpoint Registers
        2. 38.2.2.2 IN Transactions as a Host
        3. 38.2.2.3 OUT Transactions as a Host
        4. 38.2.2.4 Transaction Scheduling
        5. 38.2.2.5 USB Hubs
        6. 38.2.2.6 Babble
        7. 38.2.2.7 Host SUSPEND
        8. 38.2.2.8 USB RESET
        9. 38.2.2.9 Connect/Disconnect
      3. 38.2.3 DMA Operation
      4. 38.2.4 Address/Data Bus Bridge
    3. 38.3 Initialization and Configuration
      1. 38.3.1 Pin Configuration
      2. 38.3.2 Endpoint Configuration
    4. 38.4 USB Global Interrupts
    5. 38.5 Software
      1. 38.5.1 USB Examples
        1. 38.5.1.1  Wrapper for interrupt functions and USB support pins. - CM
        2. 38.5.1.2  USB CDC serial example
        3. 38.5.1.3  USB Composite Serial Device (usb_dev_cserial) - CM
        4. 38.5.1.4  USB HID Mouse Device
        5. 38.5.1.5  USB HID Mouse Device - CM
        6. 38.5.1.6  Data structures defining the USB mouse device. - CM
        7. 38.5.1.7  USB Device Keyboard
        8. 38.5.1.8  USB HID Keyboard Device (usb_dev_keyboard) - CM
        9. 38.5.1.9  Data structures defining the USB keyboard device. - CM
        10. 38.5.1.10 Data structures defining this bulk USB device. - CM
        11. 38.5.1.11 USB Generic Bulk Device (usb_dev_bulk) - CM
        12. 38.5.1.12 USB Generic Bulk Device
        13. 38.5.1.13 USB HID Mouse Host
        14. 38.5.1.14 USB HID Mouse Host (usb_host_mouse) - CM
        15. 38.5.1.15 USB HID Keyboard Host (usb_host_keyboard) - CM
        16. 38.5.1.16 USB HID Keyboard Host
        17. 38.5.1.17 USB Mass Storage Class Host
        18. 38.5.1.18 USB Mass Storage Class Host (usb_host_msc) - CM
        19. 38.5.1.19 USB Dual Detect
        20. 38.5.1.20 Data structures defining this bulk USB device. - CM
        21. 38.5.1.21 USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk) - CM
        22. 38.5.1.22 USB HUB Host example - CM
        23. 38.5.1.23 USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
        24. 38.5.1.24 USB HUB Host example
    6. 38.6 USB Registers
      1. 38.6.1 USB Base Address Table (C28)
      2. 38.6.2 USB_REGS Registers
      3. 38.6.3 USB Registers to Driverlib Functions
  41. 39â–º CONNECTIVITY MANAGER (CM)
    1. 39.1 Technical Reference Manual Overview
  42. 40Connectivity Manager Subsystem
    1. 40.1 Connectivity Manager Overview
    2. 40.2 Connectivity Manager Functional Block Diagram
    3. 40.3 Arm® Cortex®-M4 Processor Core Overview
  43. 41Connectivity Manager System Control and Interrupts
    1. 41.1  Introduction
    2. 41.2  Reset
      1. 41.2.1 CPU1 SYSRS
      2. 41.2.2 System Reset Request (CMSYSRESETREQ)
      3. 41.2.3 CM NMI Watchdog Reset (CMNMIWDRSTn)
      4. 41.2.4 CM Secure Code Copy Reset (CMSCCRESETn)
    3. 41.3  CM Clocking
      1. 41.3.1 CM Clock Sources
      2. 41.3.2 CM Derived Clocks
      3. 41.3.3 CM Device Clock Domains
        1. 41.3.3.1 Connectivity Manager Clock (CMCLK)
        2. 41.3.3.2 CM Peripheral Subsystem Clock (CM.PERx.SYSCLK)
        3. 41.3.3.3 MCAN Bit Clock
      4. 41.3.4 CM Clock Connectivity
    4. 41.4  SysTick
    5. 41.5  Watchdog Timer
    6. 41.6  Exceptions and NMI
      1. 41.6.1 CM Subsystem Nested Vectored Interrupt Controller
      2. 41.6.2 CM Subsystem Exceptions Handling
      3. 41.6.3 CM Subsystem Non-Maskable Interrupt (CMNMI) Module
        1. 41.6.3.1 CM Subsystem NMI Sources
          1. 41.6.3.1.1 RAM/ROM Uncorrectable Error
          2. 41.6.3.1.2 Reset Request from EtherCAT
          3. 41.6.3.1.3 Clock Fail Condition
          4. 41.6.3.1.4 MCAN Uncorrectable Error
          5. 41.6.3.1.5 CM Windowed Watchdog Timed Out
          6. 41.6.3.1.6 Flash Uncorrectable Error
        2. 41.6.3.2 CM Subsystem NMIWD Module
          1. 41.6.3.2.1 Emulation Considerations
        3. 41.6.3.3 Handling of CMNMI
      4. 41.6.4 CM Interrupts/NMI to CPU1/CPU2
    7. 41.7  Nested Vectored Interrupt Controller (NVIC)
      1. 41.7.1 Level-Sensitive and Pulse Interrupts
      2. 41.7.2 Hardware and Software Control of Interrupts
      3. 41.7.3 NVIC Registers Access
    8. 41.8  32-Bit CM CPU Timers 0/1/2
    9. 41.9  Memory Controller Module
      1. 41.9.1 Functional Description
        1. 41.9.1.1 Dedicated RAM
        2. 41.9.1.2 Shared RAM
        3. 41.9.1.3 MSG RAM
        4. 41.9.1.4 ROM
        5. 41.9.1.5 Interleaving
        6. 41.9.1.6 Access Arbitration
        7. 41.9.1.7 Access Protection
        8. 41.9.1.8 Memory Error Detection, Correction and Error Handling
          1. 41.9.1.8.1 Error Detection and Correction
          2. 41.9.1.8.2 Error Handling
          3. 41.9.1.8.3 Application Test Hooks for Error Detection and Correction
          4. 41.9.1.8.4 ROM Test
        9. 41.9.1.9 RAM Initialization
    10. 41.10 Memory Protection Unit (MPU)
      1. 41.10.1 Functional Description
      2. 41.10.2 Overlapping Regions
      3. 41.10.3 Sub-Regions
      4. 41.10.4 Programmers Model
    11. 41.11 Debug and Trace
      1. 41.11.1 Trace Port Interface Unit
    12. 41.12 CM-SysCtrl Registers
      1. 41.12.1  CM System Control Base Addresses
      2. 41.12.2  CM_MEMCFG_REGS Registers
      3. 41.12.3  CM_MEMORYDIAGERROR_REGS Registers
      4. 41.12.4  CM_MEMORYERROR_REGS Registers
      5. 41.12.5  CMSYSCTL_REGS Registers
      6. 41.12.6  CM_CPUTIMER_REGS Registers
      7. 41.12.7  MPU_REGS Registers
      8. 41.12.8  CM_NMI_INTRUPT_REGS Registers
      9. 41.12.9  NVIC Registers
      10. 41.12.10 SCB Registers
      11. 41.12.11 CSFR Registers
      12. 41.12.12 SYSTICK Registers
      13. 41.12.13 MPU Registers
      14. 41.12.14 CM_WD_REGS Registers
  44. 42Advanced Encryption Standard (AES) Accelerator
    1. 42.1 Introduction
      1. 42.1.1 AES Block Diagram
        1. 42.1.1.1 Interfaces
        2. 42.1.1.2 AES Subsystem
        3. 42.1.1.3 AES Wide-Bus Engine
      2. 42.1.2 AES Algorithm
    2. 42.2 AES Operating Modes
      1. 42.2.1  GCM Operation
      2. 42.2.2  CCM Operation
      3. 42.2.3  XTS Operation
      4. 42.2.4  ECB Feedback Mode
      5. 42.2.5  CBC Feedback Mode
      6. 42.2.6  CTR and ICM Feedback Modes
      7. 42.2.7  CFB Mode
      8. 42.2.8  F8 Mode
      9. 42.2.9  F9 Operation
      10. 42.2.10 CBC-MAC Operation
    3. 42.3 Extended and Combined Modes of Operations
      1. 42.3.1 GCM Protocol Operation
      2. 42.3.2 CCM Protocol Operation
      3. 42.3.3 Hardware Requests
    4. 42.4 AES Module Programming Guide
      1. 42.4.1 AES Low-Level Programming Models
        1. 42.4.1.1 Global Initialization
        2. 42.4.1.2 AES Operating Modes Configuration
        3. 42.4.1.3 AES Mode Configurations
        4. 42.4.1.4 AES Events Servicing
    5. 42.5 Software
      1. 42.5.1 AES Examples
        1. 42.5.1.1 AES ECB Encryption Example (CM) - CM
        2. 42.5.1.2 AES ECB De-cryption Example (CM) - CM
        3. 42.5.1.3 AES GCM Encryption Example (CM) - CM
        4. 42.5.1.4 AES GCM Decryption Example (CM) - CM
    6. 42.6 AES Registers
      1. 42.6.1 AES Base Addresses
      2. 42.6.2 AES_SS_REGS Registers
      3. 42.6.3 AES_REGS Registers
  45. 43Ethernet Media Access Controller (EMAC)
    1. 43.1 Introduction
      1. 43.1.1 Standard Compliance
      2. 43.1.2 MAC Features
        1. 43.1.2.1 MAC Tx and Rx Features
        2. 43.1.2.2 MAC Tx Features
        3. 43.1.2.3 MAC Rx Features
    2. 43.2 System Level Integration
      1. 43.2.1 Ethernet Signal Connection and Description
        1. 43.2.1.1 MII Interface Signals
        2. 43.2.1.2 RMII Interface Signals
        3. 43.2.1.3 RevMII Interface Signals
        4. 43.2.1.4 Pulse Per Second Signals
      2. 43.2.2 Configuring Device Pins
      3. 43.2.3 MAC Interface Selection
      4. 43.2.4 Clocks for Ethernet Module
      5. 43.2.5 RMII Mode Clocking
      6. 43.2.6 RevMII Mode Clocking
      7. 43.2.7 Configuring Trigger Sources for Time Stamping
        1. 43.2.7.1 Software Trigger for Time Stamping
      8. 43.2.8 Ethernet Interrupts
    3. 43.3 Features
      1. 43.3.1 Multiple Channels and Queues Support
        1. 43.3.1.1 Multiple Queues and Channels in Transmit Path
        2. 43.3.1.2 Multiple Queues and Channels in Receive Path
        3. 43.3.1.3 Rx Queue to DMA Mapping
        4. 43.3.1.4 Selection of Tag Priorities Assigned to Tx and Rx Queues
        5. 43.3.1.5 Rx Side Routing from MAC to Queues
      2. 43.3.2 IEEE 1588 Timestamp Support
        1. 43.3.2.1 Feature Description
          1. 43.3.2.1.1 Clock Types
            1. 43.3.2.1.1.1 Peer-to-Peer Transparent Clock (P2PTC) Message Support
            2. 43.3.2.1.1.2 Timestamp Correction
            3. 43.3.2.1.1.3 Ingress Correction
            4. 43.3.2.1.1.4 Egress Correction
            5. 43.3.2.1.1.5 Frequency Range of Reference Timing Clock
          2. 43.3.2.1.2 Maximum PTP Clock Frequency
          3. 43.3.2.1.3 Minimum PTP Clock Frequency
          4. 43.3.2.1.4 PTP Processing and Control
          5. 43.3.2.1.5 PTP Packets Over IPv4
          6. 43.3.2.1.6 PTP Frames Over IPv6
          7. 43.3.2.1.7 PTP Packets Over Ethernet
          8. 43.3.2.1.8 Transmit Path Functions
          9. 43.3.2.1.9 Receive Path Functions
        2. 43.3.2.2 IEEE 1588 System Time Source
          1. 43.3.2.2.1 External Timestamp Input
          2. 43.3.2.2.2 Internal Reference Time
          3. 43.3.2.2.3 System Time Register Module
        3. 43.3.2.3 IEEE 1588 Higher Word Register
        4. 43.3.2.4 IEEE 1588 Auxillary Snapshot
        5. 43.3.2.5 Flexible Pulse-Per-Second Output
          1. 43.3.2.5.1 PPS Start or Stop Time
          2. 43.3.2.5.2 PPS Width and Interval
      3. 43.3.3 Packet Filtering
        1. 43.3.3.1 Packet Filtering Sequence
        2. 43.3.3.2 Destination Address Filtering
        3. 43.3.3.3 Source Address Filtering
        4. 43.3.3.4 Inverse Filtering
        5. 43.3.3.5 VLAN Filtering
          1. 43.3.3.5.1 Comparison Modes
          2. 43.3.3.5.2 Filter Status
          3. 43.3.3.5.3 Stripping
        6. 43.3.3.6 Layer 3 and Layer 4 Filtering
          1. 43.3.3.6.1 Layer 3 Filtering
      4. 43.3.4 VLAN Support
        1. 43.3.4.1 Double VLAN Processing
          1. 43.3.4.1.1 Transmit Path
          2. 43.3.4.1.2 Receive Path
        2. 43.3.4.2 Double VLAN-Related Registers
        3. 43.3.4.3 Source Address and VLAN Insertion, Replacement, or Deletion
          1. 43.3.4.3.1 Programming VLAN Insertion, Replacement, or Deletion
        4. 43.3.4.4 Queue/Channel Based VLAN Tag Insertion on Tx
      5. 43.3.5 TCP/IP Offloading Features
        1. 43.3.5.1 Transmit Checksum Offload Engine
          1. 43.3.5.1.1 IP Header Checksum Engine
          2. 43.3.5.1.2 TCP/UDP/ICMP Checksum Engine
        2. 43.3.5.2 Receive Checksum Offload Engine
        3. 43.3.5.3 TCP/IP Segmentation Offload (TSO) Engine
          1. 43.3.5.3.1 DMA Operation with TSO Feature
            1. 43.3.5.3.1.1 TCP/IP Header Fields
            2. 43.3.5.3.1.2 Header and Payload Fields of Segmented Packets
        4. 43.3.5.4 Segmentation Versus Fragmentation
        5. 43.3.5.5 Using the IPv4 ARP Offload Engine
        6. 43.3.5.6 Energy Efficient Ethernet (EEE) Support
          1. 43.3.5.6.1 Magic Packet
          2. 43.3.5.6.2 Remote Wakeup Filter
          3. 43.3.5.6.3 Energy Efficient Ethernet (EEE)
            1. 43.3.5.6.3.1 Transmit Path Functions
          4. 43.3.5.6.4 Automated Entry/Exit of LPI mode in Transmit Path
          5. 43.3.5.6.5 Receive Path Functions
        7. 43.3.5.7 Automated Entry/Exit of LPI Mode in Transmit Path
        8. 43.3.5.8 Receive Path Functions
      6. 43.3.6 Loopback Mode
      7. 43.3.7 Reverse Media Independent Interface (RevMII)
        1. 43.3.7.1 RevMII Register Maps
        2. 43.3.7.2 MAC_RevMII_PHY_Control
        3. 43.3.7.3 MAC_RevMII_Common_Status
        4. 43.3.7.4 MAC_RevMII_Common_Ext_Status
        5. 43.3.7.5 MAC_RevMII_Interrupt_Status_Mask
        6. 43.3.7.6 MAC_RevMII_Remote_PHY_Status
        7. 43.3.7.7 MAC_RevMII_PHY_Status Register
    4. 43.4 Descriptors
      1. 43.4.1 Descriptor Structure
      2. 43.4.2 Transmit Descriptor
        1. 43.4.2.1 Transmit Normal Descriptor (Read Format)
          1. 43.4.2.1.1 TDES0 Normal Descriptor (Read Format)
          2. 43.4.2.1.2 TDES1 Normal Descriptor (Read Format)
          3. 43.4.2.1.3 TDES2 Normal Descriptor (Read Format)
          4. 43.4.2.1.4 TDES3 Normal Descriptor (Read Format)
        2. 43.4.2.2 Transmit Normal Descriptor (Write-Back Format)
          1. 43.4.2.2.1 TDES0 Normal Descriptor (Write-Back Format)
          2. 43.4.2.2.2 TDES1 Normal Descriptor (Write-Back Format)
          3. 43.4.2.2.3 TDES2 Normal Descriptor (Write-Back Format)
          4. 43.4.2.2.4 TDES3 Normal Descriptor (Write-Back Format)
        3. 43.4.2.3 Transmit Context Descriptor
          1. 43.4.2.3.1 TDES0 Context Descriptor
          2. 43.4.2.3.2 TDES1 Context Descriptor
          3. 43.4.2.3.3 TDES2 Context Descriptor
          4. 43.4.2.3.4 TDES3 Context Descriptor
      3. 43.4.3 Receive Descriptor
        1. 43.4.3.1 Receive Normal Descriptor (Read Format)
          1. 43.4.3.1.1 RDES0 Normal Descriptor (Read Format)
          2. 43.4.3.1.2 RDES1 Normal Descriptor (Read Format)
          3. 43.4.3.1.3 RDES2 Normal Descriptor (Read Format)
          4. 43.4.3.1.4 RDES3 Normal Descriptor (Read Format)
        2. 43.4.3.2 Receive Normal Descriptor (Write-Back Format)
          1. 43.4.3.2.1 RDES0 Normal Descriptor (Write-Back Format)
          2. 43.4.3.2.2 RDES1 Normal Descriptor (Write-Back Format)
          3. 43.4.3.2.3 RDES2 Normal Descriptor (Write-Back Format)
          4. 43.4.3.2.4 RDES3 Normal Descriptor (Write-Back Format)
        3. 43.4.3.3 Receive Context Descriptor
          1. 43.4.3.3.1 RDES0 Context Descriptor
          2. 43.4.3.3.2 RDES1 Context Descriptor
          3. 43.4.3.3.3 RDES2 Context Descriptor
          4. 43.4.3.3.4 RDES3 Context Descriptor
    5. 43.5 Programming
      1. 43.5.1 Initializing DMA
      2. 43.5.2 Initializing MTL Registers
      3. 43.5.3 Initializing MAC
      4. 43.5.4 Performing Normal Receive and Transmit Operation
      5. 43.5.5 Stopping and Starting Transmission
      6. 43.5.6 Programming Guidelines for Multi-Channel Multi-Queuing
        1. 43.5.6.1 Transmit
        2. 43.5.6.2 Receive
        3. 43.5.6.3 Programming Guidelines for Recovering from DMA Channel Failure
          1. 43.5.6.3.1 Recovering from the Receive DMA Channel Failure
          2. 43.5.6.3.2 Recovering from the Transmit DMA Channel Failure
        4. 43.5.6.4 Programming Guidelines for IEEE 1588 Timestamping
          1. 43.5.6.4.1 Initialization Guidelines for System Time Generation
          2. 43.5.6.4.2 System Time Correction
            1. 43.5.6.4.2.1 Coarse Correction Method
            2. 43.5.6.4.2.2 Fine Correction Method
        5. 43.5.6.5 Programming Guidelines for Energy Efficient Ethernet
          1. 43.5.6.5.1 Entering and Exiting the Tx LPI Mode
          2. 43.5.6.5.2 Gating Off the CSR Clock in the LPI Mode
          3. 43.5.6.5.3 Rx LPI Mode
          4. 43.5.6.5.4 Gating Off the CSR Clock in the Tx LPI Mode
        6. 43.5.6.6 Programming Guidelines for Flexible Pulse-Per-Second Output
          1. 43.5.6.6.1 Generating Single Pulse on PPS
          2. 43.5.6.6.2 Generating Next Pulse on PPS
          3. 43.5.6.6.3 Generating a Pulse Train on PPS
          4. 43.5.6.6.4 Generating an Interrupt without Affecting the PPS
        7. 43.5.6.7 Programming Guidelines for TSO
    6. 43.6 Software
      1. 43.6.1 ETHERNET Examples
        1. 43.6.1.1  Ethernet + IPC basic message passing example with interrupt - C28X_CM
        2. 43.6.1.2  Ethernet + IPC basic message passing example with interrupt - C28X_CM
        3. 43.6.1.3  Ethernet MAC Internal Loopback - CM
        4. 43.6.1.4  Ethernet Basic Transmit and Receive PHY Loopback - CM
        5. 43.6.1.5  Ethernet Threshold mode with level PHY loopback - CM
        6. 43.6.1.6  Ethernet PTP Basic Master - CM
        7. 43.6.1.7  Ethernet PTP Basic Slave - CM
        8. 43.6.1.8  Ethernet PTP Offload Master - CM
        9. 43.6.1.9  Ethernet PTP Offload Slave - CM
        10. 43.6.1.10 Ethernet MAC CRC and Checksum Offload - CM
        11. 43.6.1.11 Ethernet Transmit Segmentation Offload - CM
        12. 43.6.1.12 Ethernet MAC Internal Loopback - CM
        13. 43.6.1.13 Ethernet RevMII Example MII side - CM
        14. 43.6.1.14 Ethernet RevMII Example RevMII side - CM
        15. 43.6.1.15 Ethernet Low Latency Interrupt - CM
    7. 43.7 Ethernet Registers
      1. 43.7.1 Ethernet Base Addresses
      2. 43.7.2 ETHERNETSS_REGS Registers
      3. 43.7.3 EMAC_REGS Registers
  46. 44Generic Cyclic Redundancy Check (GCRC)
    1. 44.1 Generic CRC Overview
      1. 44.1.1 GCRC Features
      2. 44.1.2 GCRC Block Diagram
    2. 44.2 GCRC Functional Description
      1. 44.2.1 GCRC Polynomials
      2. 44.2.2 Fixed Polynomial
      3. 44.2.3 GCRC Data Input
      4. 44.2.4 GCRC Execution Sequence Flow
      5. 44.2.5 GCRC Transformations
        1. 44.2.5.1 Endianness Transformation
        2. 44.2.5.2 Mask Transformation
        3. 44.2.5.3 Bit Reversal Transformation
    3. 44.3 Software
      1. 44.3.1 GCRC Examples
        1. 44.3.1.1 GCRC example - CM
    4. 44.4 GCRC Registers
      1. 44.4.1 GCRC Base Addresses
      2. 44.4.2 GCRC_REGS Registers
  47. 45Modular Controller Area Network (MCAN)
    1. 45.1 MCAN Introduction
      1. 45.1.1 MCAN Related Collateral
      2. 45.1.2 MCAN Features
    2. 45.2 MCAN Environment
    3. 45.3 CAN Network Basics
    4. 45.4 MCAN Integration
    5. 45.5 MCAN Functional Description
      1. 45.5.1  Module Clocking Requirements
      2. 45.5.2  Interrupt Requests
      3. 45.5.3  Operating Modes
        1. 45.5.3.1 Software Initialization
        2. 45.5.3.2 Normal Operation
        3. 45.5.3.3 CAN FD Operation
      4. 45.5.4  Transmitter Delay Compensation
        1. 45.5.4.1 Description
        2. 45.5.4.2 Transmitter Delay Compensation Measurement
      5. 45.5.5  Restricted Operation Mode
      6. 45.5.6  Bus Monitoring Mode
      7. 45.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 45.5.7.1 Frame Transmission in DAR Mode
      8. 45.5.8  Clock Stop Mode
        1. 45.5.8.1 Suspend Mode
        2. 45.5.8.2 Wakeup Request
      9. 45.5.9  Test Modes
        1. 45.5.9.1 External Loop Back Mode
        2. 45.5.9.2 Internal Loop Back Mode
      10. 45.5.10 Timestamp Generation
        1. 45.5.10.1 External Timestamp Counter
      11. 45.5.11 Timeout Counter
      12. 45.5.12 Safety
        1. 45.5.12.1 ECC Wrapper
        2. 45.5.12.2 ECC Aggregator
          1. 45.5.12.2.1 ECC Aggregator Overview
          2. 45.5.12.2.2 ECC Aggregator Registers
        3. 45.5.12.3 Reads to ECC Control and Status Registers
        4. 45.5.12.4 ECC Interrupts
      13. 45.5.13 Rx Handling
        1. 45.5.13.1 Acceptance Filtering
          1. 45.5.13.1.1 Range Filter
          2. 45.5.13.1.2 Filter for Specific IDs
          3. 45.5.13.1.3 Classic Bit Mask Filter
          4. 45.5.13.1.4 Standard Message ID Filtering
          5. 45.5.13.1.5 Extended Message ID Filtering
        2. 45.5.13.2 Rx FIFOs
          1. 45.5.13.2.1 Rx FIFO Blocking Mode
          2. 45.5.13.2.2 Rx FIFO Overwrite Mode
        3. 45.5.13.3 Dedicated Rx Buffers
          1. 45.5.13.3.1 Rx Buffer Handling
      14. 45.5.14 Tx Handling
        1. 45.5.14.1 Transmit Pause
        2. 45.5.14.2 Dedicated Tx Buffers
        3. 45.5.14.3 Tx FIFO
        4. 45.5.14.4 Tx Queue
        5. 45.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 45.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 45.5.14.7 Transmit Cancellation
        8. 45.5.14.8 Tx Event Handling
      15. 45.5.15 FIFO Acknowledge Handling
      16. 45.5.16 Message RAM
        1. 45.5.16.1 Message RAM Configuration
        2. 45.5.16.2 Rx Buffer and FIFO Element
        3. 45.5.16.3 Tx Buffer Element
        4. 45.5.16.4 Tx Event FIFO Element
        5. 45.5.16.5 Standard Message ID Filter Element
        6. 45.5.16.6 Extended Message ID Filter Element
    6. 45.6 Software
      1. 45.6.1 MCAN Examples
        1. 45.6.1.1  MCAN Internal Loopback with Interrupt - CM
        2. 45.6.1.2  MCAN Internal Loopback with Interrupt
        3. 45.6.1.3  MCAN External Loopback with Interrupt - CM
        4. 45.6.1.4  MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
        5. 45.6.1.5  MCAN receive using Rx Buffer
        6. 45.6.1.6  MCAN External Reception (with mask filter) into RX-FIFO1
        7. 45.6.1.7  MCAN Classic frames transmission using Tx Buffer
        8. 45.6.1.8  MCAN External Reception (with RANGE filter) into RX-FIFO1
        9. 45.6.1.9  MCAN External Transmit using Tx Buffer
        10. 45.6.1.10 MCAN receive using Rx Buffer
        11. 45.6.1.11 MCAN Internal Loopback with Interrupt
        12. 45.6.1.12 MCAN External Transmit using Tx Buffer
    7. 45.7 MCAN Registers
      1. 45.7.1 MCAN Base Address Table (C28)
      2. 45.7.2 CM MCAN Base Address Table (CM)
      3. 45.7.3 MCANSS_REGS Registers
      4. 45.7.4 MCAN_REGS Registers
      5. 45.7.5 MCAN_ERROR_REGS Registers
  48. 46Connectivity Manager Inter-Integrated Circuit (I2C) Module
    1. 46.1 Introduction
      1. 46.1.1 Features
      2. 46.1.2 Block Diagram
    2. 46.2 Functional Description
      1. 46.2.1 I2C Bus Functional Overview
        1. 46.2.1.1  START and STOP Conditions
        2. 46.2.1.2  Data Format With 7-Bit Address
        3. 46.2.1.3  Data Validity
        4. 46.2.1.4  Acknowledge
        5. 46.2.1.5  Repeated START
          1. 46.2.1.5.1 Repeated Start for Master Transmit
          2. 46.2.1.5.2 Repeated Start for Master Receive
        6. 46.2.1.6  Clock Low Time-out (CLTO)
        7. 46.2.1.7  Dual Address
        8. 46.2.1.8  Arbitration
        9. 46.2.1.9  Glitch Suppression in Multi-Master Configuration
        10. 46.2.1.10 SMBus Operation
          1. 46.2.1.10.1 Quick Command
      2. 46.2.2 Available Speed Modes
        1. 46.2.2.1 Standard, Fast, and Fast Plus Modes
        2. 46.2.2.2 High-Speed Mode
      3. 46.2.3 Interrupts
      4. 46.2.4 Loopback Operation
      5. 46.2.5 FIFO and µDMA Operation
        1. 46.2.5.1 Master Module Burst Mode
          1. 46.2.5.1.1 Master Module µDMA Functionality
        2. 46.2.5.2 Slave Module
      6. 46.2.6 Command Sequence Flow Charts
        1. 46.2.6.1 I2C Master Command Sequences
        2. 46.2.6.2 I2C Slave Command Sequences
    3. 46.3 Initialization and Configuration
      1. 46.3.1 Configure the I2C Module to Transmit a Single Byte as a Master
      2. 46.3.2 Configure the I2C Master to High-Speed Mode
    4. 46.4 CM I2C Registers
      1. 46.4.1 CM I2C Base Addresses
      2. 46.4.2 CM_I2C_REGS Registers
      3. 46.4.3 CM_I2C_WRITE_REGS Registers
  49. 47Synchronous Serial Interface (SSI)
    1. 47.1 Introduction
      1. 47.1.1 Features
      2. 47.1.2 Block Diagram
    2. 47.2 Functional Description
      1. 47.2.1 Bit Rate Generation
      2. 47.2.2 FIFO Operation
        1. 47.2.2.1 Transmit FIFO
        2. 47.2.2.2 Receive FIFO
      3. 47.2.3 SSInFSS Function
      4. 47.2.4 Interrupts
      5. 47.2.5 Frame Formats
        1. 47.2.5.1 Freescale SPI Frame Format
          1. 47.2.5.1.1 SPO Clock Polarity Bit
          2. 47.2.5.1.2 SPH Phase Control Bit
        2. 47.2.5.2 Freescale SPI Frame Format with SPO=0 and SPH=0
        3. 47.2.5.3 Freescale SPI Frame Format with SPO=0 and SPH=1
        4. 47.2.5.4 Freescale SPI Frame Format with SPO=1 and SPH=0
        5. 47.2.5.5 Freescale SPI Frame Format with SPO=1 and SPH=1
      6. 47.2.6 DMA Operation
    3. 47.3 Initialization and Configuration
    4. 47.4 Software
      1. 47.4.1 SSI Examples
        1. 47.4.1.1 SSI Loopback example with interrupts - CM
        2. 47.4.1.2 SSI Loopback example with UDMA - CM
    5. 47.5 SSI Registers
      1. 47.5.1 SSI Base Addresses
      2. 47.5.2 SSI_REGS Registers
  50. 48Universal Asynchronous Receiver/Transmitter (UART)
    1. 48.1 Introduction
      1. 48.1.1 Features
      2. 48.1.2 Block Diagram
    2. 48.2 Functional Description
      1. 48.2.1 Transmit and Receive Logic
      2. 48.2.2 Baud-Rate Generation
      3. 48.2.3 Data Transmission
      4. 48.2.4 Serial IR (SIR)
      5. 48.2.5 9-Bit UART Mode
      6. 48.2.6 FIFO Operation
      7. 48.2.7 Interrupts
      8. 48.2.8 Loopback Operation
      9. 48.2.9 DMA Operation
    3. 48.3 Initialization and Configuration
    4. 48.4 Software
      1. 48.4.1 UART Examples
        1. 48.4.1.1 UART Echoback - CM
        2. 48.4.1.2 UART Loopback example with UDMA - CM
    5. 48.5 UART Registers
      1. 48.5.1 UART Base Addresses
      2. 48.5.2 UART_REGS Registers
      3. 48.5.3 UART_REGS_WRITE Registers
  51. 49Micro Direct Memory Access (µDMA)
    1. 49.1 Introduction
      1. 49.1.1 Features
      2. 49.1.2 Block Diagram
    2. 49.2 Functional Description
      1. 49.2.1  Channel Assignments
      2. 49.2.2  Priority
      3. 49.2.3  Arbitration Size
      4. 49.2.4  Request Types
        1. 49.2.4.1 Single Request
        2. 49.2.4.2 Burst Request
      5. 49.2.5  Channel Configuration
      6. 49.2.6  Transfer Modes
        1. 49.2.6.1 Stop Mode
        2. 49.2.6.2 Basic Mode
        3. 49.2.6.3 Auto Mode
        4. 49.2.6.4 Ping-Pong
        5. 49.2.6.5 Memory Scatter-Gather
        6. 49.2.6.6 Peripheral Scatter-Gather
      7. 49.2.7  Transfer Size and Increment
      8. 49.2.8  Peripheral Interface
        1. 49.2.8.1 FIFO Peripherals
        2. 49.2.8.2 Trigger Peripherals
      9. 49.2.9  Software Request
      10. 49.2.10 Interrupts and Errors
    3. 49.3 Initialization and Configuration
      1. 49.3.1 Module Initialization
      2. 49.3.2 Configuring a Memory-to-Memory Transfer
        1. 49.3.2.1 Configure the Channel Attributes
        2. 49.3.2.2 Configure the Channel Control Structure
          1. 49.3.2.2.1 Configure the Source and Destination
          2. 49.3.2.2.2 Configure Peripheral Interrupts
        3. 49.3.2.3 Start the Transfer
      3. 49.3.3 Configuring a Peripheral for Simple Transmit
        1. 49.3.3.1 Configure the Channel Attributes
        2. 49.3.3.2 Configure the Channel Control Structure
          1. 49.3.3.2.1 Configure the Source and Destination
        3. 49.3.3.3 Start the Transfer
      4. 49.3.4 Configuring a Peripheral for Ping-Pong Receive
        1. 49.3.4.1 Configure the Channel Attributes
        2. 49.3.4.2 Configure the Channel Control Structure
          1. 49.3.4.2.1 Configure the Source and Destination
        3. 49.3.4.3 Configure and Enable the Peripheral Interrupt
        4. 49.3.4.4 Process Interrupts
      5. 49.3.5 Configuring Channel Assignments
    4. 49.4 Software
      1. 49.4.1 UDMA Examples
        1. 49.4.1.1 uDMA RAM to RAM transfer - CM
        2. 49.4.1.2 uDMA RAM to RAM transfer - CM
    5. 49.5 µDMA Registers
      1. 49.5.1 µDMA Base Addresses
      2. 49.5.2 UDMAREGS Registers
      3. 49.5.3 UDMACHDES Registers
  52. 50Revision History

43.7.3 EMAC_REGS Registers

Table 43-92 lists the memory-mapped registers for the EMAC_REGS registers. All register offset addresses not listed in Table 43-92 should be considered as reserved locations and the register contents should not be modified.

Table 43-92 EMAC_REGS Registers
OffsetAcronymRegister NameSection
0hMAC_ConfigurationThe MAC Configuration Register establishes the operating mode of the MAC.Go
4hMAC_Ext_ConfigurationThe MAC Extended Configuration Register establishes the operating mode of the MAC.Go
8hMAC_Packet_FilterThe MAC Packet Filter register contains the filter controls for receiving packets.
Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering.
The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets.		Go
ChMAC_Watchdog_TimeoutThe Watchdog Timeout register controls the watchdog timeout for received packets.Go
10hMAC_Hash_Table_Reg0The Hash Table Register 0 contains the first 32 bits of the hash table, when the width of the hash table is 128 or 256 bits.
You can specify the width of the hash table by using the Hash Table Size option in coreConsultant.
The Hash table is used for group address filtering.
For hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six (seven in 128-bit Hash or eight in 256-bit Hash) bits of the CRC register are used to index the content of the Hash table.
The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register.
For example, a hash value of 6'b100000 (in 64-bit Hash) selects Bit 0 of the Hash Table Register 1, a value of 7b'1110000 (in 128-bit Hash) selects Bit 16 of the Hash Table Register 3 and a value of 8b'10111111 (in 256-bit Hash) selects Bit 31 of the Hash Table Register 5.
The hash value of the destination address is calculated in the following way:
- Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32).
- Perform bitwise reversal for the value obtained in Step 1.
- Take the upper 6 (or 7 or 8) bits from the value obtained in Step 2.
If the corresponding bit value of the register is 1'b1, the packet is accepted.
Otherwise, it is rejected.
If the PM bit is set in MAC_Packet_Filter, all multicast packets are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
If double-synchronization is enabled, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.		Go
14hMAC_Hash_Table_Reg1The Hash Table Register 1 contains the second 32 bits of the hash table.
You can specify the width of the hash table by using the Hash Table Size option in coreConsultant.
The Hash table is used for group address filtering.
For hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six (seven in 128-bit Hash or eight in 256-bit Hash) bits of the CRC register are used to index the content of the Hash table.
The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register.
For example, a hash value of 6'b100000 (in 64-bit Hash) selects Bit 0 of the Hash Table Register 1, a value of 7b'1110000 (in 128-bit Hash) selects Bit 16 of the Hash Table Register 3 and a value of 8b'10111111 (in 256-bit Hash) selects Bit 31 of the Hash Table Register 5.
The hash value of the destination address is calculated in the following way:
- Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32).
- Perform bitwise reversal for the value obtained in Step 1.
- Take the upper 6 (or 7 or 8) bits from the value obtained in Step 2.
If the corresponding bit value of the register is 1'b1, the packet is accepted.
Otherwise, it is rejected.
If the PM bit is set in MAC_Packet_Filter, all multicast packets are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
If double-synchronization is enabled, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.		Go
50hMAC_VLAN_Tag_CtrlThis register is the redefined format of the MAC VLAN Tag Register.
It is used for indirect addressing.
It contains the address offset, command type and Busy Bit for CSR access of the Per VLAN Tag registers.		Go
54hMAC_VLAN_Tag_DataThis register holds the read/write data for Indirect Access of the Per VLAN Tag registers.
During the read access, this field contains valid read data only after the OB bit is reset.
During the write access, this field should be valid prior to setting the OB bit in the MAC_VLAN_Tag_Ctrl Register.		Go
58hMAC_VLAN_Hash_TableWhen VTHM bit of the MAC_VLAN_Tag register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag.
For hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of MAC_VLAN_Tag Register) in the incoming packet is passed through the CRC logic.
The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table.
For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash table.
The hash value of the destination address is calculated in the following way:
- Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3).
- Perform bitwise reversal for the value obtained in step 1.
- Take the upper four bits from the value obtained in step 2.
If the VLAN hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written.
- If double-synchronization is enabled, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.		Go
60hMAC_VLAN_InclThe VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets.
It also contains the VLAN tag insertion controls.		Go
64hMAC_Inner_VLAN_InclThe Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet.
It also contains the inner VLAN tag insertion controls.		Go
70hMAC_Q0_Tx_Flow_CtrlThe Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC.
A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet.
The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet.
The Busy bit remains set until the control packet is transferred onto the cable.
The application must make sure that the Busy bit is cleared before writing to the register.
When the PFCE bit in the MAC_Rx_Flow_Ctrl register is enabled, this register controls the generation of Priority Flow Control (PFC) frames with priorities mapped according to PSRQ0 in the MAC_RxQ_Ctrl2 register.
Go
90hMAC_Rx_Flow_CtrlThe Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet.Go
94hMAC_RxQ_Ctrl4The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues.Go
A0hMAC_RxQ_Ctrl0The Receive Queue Control 0 register controls the queue management in the MAC Receiver.
Note: In multiple Rx queues configuration, all the queues are disabled by default.
Enable the Rx queue by programming the corresponding field in this register.		Go
A4hMAC_RxQ_Ctrl1The Receive Queue Control 1 register controls the routing of multicast, broadcast, AV, DCB, and untagged packets to the Rx queues.Go
A8hMAC_RxQ_Ctrl2This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3.Go
B0hMAC_Interrupt_StatusThe Interrupt Status register contains the status of interrupts.Go
B4hMAC_Interrupt_EnableThe Interrupt Enable register contains the masks for generating the interrupts.Go
B8hMAC_Rx_Tx_StatusThe Receive Transmit Status register contains the Receive and Transmit Error status.Go
C0hMAC_PMT_Control_StatusThe PMT Control and Status Register.Go
C4hMAC_RWK_Packet_FilterThe wkuppktfilter_reg register at address 0C4H loads the Wake-up Packet Filter register.
To load values in a Wake-up Packet Filter register, the entire register (wkuppktfilter_reg) must be written.
The wkuppktfilter_reg register is loaded by sequentially loading the eight, sixteen or thirty two register values in address (0C4H) for wkuppktfilter_reg0, wkuppktfilter_reg1,..
wkuppktfilter_reg31, respectively.
The wkuppktfilter_reg register is read in a similar way.
The DWC_ether_qos updates the wkuppktfilter_reg register current pointer value in Bits[26:24] of MAC_PMT_Control_Status register.
Filter i Byte Mask: The filter i byte mask register defines the bytes of the packet that are examined by filter i (0, 1, 2, 3,..,15) to determine whether or not a packet is a wake-up packet.
- The MSB (31st bit) must be zero.
- Bit j[30:0] is the byte mask.
- If Bit j (byte number) of the byte mask is set, the CRC block processes the Filter i Offset + j of the incoming packet; otherwise Filter i Offset + j is ignored.
Filter i Command: The 4-bit filter i command controls the filter i operation.
- Bit 3 specifies the address type, defining the destination address type of the pattern.
When the bit is set, the pattern applies to only multicast packets; when the bit is reset, the pattern applies only to unicast packet.
- Bit 2 (Inverse Mode), when set, reverses the logic of the CRC16 hash function signal, to reject a packet with matching CRC_16 value.
- Bit 2, along with Bit 1, allows a MAC to reject a subset of remote wake-up packets by creating filter logic such as "Pattern 1 AND NOT Pattern 2".
- Bit 1 (And_Previous) implements the Boolean logic.
When set, the result of the current entry is logically ANDed with the result of the previous filter.
This AND logic allows a filter pattern longer than 32 bytes by splitting the mask among two, three, or four filters.
This depends on the number of filters that have the And_Previous bit set.
- Bit 0 is the enable for filter i.
If Bit 0 is not set, filter i is disabled.
Filter i Offset: This filter i offset register defines the offset (within the packet) from which the filter i examines the packets.
- This 8-bit pattern-offset is the offset for the filter i first byte to be examined.
- The minimum allowed offset is 12, which refers to the 13th byte of the packet.
- The offset value 0 refers to the first byte of the packet.
Filter i CRC-16: This filter i CRC-16 register contains the CRC_16 value calculated from the pattern and also the byte mask programmed to the wake-up filter register block.
- The 16-bit CRC calculation uses the following polynomial:
G(x) = x^16 + x^15 + x^2 + 1
Each mask, used in the hash function calculation, is compared with a 16-bit value associated with that mask.
Each filter has the following:
- 32-bit Mask: Each bit in this mask corresponds to one byte in the detected packet.
If the bit is 1', the corresponding byte is taken into the CRC16 calculation.
- 8-bit Offset Pointer: Specifies the byte to start the CRC16 computation.
The pointer and the mask are used together to locate the bytes to be used in the CRC16 calculations.
- Note: If you are accessing these registers in byte or half-word mode, the internal counter to access the appropriate wkuppktfilter_reg is incremented when CPU accesses Lane 3 (or Lane 0 in big-endian mode).
- Note: When any Register content is being transferred to a different clock domain after a write operation, there should not be any further writes to the same location until the first write is updated.
Otherwise, the second write operation does not get updated to the destination clock domain.
Therefore, the delay between two writes to the same register location should be at least 4 cycles of the destination clock (PHY receive clock, PHY transmit clock, or PTP clock).
Notes on And_Previous bit setting
The And_Previous bit setting is applicable within a set of 4 filters.
- Setting of And_Previous bit of filter that is not enabled has no effect.
In other words, setting And_Previous bit of lowest number filter in the set of 4 filters has no effect.
For example, setting of And_Previous bit of Filter 0 has no effect.

- If And_Previous bit is set for filter to form AND chained filter, the AND chain breaks at the point any filter is not enabled.
For example:
If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set) but Filter 1 is not enabled (bit 0 of in Filter 1 command is reset), then only Filter 2 result is considered.
If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 3 And_Previous bit is set (bit 1 of Filter 3 command is set), but Filter 1 is not enabled (bit 0 of in Filter 1 command is reset), then only Filter 2 result ANDed with Filter 3
result is considered.
If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 3 And_Previous bit is set (bit 1 of Filter 3 command is set), but Filter 2 is not enabled (bit 0 of in Filter 2 command is reset), then since setting of Filter 2 And_Previous bit
has no effect only Filter 1 result ORed with Filter 3 result is considered.
- If filters chained by And_Previous bit setting have complementary programming, then a frame may never pass the AND chained filter.
For example, if Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 1 Address_Type bit is set (bit 3 of Filter 1 command is set) indicating multicast detection and Filter 2 Address_Type bit is reset (bit 3 of Filter 2 command is reset) indicating unicast detection or vice versa, a remote wakeup frame does not pass the AND chained filter as a remote wakeup frame cannot be of both unicast and multicast address type.
Go
D0hMAC_LPI_Control_StatusThe LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status.
The status bits are cleared when this register is read.		Go
D4hMAC_LPI_Timers_ControlThe LPI Timers Control register controls the timeout values in the LPI states.
It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.		Go
D8hMAC_LPI_Entry_TimerThis register controls the Tx LPI entry timer.
This counter is enabled only when bit[20](LPITE) bit of MAC_LPI_Control_Status is set to 1.		Go
DChMAC_1US_Tic_CounterThis register controls the generation of the Reference time (1 microsecond tic) for all the LPI timers.
This timer has to be programmed by the software initially.		Go
110hMAC_VersionThe version register identifies the version of the DWC_ether_qos.
This register contains two bytes: one that Synopsys uses to identify the core release number, and the other that you set while configuring the core.		Go
114hMAC_DebugThe Debug register provides the debug status of various MAC blocks.Go
11ChMAC_HW_Feature0This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos.
The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
Note: All bits are set or reset according to the features selected while configuring the core in coreConsultant.
Go
120hMAC_HW_Feature1This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos.
The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
Note: All bits are set or reset according to the features selected while configuring the core in coreConsultant.
Go
124hMAC_HW_Feature2This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos.
The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.		Go
128hMAC_HW_Feature3This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos.
The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.		Go
200hMAC_MDIO_AddressThe MDIO Address register controls the management cycles to external PHY through a management interface.Go
204hMAC_MDIO_DataThe MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address.
This register also stores the Read data from the PHY register located at the address specified by MDIO Address register.		Go
210hMAC_ARP_AddressThe ARP Address register contains the IPv4 Destination Address of the MAC.
Note: IP address should be written to this register in host byte order format.		Go
230hMAC_CSR_SW_CtrlThis register contains SW programmable controls for changing the CSR access response and status bits clearing.Go
238hMAC_Ext_Cfg1This register contains Split mode control field and offset field for Split Header feature.Go
300hMAC_Address0_HighThe MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station.
The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register.
For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
304hMAC_Address0_LowThe MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station.Go
308hMAC_Address1_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
30ChMAC_Address1_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
310hMAC_Address2_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
314hMAC_Address2_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
318hMAC_Address3_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
31ChMAC_Address3_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
320hMAC_Address4_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
324hMAC_Address4_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
328hMAC_Address5_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
32ChMAC_Address5_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
330hMAC_Address6_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
334hMAC_Address6_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
338hMAC_Address7_HighThe MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written.
For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.		Go
33ChMAC_Address7_LowThe MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.Go
700hMMC_ControlThis register establishes the operating mode of MMC.Go
704hMMC_Rx_InterruptThis register maintains the interrupts generated from all Receive statistics counters.

The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur:
- Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter).

- Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter).

When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones.
The MMC Receive Interrupt register
is a 32 bit register.
An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read.
The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.

Note: R_SS_RC means that this register bit is set internally, and it is cleared when the Counter register is read.

Go
708hMMC_Tx_InterruptThis register maintains the interrupts generated from all Transmit statistics counters.

The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values
(0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter).

When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones.

The MMC Transmit Interrupt register is a 32 bit register.
An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read.

The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.

Go
70ChMMC_Rx_Interrupt_MaskThis register maintains the masks for interrupts generated from all Receive statistics counters.

The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values.

This register is 32 bit wide.		Go
710hMMC_Tx_Interrupt_MaskThis register maintains the masks for interrupts generated from all Transmit statistics counters.

The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values.
This register is 32 bit wide.		Go
714hTx_Octet_Count_Good_BadThis register provides the number of bytes transmitted by the DWC_ether_qos, exclusive of preamble and retried bytes, in good and bad packets.Go
718hTx_Packet_Count_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos, exclusive of retried packets.Go
71ChTx_Broadcast_Packets_GoodThis register provides the number of good broadcast packets transmitted by DWC_ether_qos.Go
720hTx_Multicast_Packets_GoodThis register provides the number of good multicast packets transmitted by DWC_ether_qos.Go
724hTx_64Octets_Packets_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes, exclusive of preamble and retried packets.Go
728hTx_65To127Octets_Packets_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried packets.Go
72ChTx_128To255Octets_Packets_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes, exclusive of preamble and retried packets.Go
730hTx_256To511Octets_Packets_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes, exclusive of preamble and retried packets.Go
734hTx_512To1023Octets_Packets_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes, exclusive of preamble and retried packets.Go
738hTx_1024ToMaxOctets_Packets_Good_BadThis register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes, exclusive of preamble and retried packets.Go
73ChTx_Unicast_Packets_Good_BadThis register provides the number of good and bad unicast packets transmitted by DWC_ether_qos.Go
740hTx_Multicast_Packets_Good_BadThis register provides the number of good and bad multicast packets transmitted by DWC_ether_qos.Go
744hTx_Broadcast_Packets_Good_BadThis register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos.Go
748hTx_Underflow_Error_PacketsThis register provides the number of packets aborted by DWC_ether_qos because of packets underflow error.Go
74ChTx_Single_Collision_Good_PacketsThis register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode.Go
750hTx_Multiple_Collision_Good_PacketsThis register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode.Go
754hTx_Deferred_PacketsThis register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode.Go
758hTx_Late_Collision_PacketsThis register provides the number of packets aborted by DWC_ether_qos because of late collision error.Go
75ChTx_Excessive_Collision_PacketsThis register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors.Go
760hTx_Carrier_Error_PacketsThis register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier).Go
764hTx_Octet_Count_GoodThis register provides the number of bytes transmitted by DWC_ether_qos, exclusive of preamble, only in good packets.Go
768hTx_Packet_Count_GoodThis register provides the number of good packets transmitted by DWC_ether_qos.Go
76ChTx_Excessive_Deferral_ErrorThis register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times).Go
770hTx_Pause_PacketsThis register provides the number of good Pause packets transmitted by DWC_ether_qos.Go
774hTx_VLAN_Packets_GoodThis register provides the number of good VLAN packets transmitted by DWC_ether_qos.Go
778hTx_OSize_Packets_GoodThis register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the MAC_Configuration register).Go
780hRx_Packets_Count_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos.Go
784hRx_Octet_Count_Good_BadThis register provides the number of bytes received by DWC_ther_qos, exclusive of preamble, in good and bad packets.Go
788hRx_Octet_Count_GoodThis register provides the number of bytes received by DWC_ether_qos, exclusive of preamble, only in good packets.Go
78ChRx_Broadcast_Packets_GoodThis register provides the number of good broadcast packets received by DWC_ether_qos.Go
790hRx_Multicast_Packets_GoodThis register provides the number of good multicast packets received by DWC_ether_qos.Go
794hRx_CRC_Error_PacketsThis register provides the number of packets received by DWC_ether_qos with CRC error.Go
798hRx_Alignment_Error_PacketsThis register provides the number of packets received by DWC_ether_qos with alignment (dribble) error.
It is valid only in 10/100 mode.		Go
79ChRx_Runt_Error_PacketsThis register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error.Go
7A0hRx_Jabber_Error_PacketsThis register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error.
If Jumbo Packet mode is enabled, packets of length greater than 9,018 bytes (9,022 bytes for VLAN tagged) are considered as giant packets.		Go
7A4hRx_Undersize_Packets_GoodThis register provides the number of packets received by DWC_ether_qos with length less than 64 bytes, without any errors.Go
7A8hRx_Oversize_Packets_GoodThis register provides the number of packets received by DWC_ether_qos without errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the MAC_Configuration register).Go
7AChRx_64Octets_Packets_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes, exclusive of the preamble.Go
7B0hRx_65To127Octets_Packets_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.Go
7B4hRx_128To255Octets_Packets_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes, exclusive of the preamble.Go
7B8hRx_256To511Octets_Packets_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes, exclusive of the preamble.Go
7BChRx_512To1023Octets_Packets_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes, exclusive of the preamble.Go
7C0hRx_1024ToMaxOctets_Packets_Good_BadThis register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes, exclusive of the preamble.Go
7C4hRx_Unicast_Packets_GoodThis register provides the number of good unicast packets received by DWC_ether_qos.Go
7C8hRx_Length_Error_PacketsThis register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size), for all packets with valid length field.Go
7CChRx_Out_Of_Range_Type_PacketsThis register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).Go
7D0hRx_Pause_PacketsThis register provides the number of good and valid Pause packets received by DWC_ether_qos.Go
7D4hRx_FIFO_Overflow_PacketsThis register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos.Go
7D8hRx_VLAN_Packets_Good_BadThis register provides the number of good and bad VLAN packets received by DWC_ether_qos.Go
7DChRx_Watchdog_Error_PacketsThis register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when JE and WD bits are reset in MAC_Configuration register), 10,240 bytes (when JE bit is set and WD bit is reset in MAC_Configuration register), 16,384 bytes (when WD bit is set in MAC_Configuration register) or the value programmed in the MAC_Watchdog_Timeout register).Go
7E0hRx_Receive_Error_PacketsThis register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface.Go
7E4hRx_Control_Packets_GoodThis register provides the number of good control packets received by DWC_ether_qos.Go
7EChTx_LPI_USEC_CntrThis register provides the number of microseconds Tx LPI is asserted by DWC_ether_qos.Go
7F0hTx_LPI_Tran_CntrThis register provides the number of times DWC_ether_qos has entered Tx LPI.Go
7F4hRx_LPI_USEC_CntrThis register provides the number of microseconds Rx LPI is sampled by DWC_ether_qos.Go
7F8hRx_LPI_Tran_CntrThis register provides the number of times DWC_ether_qos has entered Rx LPI.Go
800hMMC_IPC_Rx_Interrupt_MaskThis register maintains the mask for the interrupt generated from the receive IPC statistic counters.

The MMC Receive Checksum Off load Interrupt Mask register maintains the masks for the interrupts generated when the receive IPC (Checksum Off load) statistic counters reach half their maximum value, and when they reach their maximum values.
This register is 32 bits wide.		Go
808hMMC_IPC_Rx_InterruptThis register maintains the interrupt that the receive IPC statistic counters generate.
The MMC Receive Checksum Offload Interrupt register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter).
When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones.

The MMC Receive Checksum Offload Interrupt register is 32 bit wide.
When the MMC IPC counter that caused the interrupt is read, its corresponding interrupt bit is cleared.
The counter's least-significant byte lane (Bits[7:0]) must be read to clear the interrupt bit.

Go
810hRxIPv4_Good_PacketsThis register provides the number of good IPv4 datagrams received by DWC_ether_qos with the TCP, UDP, or ICMP payload.Go
814hRxIPv4_Header_Error_PacketsRxIPv4 Header Error Packets
This register provides the number of IPv4 datagrams received by DWC_ether_qos with header (checksum, length, or version mismatch) errors.		Go
818hRxIPv4_No_Payload_PacketsThis register provides the number of IPv4 datagram packets received by DWC_ether_qos that did not have a TCP, UDP, or ICMP payload.Go
81ChRxIPv4_Fragmented_PacketsThis register provides the number of good IPv4 datagrams received by DWC_ether_qos with fragmentation.Go
820hRxIPv4_UDP_Checksum_Disabled_PacketsThis register provides the number of good IPv4 datagrams received by DWC_ether_qos that had a UDP payload with checksum disabled.Go
824hRxIPv6_Good_PacketsThis register provides the number of good IPv6 datagrams received by DWC_ether_qos with the TCP, UDP, or ICMP payload.Go
828hRxIPv6_Header_Error_PacketsThis register provides the number of IPv6 datagrams received by DWC_ether_qos with header (length or version mismatch) errors.Go
82ChRxIPv6_No_Payload_PacketsThis register provides the number of IPv6 datagram packets received by DWC_ether_qos that did not have a TCP, UDP, or ICMP payload.
This includes all IPv6 datagrams with fragmentation or security extension headers.		Go
830hRxUDP_Good_PacketsThis register provides the number of good IP datagrams received by DWC_ether_qos with a good UDP payload.
This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented.		Go
834hRxUDP_Error_PacketsThis register provides the number of good IP datagrams received by DWC_ether_qos whose UDP payload has a checksum error.Go
838hRxTCP_Good_PacketsThis register provides the number of good IP datagrams received by DWC_ether_qos with a good TCP payload.Go
83ChRxTCP_Error_PacketsThis register provides the number of good IP datagrams received by DWC_ether_qos whose TCP payload has a checksum error.Go
840hRxICMP_Good_PacketsThis register provides the number of good IP datagrams received by DWC_ether_qos with a good ICMP payload.Go
844hRxICMP_Error_PacketsThis register provides the number of good IP datagrams received by DWC_ether_qos whose ICMP payload has a checksum error.Go
850hRxIPv4_Good_OctetsThis register provides the number of bytes received by DWC_ether_qos in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
854hRxIPv4_Header_Error_OctetsThis register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams with header errors (checksum, length, version mismatch).
The value in the Length field of IPv4 header is used to update this counter.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
858hRxIPv4_No_Payload_OctetsThis register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload.
The value in the Length field of IPv4 header is used to update this counter.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
85ChRxIPv4_Fragmented_OctetsThis register provides the number of bytes received by DWC_ether_qos in fragmented IPv4 datagrams.
The value in the Length field of IPv4 header is used to update this counter.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
860hRxIPv4_UDP_Checksum_Disable_OctetsThis register provides the number of bytes received by DWC_ether_qos in a UDP segment that had the UDP checksum disabled.
This counter does not count IP Header bytes.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
864hRxIPv6_Good_OctetsThis register provides the number of bytes received by DWC_ether_qos in good IPv6 datagrams encapsulating TCP, UDP, or ICMP data.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
868hRxIPv6_Header_Error_OctetsThis register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams with header errors (length, version mismatch).
The value in the Length field of IPv6 header is used to update this counter.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
86ChRxIPv6_No_Payload_OctetsThis register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload.
The value in the Length field of IPv6 header is used to update this counter.
(Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.		Go
870hRxUDP_Good_OctetsThis register provides the number of bytes received by DWC_ether_qos in a good UDP segment.
This counter does not count IP header bytes.		Go
874hRxUDP_Error_OctetsThis register provides the number of bytes received by DWC_ether_qos in a UDP segment that had checksum errors.
This counter does not count IP header bytes.		Go
878hRxTCP_Good_OctetsThis register provides the number of bytes received by DWC_ether_qos in a good TCP segment.
This counter does not count IP header bytes.		Go
87ChRxTCP_Error_OctetsThis register provides the number of bytes received by DWC_ether_qos in a TCP segment that had checksum errors.
This counter does not count IP header bytes.		Go
880hRxICMP_Good_OctetsThis register provides the number of bytes received by DWC_ether_qos in a good ICMP segment.
This counter does not count IP header bytes.		Go
884hRxICMP_Error_OctetsThis register provides the number of bytes received by DWC_ether_qos in a ICMP segment that had checksum errors.
This counter does not count IP header bytes.		Go
900hMAC_L3_L4_Control0The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.Go
904hMAC_Layer4_Address0The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core.
When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written.
For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.		Go
910hMAC_Layer3_Addr0_Reg0For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field.
For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.		Go
914hMAC_Layer3_Addr1_Reg0For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field.
For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.		Go
918hMAC_Layer3_Addr2_Reg0The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.		Go
91ChMAC_Layer3_Addr3_Reg0The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.		Go
930hMAC_L3_L4_Control1The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.Go
934hMAC_Layer4_Address1The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core.
When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written.
For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.		Go
940hMAC_Layer3_Addr0_Reg1For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field.
For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.		Go
944hMAC_Layer3_Addr1_Reg1For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field.
For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.		Go
948hMAC_Layer3_Addr2_Reg1The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.		Go
94ChMAC_Layer3_Addr3_Reg1The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.		Go
960hMAC_L3_L4_Control2The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.Go
964hMAC_Layer4_Address2The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core.
When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written.
For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.		Go
970hMAC_Layer3_Addr0_Reg2For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field.
For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.		Go
974hMAC_Layer3_Addr1_Reg2For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field.
For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.		Go
978hMAC_Layer3_Addr2_Reg2The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.		Go
97ChMAC_Layer3_Addr3_Reg2The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.		Go
990hMAC_L3_L4_Control3The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.Go
994hMAC_Layer4_Address3The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core.
When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written.
For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.		Go
9A0hMAC_Layer3_Addr0_Reg3For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field.
For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.		Go
9A4hMAC_Layer3_Addr1_Reg3For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field.
For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.		Go
9A8hMAC_Layer3_Addr2_Reg3The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.		Go
9AChMAC_Layer3_Addr3_Reg3The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets.
For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.		Go
B00hMAC_Timestamp_ControlThis register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver.Go
B04hMAC_Sub_Second_IncrementThis register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock.Go
B08hMAC_System_Time_SecondsThe System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC.
Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from clk_ptp_ref_i to CSR clock).		Go
B0ChMAC_System_Time_NanosecondsThe System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC.Go
B10hMAC_System_Time_Seconds_UpdateThe System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC.
You must write both registers before setting the TSINIT or TSUPDT bits in EMAC_REGS/EQOS_MAC/MAC_Timestamp_Control.		Go
B14hMAC_System_Time_Nanoseconds_UpdateMAC System Time Nanoseconds Update register.Go
B18hMAC_Timestamp_AddendTimestamp Addend register.
This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register).
The content of this register is added to a 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time is updated whenever the accumulator overflows.		Go
B1ChMAC_System_Time_Higher_Word_SecondsSystem Time - Higher Word Seconds register.Go
B20hMAC_Timestamp_StatusTimestamp Status register.
All bits except Bits[27:25] gets cleared when the application reads this register.		Go
B30hMAC_Tx_Timestamp_Status_NanosecondsThis register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled.
The MAC_Tx_Timestamp_Status_Nanoseconds register, along with MAC_Tx_Timestamp_Status_Seconds, gives the 64-bit timestamp captured for the PTP packet successfully transmitted by the MAC.
This value is considered to be read by the application when the last byte of MAC_Tx_Timestamp_Status_Nanoseconds is read.
In the little-endian mode, this means when bits[31:24] are read; in big-endian mode, bits[7:0] are read.
If the application does not read these registers and timestamp of another packet is captured, then either the current timestamp is lost (overwritten) or the new timestamp is lost (dropped), depending on the setting of the TXTSSTSM bit of the MAC_Timestamp_Control register.
The status bit TXTSC bit [15] in MAC_Timestamp_Status register is set whenever the MAC transmitter captures the timestamp.		Go
B34hMAC_Tx_Timestamp_Status_SecondsThe register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted.Go
B40hMAC_Auxiliary_ControlThe Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot.Go
B48hMAC_Auxiliary_Timestamp_NanosecondsThe Auxiliary Timestamp Nanoseconds register, along with MAC_Auxiliary_Timestamp_Seconds, gives the 64-bit timestamp stored as auxiliary snapshot.
These two registers form the read port of a 64-bit wide FIFO with a depth of 4, 8, or 16 as selected while configuring the core.
You can store multiple snapshots in this FIFO.
Bits[29:25] in MAC_Timestamp_Status indicate the fill-level of the FIFO.
The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read.
In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read.		Go
B4ChMAC_Auxiliary_Timestamp_SecondsThe Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register.Go
B50hMAC_Timestamp_Ingress_Asym_CorrThe MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages.Go
B54hMAC_Timestamp_Egress_Asym_CorrThe MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages.Go
B58hMAC_Timestamp_Ingress_Corr_NanosecondThis register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path.Go
B5ChMAC_Timestamp_Egress_Corr_NanosecondThis register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path.Go
B60hMAC_Timestamp_Ingress_Corr_SubnanosecThis register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value, for ingress direction.Go
B64hMAC_Timestamp_Egress_Corr_SubnanosecThis register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value, for egress direction.Go
B70hMAC_PPS_ControlPPS Control register.
Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected.
Bits[22:16] are valid only when three or more Flexible PPS outputs are selected.
Bits[14:8] are valid only when two or more Flexible PPS outputs are selected.
Bits[6:4] are valid only when Flexible PPS feature is selected.		Go
B80hMAC_PPS0_Target_Time_SecondsThe PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers.Go
B84hMAC_PPS0_Target_Time_NanosecondsPPS0 Target Time Nanoseconds register.Go
B88hMAC_PPS0_IntervalThe PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).Go
B8ChMAC_PPS0_WidthThe PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0]).Go
B90hMAC_PPS1_Target_Time_SecondsThe PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers.Go
B94hMAC_PPS1_Target_Time_NanosecondsPPS0 Target Time Nanoseconds register.Go
B98hMAC_PPS1_IntervalThe PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).Go
B9ChMAC_PPS1_WidthThe PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0]).Go
BC0hMAC_PTO_ControlThis register controls the PTP Offload Engine operation.
This register is available only when the Enable PTP Timestamp Offload feature is selected.		Go
BC4hMAC_Source_Port_Identity0This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node.
This register is available only when the Enable PTP Timestamp Offload feature is selected.		Go
BC8hMAC_Source_Port_Identity1This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node.
This register is available only when the Enable PTP Timestamp Offload feature is selected.		Go
BCChMAC_Source_Port_Identity2This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node.
This register is available only when the Enable PTP Timestamp Offload feature is selected.		Go
BD0hMAC_Log_Message_Interval
This register contains the periodic intervals for automatic PTP packet generation.
This register is available only when the Enable PTP Timestamp Offload feature is selected.
Go
C00hMTL_Operation_ModeThe Operation Mode register establishes the Transmit and Receive operating modes and commands.Go
C08hMTL_DBG_CTLThe FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access.Go
C0ChMTL_DBG_STSThe FIFO Debug Status register contains the status of FIFO debug access.Go
C10hMTL_FIFO_Debug_DataThe FIFO Debug Data register contains the data to be written to or read from the FIFOs.Go
C20hMTL_Interrupt_StatusThe software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.Go
C30hMTL_RxQ_DMA_Map0The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations.Go
D00hMTL_TxQ0_Operation_ModeThe Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands.Go
D04hMTL_TxQ0_UnderflowThe Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flushGo
D08hMTL_TxQ0_DebugThe Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue.Go
D14hMTL_TxQ0_ETS_StatusThe Queue 0 ETS Status register provides the average traffic transmitted in Queue 0.Go
D18hMTL_TxQ0_Quantum_WeightThe Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR), weights for the Weighted Round Robin (WRR), and Weighted Fair Queuing (WFQ) for Queue 0.Go
D2ChMTL_Q0_Interrupt_Control_StatusThis register contains the interrupt enable and status bits for the queue 0 interrupts.Go
D30hMTL_RxQ0_Operation_ModeThe Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command.
The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release		Go
D34hMTL_RxQ0_Missed_Packet_Overflow_CntThe Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow.Go
D38hMTL_RxQ0_DebugThe Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue.Go
D3ChMTL_RxQ0_ControlThe Queue Receive Control register controls the receive arbitration and passing of received packets to the application.Go
D40hMTL_TxQ1_Operation_ModeThe Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands.Go
D44hMTL_TxQ1_UnderflowThe Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flushGo
D48hMTL_TxQ1_DebugThe Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue.Go
D54hMTL_TxQ1_ETS_StatusThe Queue 1 ETS Status register provides the average traffic transmitted in Queue 1.Go
D58hMTL_TxQ1_Quantum_WeightThe Queue 1 idleSlopeCredit, Quantum or Weights register provides the average traffic transmitted in Queue 1.Go
D6ChMTL_Q1_Interrupt_Control_StatusThis register contains the interrupt enable and status bits for the queue 1 interrupts.Go
D70hMTL_RxQ1_Operation_ModeThe Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command.
The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release		Go
D74hMTL_RxQ1_Missed_Packet_Overflow_CntThe Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow.Go
D78hMTL_RxQ1_DebugThe Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue.Go
D7ChMTL_RxQ1_ControlThe Queue Receive Control register controls the receive arbitration and passing of received packets to the application.Go
1000hDMA_ModeThe Bus Mode register establishes the bus operating modes for the DMA.Go
1004hDMA_SysBus_ModeThe System Bus mode register controls the behavior of the AHB or AXI master.
It mainly controls burst splitting and number of outstanding requests.		Go
1008hDMA_Interrupt_StatusThe application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels, MTL queues, and the MAC.Go
100ChDMA_Debug_Status0The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose.Go
1100hDMA_CH0_ControlThe DMA Channeli Control register specifies the MSS value for segmentation, length to skip between two descriptors, and also the features such as header splitting and 8xPBL mode.Go
1104hDMA_CH0_Tx_ControlThe DMA Channeli Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights.Go
1108hDMA_CH0_Rx_ControlThe DMA Channeli Receive Control register controls the Rx features such as PBL, buffer size, and extended status.Go
1114hDMA_CH0_TxDesc_List_AddressThe Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list.
The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus).
The DMA internally converts it to bus width aligned address by making the corresponding LSB to low.
You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in DMA_CH0_Tx_Control register.
When stopped, this register can be written with a new descriptor list address.
When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address.
If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier.		Go
111ChDMA_CH0_RxDesc_List_AddressThe Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list.
This register points to the start of the Receive Descriptor List.
The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus).
The DMA internally converts it to bus width aligned address by making the corresponding LS bits low.
Writing to this register is permitted only when reception is stopped.
When stopped, this register must be written to before the receive Start command is given.
You can write to this register only when Rx DMA has stopped, that is, SR bit is set to zero in DMA_CH0_Rx_Control register.
When stopped, this register can be written with a new descriptor list address.
When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.		Go
1120hDMA_CH0_TxDesc_Tail_PointerThe Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor.Go
1128hDMA_CH0_RxDesc_Tail_PointerThe Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor.Go
112ChDMA_CH0_TxDesc_Ring_LengthThe Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring.Go
1130hDMA_CH0_RxDesc_Ring_LengthThe Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring.Go
1134hDMA_CH0_Interrupt_EnableThe Channeli Interrupt Enable register enables the interrupts reported by the Status register.Go
1138hDMA_CH0_Rx_Interrupt_Watchdog_TimerThe Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA.
When this register is written with a non-zero value, it enables the watchdog timer for the RI bit of the DMA_CHi_Status register.		Go
1144hDMA_CH0_Current_App_TxDescThe Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA.Go
114ChDMA_CH0_Current_App_RxDescThe Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA.Go
1154hDMA_CH0_Current_App_TxBufferThe Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA.Go
115ChDMA_CH0_Current_App_RxBufferThe Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA.Go
1160hDMA_CH0_StatusThe software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA.
Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx DMA Channels and Tx DMA Channels.		Go
1164hDMA_CH0_Miss_Frame_CntThis register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH${i}_Rx_Control register.Go
116ChDMA_CH0_RX_ERI_CntGo
1180hDMA_CH1_ControlThe DMA Channeli Control register specifies the MSS value for segmentation, length to skip between two descriptors, and also the features such as header splitting and 8xPBL mode.Go
1184hDMA_CH1_Tx_ControlThe DMA Channeli Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights.Go
1188hDMA_CH1_Rx_ControlThe DMA Channeli Receive Control register controls the Rx features such as PBL, buffer size, and extended status.Go
1194hDMA_CH1_TxDesc_List_AddressThe Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list.
The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus).
The DMA internally converts it to bus width aligned address by making the corresponding LSB to low.
You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in DMA_CH0_Tx_Control register.
When stopped, this register can be written with a new descriptor list address.
When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address.
If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier.		Go
119ChDMA_CH1_RxDesc_List_AddressThe Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list.
This register points to the start of the Receive Descriptor List.
The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus).
The DMA internally converts it to bus width aligned address by making the corresponding LS bits low.
Writing to this register is permitted only when reception is stopped.
When stopped, this register must be written to before the receive Start command is given.
You can write to this register only when Rx DMA has stopped, that is, SR bit is set to zero in DMA_CH0_Rx_Control register.
When stopped, this register can be written with a new descriptor list address.
When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.		Go
11A0hDMA_CH1_TxDesc_Tail_PointerThe Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor.Go
11A8hDMA_CH1_RxDesc_Tail_PointerThe Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor.Go
11AChDMA_CH1_TxDesc_Ring_LengthThe Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring.Go
11B0hDMA_CH1_RxDesc_Ring_LengthThe Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring.Go
11B4hDMA_CH1_Interrupt_EnableThe Channeli Interrupt Enable register enables the interrupts reported by the Status register.Go
11B8hDMA_CH1_Rx_Interrupt_Watchdog_TimerThe Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA.
When this register is written with a non-zero value, it enables the watchdog timer for the RI bit of the DMA_CHi_Status register.		Go
11C4hDMA_CH1_Current_App_TxDescThe Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA.Go
11CChDMA_CH1_Current_App_RxDescThe Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA.Go
11D4hDMA_CH1_Current_App_TxBufferThe Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA.Go
11DChDMA_CH1_Current_App_RxBufferThe Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA.Go
11E0hDMA_CH1_StatusThe software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA.
Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx DMA Channels and Tx DMA Channels.		Go
11E4hDMA_CH1_Miss_Frame_CntThis register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH${i}_Rx_Control register.Go
11EChDMA_CH1_RX_ERI_CntGo

Complex bit access types are encoded to fit into small table cells. Table 43-93 shows the codes that are used for access types in this section.

Table 43-93 EMAC_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

43.7.3.1 MAC_Configuration Register (Offset = 0h) [Reset = 8000h]

MAC_Configuration is shown in Figure 43-40 and described in Table 43-94.

Return to the Summary Table.

The MAC Configuration Register establishes the operating mode of the MAC.

Figure 43-40 MAC_Configuration Register
3130292827262524
ARPENSARCIPCIPG
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPSLCES2KPCSTACSWDRESERVEDJDJE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
15141312111098
PSFESDMLMECRSFDDODCRSDR
R-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDBLDCPRELENTERE
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-94 MAC_Configuration Register Field Descriptions
BitFieldTypeResetDescription
31ARPENR/W0hARP Offload Enable
When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It forwards the ARP packet to the application and also indicate the events in the RxStatus.
When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the RxStatus.
This bit is available only when the Enable IPv4 ARP Offload is selected.
0h = ARP Offload is disabled : 0x0
1h = ARP Offload is enabled : 0x1
30-28SARCR/W0hSource Address Insertion or Replacement Control
This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[29:28]:
2'b0x:
- The SA Insertion control is to be programmed in Bits[25:23] of TDES3 in first Transmit Descriptor of the packet.
2'b10:
- If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (MAC registers 192 and 193) in the SA field of all transmitted packets.
- If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected while configuring the core, the MAC inserts the content of the MAC Address 1 registers (MAC registers 194 and 195) in the SA field of all transmitted packets.
2'b11:
- If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (MAC registers 192 and 193) in the SA field of all transmitted packets.
- If Bit 30 is set to 1 and the MAC Address Register 1 is enabled, the MAC replaces the content of the MAC Address 1 registers (MAC registers 194 and 195) in the SA field of all transmitted packets.
Note:
- Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value.
0h = mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation : 0x0
2h = Contents of MAC Addr-0 inserted in SA field : 0x2
3h = Contents of MAC Addr-0 replaces SA field : 0x3
6h = Contents of MAC Addr-1 inserted in SA field : 0x6
7h = Contents of MAC Addr-1 replaces SA field : 0x7
27IPCR/W0hChecksum Offload
When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled.
The Layer 3 and Layer 4 Packet Filter and Enable Split Header features automatically selects the IPC Full Checksum Offload Engine on the Receive side. When any of these features are enabled, you must set the IPC bit.
0h = IP header/payload checksum checking is disabled : 0x0
1h = IP header/payload checksum checking is enabled : 0x1
26-24IPGR/W0hInter-Packet Gap
These bits control the minimum IPG between packets during transmission.
This range of minimum IPG is valid in full-duplex mode.
In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered.
When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IPG.
The above function (IPG less than 96 bit times) is valid only when EIPGEN bit in MAC_Ext_Configuration register is reset. When EIPGEN is set, then the minimum IPG (greater than 96 bit times) is controlled as per the description given in EIPG field in MAC_Ext_Configuration register.
0h = 96 bit times IPG : 0x0
1h = 88 bit times IPG : 0x1
2h = 80 bit times IPG : 0x2
3h = 72 bit times IPG : 0x3
4h = 64 bit times IPG : 0x4
5h = 56 bit times IPG : 0x5
6h = 48 bit times IPG : 0x6
7h = 40 bit times IPG : 0x7
23GPSLCER/W0hGiant Packet Size Limit Control Enable
When this bit is set, the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet. This field must be programmed to more than 1,518 bytes. Otherwise, the MAC considers 1,518 bytes as giant packet limit.
When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1,518 bytes (1522 bytes for tagged packet).
The watchdog timeout limit, Jumbo Packet Enable and 2K Packet Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9,018 bytes (9,022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2,000 bytes with 2K Packet Enabled. The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status.
0h = Giant Packet Size Limit Control is disabled : 0x0
1h = Giant Packet Size Limit Control is enabled : 0x1
22S2KPR/W0hIEEE 802.3as Support for 2K Packets
When this bit is set, the MAC considers all packets with up to 2,000 bytes length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2K bytes as Giant packets.
When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1,518 bytes (1,522 bytes for tagged) as giant packets. For more information about how the setting of this bit and the JE bit impact the Giant packet status, see the Table, Gaint Packet Status based on S2KP and JE Bits.
Note: When the JE bit is set, setting this bit has no effect on the giant packet status.
0h = Support upto 2K packet is disabled : 0x0
1h = Support upto 2K packet is Enabled : 0x1
21CSTR/W0hCRC stripping for Type packets
When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application.
Note: For information about how the settings of the ACS bit and this bit impact the packet length, see the Table, Packet Length based on the CST and ACS Bits.
0h = CRC stripping for Type packets is disabled : 0x0
1h = CRC stripping for Type packets is enabled : 0x1
20ACSR/W0hAutomatic Pad or CRC Stripping
When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. All received packets with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field.
When this bit is reset, the MAC passes all incoming packets to the application, without any modification.
Note: For information about how the settings of CST bit and this bit impact the packet length, see the Table, Packet Length based on the CST and ACS Bit .
0h = Automatic Pad or CRC Stripping is disabled : 0x0
1h = Automatic Pad or CRC Stripping is enabled : 0x1
19WDR/W0hWatchdog Disable
When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes.
When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes.
0h = Watchdog is enabled : 0x0
1h = Watchdog is disabled : 0x1
18RESERVEDR0hReserved.
17JDR/W0hJabber Disable
When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes.
When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet.
0h = Jabber is enabled : 0x0
1h = Jabber is disabled : 0x1
16JER/W0hJumbo Packet Enable
When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status.
0h = Jumbo packet is disabled : 0x0
1h = Jumbo packet is enabled : 0x1
15PSR1hPort Select
This bit selects the Ethernet line speed.
This bit, along with Bit 14, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only (RO) with appropriate value. In default 10/100/1000 Mbps configurations, this bit is read-write (R/W). The mac_speed_o[1] signal reflects the value of this bit.
0h = For 1000 or 2500 Mbps operations : 0x0
1h = For 10 or 100 Mbps operations : 0x1
14FESR/W0hSpeed
This bit selects the speed mode.
The mac_speed_o[0] signal reflects the value of this bit.
0h = 10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 : 0x0
1h = 100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 : 0x1
13DMR/W0hDuplex Mode
When this bit is set, the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configurations.
0h = Half-duplex mode : 0x0
1h = Full-duplex mode : 0x1
12LMR/W0hLoopback Mode
When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Rx clock input (clk_rx_i) is required for the loopback to work properly. This is because the Tx clock is not internally looped back.
0h = Loopback is disabled : 0x0
1h = Loopback is enabled : 0x1
11ECRSFDR/W0hEnable Carrier Sense Before Transmission in Full-Duplex Mode
When this bit is set, the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low.
When this bit is reset, the MAC transmitter ignores the status of the CRS signal.
0h = ECRSFD is disabled : 0x0
1h = ECRSFD is enabled : 0x1
10DOR/W0hDisable Receive Own
When this bit is set, the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets given by the PHY.
This bit is not applicable in the full-duplex mode.
0h = Enable Receive Own : 0x0
1h = Disable Receive Own : 0x1
9DCRSR/W0hDisable Carrier Sense During Transmission
When this bit is set, the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission.
When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission.
0h = Enable Carrier Sense During Transmission : 0x0
1h = Disable Carrier Sense During Transmission : 0x1
8DRR/W0hDisable Retry
When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status.
When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the half-duplex mode.
0h = Enable Retry : 0x0
1h = Disable Retry : 0x1
7RESERVEDR0hReserved.
6-5BLR/W0hBack-Off Limit
The back-off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000/2500 Mbps
512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision.
n = retransmission attempt.
The random integer r takes the value in the range 0 <= r < 2k
This bit is applicable only in the half-duplex mode.
0h = k = min(n,10) : 0x0
1h = k = min(n,8) : 0x1
2h = k = min(n,4) : 0x2
3h = k = min(n,1) : 0x3
4DCR/W0hDeferral Check
When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288 bit times in 10 or 100 Mbps mode.
If the MAC is configured for 1000/2500 Mbps operation, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII.
The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted.
When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive.
This bit is applicable only in the half-duplex mode.
0h = Deferral check function is disabled : 0x0
1h = Deferral check function is enabled : 0x1
3-2PRELENR/W0hPreamble Length for Transmit packets
These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.
0h = 7 bytes of preamble : 0x0
1h = 5 bytes of preamble : 0x1
2h = 3 bytes of preamble : 0x2
3h = Reserved : 0x3
1TER/W0hTransmitter Enable
When this bit is set, the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets.
0h = Transmitter is disabled : 0x0
1h = Transmitter is enabled : 0x1
0RER/W0hReceiver Enable
When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the GMII or MII interface.
0h = Receiver is disabled : 0x0
1h = Receiver is enabled : 0x1

43.7.3.2 MAC_Ext_Configuration Register (Offset = 4h) [Reset = 0h]

MAC_Ext_Configuration is shown in Figure 43-41 and described in Table 43-95.

Return to the Summary Table.

The MAC Extended Configuration Register establishes the operating mode of the MAC.

Figure 43-41 MAC_Ext_Configuration Register
3130292827262524
RESERVEDEIPGEIPGEN
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDHDSMSRESERVEDUSPSPENDCRCC
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPSL
R-0hR/W-0h
76543210
GPSL
R/W-0h
Table 43-95 MAC_Ext_Configuration Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved.
29-25EIPGR/W0hExtended Inter-Packet Gap
The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits), along with IPG field in MAC_Configuration register, gives the minimum IPG greater than 96 bit times in steps of 8 bit times:
{EIPG, IPG}
8'h00 - 104 bit times
8'h01 - 112 bit times
8'h02 - 120 bit times
-----------------------
8'hFF - 2144 bit times
24EIPGENR/W0hExtended Inter-Packet Gap Enable
When this bit is set, the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times.
When this bit is reset, the MAC ignores EIPG field and interprets IPG field in MAC_Configuration register as minimum IPG less than or equal to 96 bit times in steps of 8 bit times.
Note: The extended Inter-Packet Gap feature must be enabled when operating in Full-Duplex mode only. There may be undesirable effects on back-pressure function and frame transmission if it is enabled in Half-Duplex mode.
0h = Extended Inter-Packet Gap is disabled : 0x0
1h = Extended Inter-Packet Gap is enabled : 0x1
23RESERVEDR0hReserved.
22-20HDSMSR/W0hMaximum Size for Splitting the Header Data
These bits indicate the maximum header size allowed for splitting the header data in the received packet.

0h = Maximum Size for Splitting the Header Data is 64 bytes : 0x0
1h = Maximum Size for Splitting the Header Data is 128 bytes : 0x1
2h = Maximum Size for Splitting the Header Data is 256 bytes : 0x2
3h = Maximum Size for Splitting the Header Data is 512 bytes : 0x3
4h = Maximum Size for Splitting the Header Data is 1024 bytes : 0x4
5h = Reserved : 0x5
19RESERVEDR0hReserved.
18USPR/W0hUnicast Slow Protocol Packet Detect
When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers. The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-00-00-02).
When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2008, Section 5.
0h = Unicast Slow Protocol Packet Detection is disabled : 0x0
1h = Unicast Slow Protocol Packet Detection is enabled : 0x1
17SPENR/W0hSlow Protocol Detection Enable
When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types.
When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets.
0h = Slow Protocol Detection is disabled : 0x0
1h = Slow Protocol Detection is enabled : 0x1
16DCRCCR/W0hDisable CRC Checking for Received Packets
When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets.
0h = CRC Checking is enabled : 0x0
1h = CRC Checking is disabled : 0x1
15-14RESERVEDR0hReserved.
13-0GPSLR/W0hGiant Packet Size Limit
If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1,518 bytes. Any other programmed value is considered as 1,518 bytes.
For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. When the Enable Double VLAN Processing option is selected, the MAC adds 8 bytes to the programmed value for double VLAN tagged packets. The value in this field is applicable when the GPSLCE bit is set in MAC_Configuration register.

43.7.3.3 MAC_Packet_Filter Register (Offset = 8h) [Reset = 0h]

MAC_Packet_Filter is shown in Figure 43-42 and described in Table 43-96.

Return to the Summary Table.

The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets.

Figure 43-42 MAC_Packet_Filter Register
3130292827262524
RARESERVED
R/W-0hR-0h
2322212019181716
RESERVEDDNTUIPFERESERVEDVTFE
R-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDHPFSAFSAIF
R-0hR/W-0hR/W-0hR/W-0h
76543210
PCFDBFPMDAIFHMCHUCPR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-96 MAC_Packet_Filter Register Field Descriptions
BitFieldTypeResetDescription
31RAR/W0hReceive All
When this bit is set, the MAC Receiver module passes all received packets to the application, irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bit in the Rx Status Word.
When this bit is reset, the Receiver module passes only those packets to the application that pass the SA or DA address filter.
0h = Receive All is disabled : 0x0
1h = Receive All is enabled : 0x1
30-22RESERVEDR0hReserved.
21DNTUR/W0hDrop Non-TCP/UDP over IP Packets
When this bit is set, the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset, the MAC forwards all non-TCP or UDP over IP packets.
0h = Forward Non-TCP/UDP over IP Packets : 0x0
1h = Drop Non-TCP/UDP over IP Packets : 0x1
20IPFER/W0hLayer 3 and Layer 4 Filter Enable
When this bit is set, the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect.
When this bit is reset, the MAC forwards all packets irrespective of the match status of the Layer 3 and Layer 4 fields.
0h = Layer 3 and Layer 4 Filters are disabled : 0x0
1h = Layer 3 and Layer 4 Filters are enabled : 0x1
19-17RESERVEDR0hReserved.
16VTFER/W0hVLAN Tag Filter Enable
When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset, the MAC forwards all packets irrespective of the match status of the VLAN Tag.
0h = VLAN Tag Filter is disabled : 0x0
1h = VLAN Tag Filter is enabled : 0x1
15-11RESERVEDR0hReserved.
10HPFR/W0hHash or Perfect Filter
When this bit is set, the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit.
When this bit is reset and the HUC or HMC bit is set, the packet is passed only if it matches the Hash filter.
0h = Hash or Perfect Filter is disabled : 0x0
1h = Hash or Perfect Filter is enabled : 0x1
9SAFR/W0hSource Address Filter Enable
When this bit is set, the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the packet.
When this bit is reset, the MAC forwards the received packet to the application with updated SAF bit of the Rx Status depending on the SA address comparison.
Note: According to the IEEE specification, Bit 47 of the SA is reserved. However, in DWC_ether_qos, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA.
0h = SA Filtering is disabled : 0x0
1h = SA Filtering is enabled : 0x1
8SAIFR/W0hSA Inverse Filtering
When this bit is set, the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers, it is marked as failing the SA Address filter.
When this bit is reset, if the SA of a packet does not match the values programmed in the SA registers, it is marked as failing the SA Address filter.
0h = SA Inverse Filtering is disabled : 0x0
1h = SA Inverse Filtering is enabled : 0x1
7-6PCFR/W0hPass Control Packets
These bits control the forwarding of all control packets (including unicast and multicast Pause packets).
0h = MAC filters all control packets from reaching the application : 0x0
1h = MAC forwards all control packets except Pause packets to the application even if they fail the Address filter : 0x1
2h = MAC forwards all control packets to the application even if they fail the Address filter : 0x2
3h = MAC forwards the control packets that pass the Address filter : 0x3
5DBFR/W0hDisable Broadcast Packets
When this bit is set, the AFM module blocks all incoming broadcast packets. In addition, it overrides all other filter settings.
When this bit is reset, the AFM module passes all received broadcast packets.
0h = Enable Broadcast Packets : 0x0
1h = Disable Broadcast Packets : 0x1
4PMR/W0hPass All Multicast
When this bit is set, it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset, filtering of multicast packet depends on HMC bit.
0h = Pass All Multicast is disabled : 0x0
1h = Pass All Multicast is enabled : 0x1
3DAIFR/W0hDA Inverse Filtering
When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset, normal filtering of packets is performed.
0h = DA Inverse Filtering is disabled : 0x0
1h = DA Inverse Filtering is enabled : 0x1
2HMCR/W0hHash Multicast
When this bit is set, the MAC performs the destination address filtering of received multicast packets according to the hash table.
When this bit is reset, the MAC performs the perfect destination address filtering for multicast packets, that is, it compares the DA field with the values programmed in DA registers.
0h = Hash Multicast is disabled : 0x0
1h = Hash Multicast is enabled : 0x1
1HUCR/W0hHash Unicast
When this bit is set, the MAC performs the destination address filtering of unicast packets according to the hash table.
When this bit is reset, the MAC performs a perfect destination address filtering for unicast packets, that is, it compares the DA field with the values programmed in DA registers.
0h = Hash Unicast is disabled : 0x0
1h = Hash Unicast is enabled : 0x1
0PRR/W0hPromiscuous Mode
When this bit is set, the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set.
0h = Promiscuous Mode is disabled : 0x0
1h = Promiscuous Mode is enabled : 0x1

43.7.3.4 MAC_Watchdog_Timeout Register (Offset = Ch) [Reset = 0h]

MAC_Watchdog_Timeout is shown in Figure 43-43 and described in Table 43-97.

Return to the Summary Table.

The Watchdog Timeout register controls the watchdog timeout for received packets.

Figure 43-43 MAC_Watchdog_Timeout Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPWERESERVEDWTO
R-0hR/W-0hR-0hR/W-0h
Table 43-97 MAC_Watchdog_Timeout Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved.
8PWER/W0hProgrammable Watchdog Enable
When this bit is set and the WD bit of the MAC_Configuration register is reset, the WTO field is used as watchdog timeout for a received packet. When this bit is cleared, the watchdog timeout for a received packet is controlled by setting of WD and JE bits in MAC_Configuration register.
0h = Programmable Watchdog is disabled : 0x0
1h = Programmable Watchdog is enabled : 0x1
7-4RESERVEDR0hReserved.
3-0WTOR/W0hWatchdog Timeout
When the PWE bit is set and the WD bit of the MAC_Configuration register is reset, this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field, such packet is terminated and declared as an error packet.
Note: When the PWE bit is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE 802.3-specified valid tagged packets are declared as error packets and then dropped.
0h = 2 KB : 0x0
1h = 3 KB : 0x1
2h = 4 KB : 0x2
3h = 5 KB : 0x3
4h = 6 KB : 0x4
5h = 7 KB : 0x5
6h = 8 KB : 0x6
7h = 9 KB : 0x7
8h = 10 KB : 0x8
9h = 11 KB : 0x9
Ah = 12 KB : 0xa
Bh = 13 KB : 0xb
Ch = 14 KB : 0xc
Dh = 15 KB : 0xd
Eh = 16383 Bytes : 0xe
Fh = Reserved : 0xf

43.7.3.5 MAC_Hash_Table_Reg0 Register (Offset = 10h) [Reset = 0h]

MAC_Hash_Table_Reg0 is shown in Figure 43-44 and described in Table 43-98.

Return to the Summary Table.

The Hash Table Register 0 contains the first 32 bits of the hash table, when the width of the hash table is 128 or 256 bits. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant.
The Hash table is used for group address filtering. For hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six (seven in 128-bit Hash or eight in 256-bit Hash) bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register. For example, a hash value of 6'b100000 (in 64-bit Hash) selects Bit 0 of the Hash Table Register 1, a value of 7b'1110000 (in 128-bit Hash) selects Bit 16 of the Hash Table Register 3 and a value of 8b'10111111 (in 256-bit Hash) selects Bit 31 of the Hash Table Register 5.
The hash value of the destination address is calculated in the following way:
- Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32).
- Perform bitwise reversal for the value obtained in Step 1.
- Take the upper 6 (or 7 or 8) bits from the value obtained in Step 2.
If the corresponding bit value of the register is 1'b1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in MAC_Packet_Filter, all multicast packets are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
If double-synchronization is enabled, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-44 MAC_Hash_Table_Reg0 Register
313029282726252423222120191817161514131211109876543210
HT31T0
R/W-0h
Table 43-98 MAC_Hash_Table_Reg0 Register Field Descriptions
BitFieldTypeResetDescription
31-0HT31T0R/W0hMAC Hash Table First 32 Bits
This field contains the first 32 Bits [31:0] of the Hash table.

43.7.3.6 MAC_Hash_Table_Reg1 Register (Offset = 14h) [Reset = 0h]

MAC_Hash_Table_Reg1 is shown in Figure 43-45 and described in Table 43-99.

Return to the Summary Table.

The Hash Table Register 1 contains the second 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant.
The Hash table is used for group address filtering. For hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six (seven in 128-bit Hash or eight in 256-bit Hash) bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register. For example, a hash value of 6'b100000 (in 64-bit Hash) selects Bit 0 of the Hash Table Register 1, a value of 7b'1110000 (in 128-bit Hash) selects Bit 16 of the Hash Table Register 3 and a value of 8b'10111111 (in 256-bit Hash) selects Bit 31 of the Hash Table Register 5.
The hash value of the destination address is calculated in the following way:
- Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32).
- Perform bitwise reversal for the value obtained in Step 1.
- Take the upper 6 (or 7 or 8) bits from the value obtained in Step 2.
If the corresponding bit value of the register is 1'b1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in MAC_Packet_Filter, all multicast packets are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
If double-synchronization is enabled, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-45 MAC_Hash_Table_Reg1 Register
313029282726252423222120191817161514131211109876543210
HT63T32
R/W-0h
Table 43-99 MAC_Hash_Table_Reg1 Register Field Descriptions
BitFieldTypeResetDescription
31-0HT63T32R/W0hMAC Hash Table Second 32 Bits
This field contains the second 32 Bits [63:32] of the Hash table.

43.7.3.7 MAC_VLAN_Tag_Ctrl Register (Offset = 50h) [Reset = 0h]

MAC_VLAN_Tag_Ctrl is shown in Figure 43-46 and described in Table 43-100.

Return to the Summary Table.

This register is the redefined format of the MAC VLAN Tag Register. It is used for indirect addressing. It contains the address offset, command type and Busy Bit for CSR access of the Per VLAN Tag registers.

Figure 43-46 MAC_VLAN_Tag_Ctrl Register
3130292827262524
EIVLRXSRESERVEDEIVLSERIVLTEDVLPVTHMEVLRXS
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDEVLSRESERVEDESVLVTIMRESERVED
R-0hR/W-0hR-0hR/W-0hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDOFSCTOB
R-0hR/W-0hR/W-0hR/W-0h
Table 43-100 MAC_VLAN_Tag_Ctrl Register Field Descriptions
BitFieldTypeResetDescription
31EIVLRXSR/W0hEnable Inner VLAN Tag in Rx Status
When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the inner VLAN Tag in Rx status.
0h = Inner VLAN Tag in Rx status is disabled : 0x0
1h = Inner VLAN Tag in Rx status is enabled : 0x1
30RESERVEDR0hReserved.
29-28EIVLSR/W0hEnable Inner VLAN Tag Stripping on Receive
This field indicates the stripping operation on inner VLAN Tag in received packet.
0h = Do not strip : 0x0
1h = Strip if VLAN filter passes : 0x1
2h = Strip if VLAN filter fails : 0x2
3h = Always strip : 0x3
27ERIVLTR/W0h
26EDVLPR/W0hEnable Double VLAN Processing
When this bit is set, the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset, the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present).
0h = Double VLAN Processing is disabled : 0x0
1h = Double VLAN Processing is enabled : 0x1
25VTHMR/W0hVLAN Tag Hash Table Match Enable
When this bit is set, the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register. A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the packet matched the VLAN hash table.
When the ETV bit is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison. When the ETV bit is reset, the CRC of the 16-bit VLAN tag is used for comparison.
When this bit is reset, the VLAN Hash Match operation is not performed.
0h = VLAN Tag Hash Table Match is disabled : 0x0
1h = VLAN Tag Hash Table Match is enabled : 0x1
24EVLRXSR/W0hEnable VLAN Tag in Rx status
When this bit is set, MAC provides the outer VLAN Tag in the Rx status. When this bit is reset, the MAC does not provide the outer VLAN Tag in Rx status.
0h = VLAN Tag in Rx status is disabled : 0x0
1h = VLAN Tag in Rx status is enabled : 0x1
23RESERVEDR0hReserved.
22-21EVLSR/W0hEnable VLAN Tag Stripping on Receive
This field indicates the stripping operation on the outer VLAN Tag in received packet.
0h = Do not strip : 0x0
1h = Strip if VLAN filter passes : 0x1
2h = Strip if VLAN filter fails : 0x2
3h = Always strip : 0x3
20-19RESERVEDR0hReserved.
18ESVLR/W0hEnable S-VLAN
When this bit is set, the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets.
0h = S-VLAN is disabled : 0x0
1h = S-VLAN is enabled : 0x1
17VTIMR/W0hVLAN Tag Inverse Match Enable
When this bit is set, this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The packets with matched VLAN Tag are marked as matched.
0h = VLAN Tag Inverse Match is disabled : 0x0
1h = VLAN Tag Inverse Match is enabled : 0x1
16-7RESERVEDR0hReserved.
6-2OFSR/W0hOffset
This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access.
The width of the field depends on the number of MAC VLAN Tag Registers enabled.
1CTR/W0hCommand Type
This bit indicates if the current register access is a read or a write.
When set, it indicate a read operation. When reset, it indicates a write operation.
0h = Write operation : 0x0
1h = Read operation : 0x1
0OBR/W0hOperation Busy
This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register. This bit is reset when the read or write command to per VLAN Tag Filter indirect access register is complete. The next indirect register access can be initiated only after this bit is reset.
During a write operation, the bit is reset only after the data has been written into the Per VLAN Tag register.
During a read operation, the data should be read from the MAC_VLAN_Tag_Data register only after this bit is reset.
0h = Operation Busy is disabled : 0x0
1h = Operation Busy is enabled : 0x1

43.7.3.8 MAC_VLAN_Tag_Data Register (Offset = 54h) [Reset = 0h]

MAC_VLAN_Tag_Data is shown in Figure 43-47 and described in Table 43-101.

Return to the Summary Table.

This register holds the read/write data for Indirect Access of the Per VLAN Tag registers. During the read access, this field contains valid read data only after the OB bit is reset.
During the write access, this field should be valid prior to setting the OB bit in the MAC_VLAN_Tag_Ctrl Register.

Figure 43-47 MAC_VLAN_Tag_Data Register
3130292827262524
RESERVEDDMACHNDMACHEN
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDERIVLTERSVLMDOVLTCETVVEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
VID
R/W-0h
76543210
VID
R/W-0h
Table 43-101 MAC_VLAN_Tag_Data Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved.
25DMACHNR/W0hDMA Channel Number
The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field.
If the Routing based on VLAN Tag Filter is not necessary, this field need not be programmed.
24DMACHENR/W0hDMA Channel Number Enable
This bit is the Enable for the DMA Channel Number value programmed in the field DMACH.
When this bit is reset, the Routing does not occur based on VLAN Filter result. The frame is routed based on DA Based DMA Channel Routing.
0h = DMA Channel Number is disabled : 0x0
1h = DMA Channel Number is enabled : 0x1
23-21RESERVEDR0hReserved.
20ERIVLTR/W0hEnable Inner VLAN Tag Comparison
This bit is valid only when VLAN Tag Enable of the Filter is set.
When this bit and the EDVLP field are set, the MAC receiver enables operation on the inner VLAN Tag (if present).
When this bit is reset, the MAC receiver enables operation on the outer VLAN Tag (if present).
0h = Inner VLAN tag comparision is disabled : 0x0
1h = Inner VLAN tag comparision is enabled : 0x1
19ERSVLMR/W0hEnable S-VLAN Match for received Frames
This bit is valid only when VLAN Tag Enable of the Filter is set.
When this bit is set, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets.
When this bit is reset, the MAC receiver enables filtering or matching for C-VLAN (Type = 0x8100) packets.
0h = Receive S-VLAN Match is disabled : 0x0
1h = Receive S-VLAN Match is enabled : 0x1
18DOVLTCR/W0hDisable VLAN Type Comparison
This bit is valid only when VLAN Tag Enable of the Filter is set.
When this bit is set, the MAC does not check whether the VLAN Tag specified by the Enable Inner VLAN Tag Comparison bit is of type S-VLAN or C-VLAN.
When this bit is reset, the MAC filters or matches the VLAN Tag specified by the Enable Inner VLAN Tag Comparison bit only when VLAN Tag type is similar to the one specified by the Enable S-VLAN Match for received Frames bit.
0h = VLAN type comparision is enabled : 0x0
1h = VLAN type comparision is disabled : 0x1
17ETVR/W0h12bits or 16bits VLAN comparison
This bit is valid only when VEN of the Filter is set.
When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged packet.
0h = 16 bit VLAN comparision : 0x0
1h = 12 bit VLAN comparision : 0x1
16VENR/W0hVLAN Tag Enable
This bit is used to enable or disable the VLAN Tag.
When this bit is set, the MAC compares the VLAN Tag of received packet with the VLAN Tag ID.
When this bit is reset, no comparison is performed irrespective of the programming of the other fields.
0h = VLAN Tag is disabled : 0x0
1h = VLAN Tag is enabled : 0x1
15-0VIDR/W0hVLAN Tag ID
This field holds the VLAN Tag value which is used by the MAC for perfect comparison. It is valid when VLAN Tag Enable is set.

43.7.3.9 MAC_VLAN_Hash_Table Register (Offset = 58h) [Reset = 0h]

MAC_VLAN_Hash_Table is shown in Figure 43-48 and described in Table 43-102.

Return to the Summary Table.

When VTHM bit of the MAC_VLAN_Tag register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of MAC_VLAN_Tag Register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash table.
The hash value of the destination address is calculated in the following way:
- Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3).
- Perform bitwise reversal for the value obtained in step 1.
- Take the upper four bits from the value obtained in step 2.
If the VLAN hash Table register is configured to be double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written.
- If double-synchronization is enabled, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-48 MAC_VLAN_Hash_Table Register
313029282726252423222120191817161514131211109876543210
RESERVEDVLHT
R-0hR/W-0h
Table 43-102 MAC_VLAN_Hash_Table Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-0VLHTR/W0hVLAN Hash Table
This field contains the 16-bit VLAN Hash Table.

43.7.3.10 MAC_VLAN_Incl Register (Offset = 60h) [Reset = 0h]

MAC_VLAN_Incl is shown in Figure 43-49 and described in Table 43-103.

Return to the Summary Table.

The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls.

Figure 43-49 MAC_VLAN_Incl Register
3130292827262524
BUSYRDWRRESERVEDADDR
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDCBTIVLTICSVLVLPVLC
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
VLT
R/W-0h
76543210
VLT
R/W-0h
Table 43-103 MAC_VLAN_Incl Register Field Descriptions
BitFieldTypeResetDescription
31BUSYR0hBusy
This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register.
For write operation write to a register is complete when this bit is reset. For read operation the read data is valid when the bit is reset.
The application must make sure that this bit is reset before attempting subsequent access to this register.
0h = Busy status not detected : 0x0
1h = Busy status detected : 0x1
30RDWRR/W0hRead write control
This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register.
When set indicates write operation and when reset indicates read operation.
This does not have any effect when CBTI is reset.
0h = Read operation of indirect access : 0x0
1h = Write operation of indirect access : 0x1
29-25RESERVEDR0hReserved.
24ADDRR/W0hAddress
This field selects one of the queue/channel specific VLAN Inclusion register for read/write access.
This does not have any effect when CBTI is reset.
23-22RESERVEDR0hReserved.
21CBTIR/W0hChannel based tag insertion
When this bit is set, outer VLAN tag is inserted for every packets transmitted by the MAC. The tag value is taken from the queue/channel specific VLAN tag register. The VLTI, VLP, VLC, and VLT fields of this register are ignored when this bit is set.
When this bit is set, a write operation to byte 3 of this register initiates the read/write access to the indirect register.
When reset, outer VLAN operation is based on the setting of VLTI, VLP, VLC and VLT fields of this register.
0h = Channel based tag insertion is disabled : 0x0
1h = Channel based tag insertion is enabled : 0x1
20VLTIR/W0hVLAN Tag Input
When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from:


- The Tx descriptor
0h = VLAN Tag Input is disabled : 0x0
1h = VLAN Tag Input is enabled : 0x1
19CSVLR/W0hC-VLAN or S-VLAN
When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets.
0h = C-VLAN type (0x8100) is inserted or replaced : 0x0
1h = S-VLAN type (0x88A8) is inserted or replaced : 0x1
18VLPR/W0hVLAN Priority Control
When this bit is set, the control bits[17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used and bits[17:16] are ignored.
0h = VLAN Priority Control is disabled : 0x0
1h = VLAN Priority Control is enabled : 0x1
17-16VLCR/W0hVLAN Tag Control in Transmit Packets
- 2'b00: No VLAN tag deletion, insertion, or replacement
- 2'b01: VLAN tag deletion
The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags.
- 2'b10: VLAN tag insertion
The MAC inserts VLT in bytes 15 and 16 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 13 and 14. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag.
- 2'b11: VLAN tag replacement
The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted packets (Bytes 13 and 14 are 0x8100 or 0x88a8).
Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value.
0h = No VLAN tag deletion, insertion, or replacement : 0x0
1h = VLAN tag deletion : 0x1
2h = VLAN tag insertion : 0x2
3h = VLAN tag replacement : 0x3
15-0VLTR/W0hVLAN Tag for Transmit Packets
This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase.
Bits[15:13] are the User Priority field, Bit 12 is the CFI/DEI field, and Bits[11:0] are the VID field in the VLAN tag.
The following list describes the bits of this field:
- Bits[15:13]: User Priority
- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
- Bits[11:0]: VLAN Identifier (VID) field of VLAN tag

43.7.3.11 MAC_Inner_VLAN_Incl Register (Offset = 64h) [Reset = 0h]

MAC_Inner_VLAN_Incl is shown in Figure 43-50 and described in Table 43-104.

Return to the Summary Table.

The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls.

Figure 43-50 MAC_Inner_VLAN_Incl Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDVLTICSVLVLPVLC
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
VLT
R/W-0h
76543210
VLT
R/W-0h
Table 43-104 MAC_Inner_VLAN_Incl Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved.
20VLTIR/W0hVLAN Tag Input
When this bit is set, it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from:


- The Tx descriptor
0h = VLAN Tag Input is disabled : 0x0
1h = VLAN Tag Input is enabled : 0x1
19CSVLR/W0hC-VLAN or S-VLAN
When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted packets.
0h = C-VLAN type (0x8100) is inserted : 0x0
1h = S-VLAN type (0x88A8) is inserted : 0x1
18VLPR/W0hVLAN Priority Control
When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used and the VLC field is ignored.
0h = VLAN Priority Control is disabled : 0x0
1h = VLAN Priority Control is enabled : 0x1
17-16VLCR/W0hVLAN Tag Control in Transmit Packets
- 2'b00: No VLAN tag deletion, insertion, or replacement
- 2'b01: VLAN tag deletion
The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags.
- 2'b10: VLAN tag insertion
The MAC inserts VLT in bytes 19 and 20 of the packet after inserting the Type value (0x8100 or 0x88a8) in bytes 17 and 18. This operation is performed on all transmitted packets, irrespective of whether they already have a VLAN tag.
- 2'b11: VLAN tag replacement
The MAC replaces VLT in bytes 19 and 20 of all VLAN-type transmitted packets (Bytes 17 and 18 are 0x8100 or 0x88a8).
Note: Changes to this field take effect only on the start of a packet. If you write this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value.
0h = No VLAN tag deletion, insertion, or replacement : 0x0
1h = VLAN tag deletion : 0x1
2h = VLAN tag insertion : 0x2
3h = VLAN tag replacement : 0x3
15-0VLTR/W0hVLAN Tag for Transmit Packets
This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase.
Bits[15:13] are the User Priority field, Bit 12 is the CFI/DEI field, and Bits[11:0] are the VID field in the VLAN tag.
The following list describes the bits of this field:
- Bits[15:13]: User Priority
- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
- Bits[11:0]: VLAN Identifier (VID) field of VLAN tag

43.7.3.12 MAC_Q0_Tx_Flow_Ctrl Register (Offset = 70h) [Reset = 0h]

MAC_Q0_Tx_Flow_Ctrl is shown in Figure 43-51 and described in Table 43-105.

Return to the Summary Table.

The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register.
When the PFCE bit in the MAC_Rx_Flow_Ctrl register is enabled, this register controls the generation of Priority Flow Control (PFC) frames with priorities mapped according to PSRQ0 in the MAC_RxQ_Ctrl2 register.

Figure 43-51 MAC_Q0_Tx_Flow_Ctrl Register
3130292827262524
PT
R/W-0h
2322212019181716
PT
R/W-0h
15141312111098
RESERVED
R-0h
76543210
DZPQPLTRESERVEDTFEFCB_BPA
R/W-0hR/W-0hR-0hR/W-0hR/W-0h
Table 43-105 MAC_Q0_Tx_Flow_Ctrl Register Field Descriptions
BitFieldTypeResetDescription
31-16PTR/W0hPause Time
This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain, consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.
15-8RESERVEDR0hReserved.
7DZPQR/W0hDisable Zero-Quanta Pause
When this bit is set, it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or mti_flowctrl_i).
When this bit is reset, normal operation with automatic zero-quanta Pause packet generation is enabled.
0h = Zero-Quanta Pause packet generation is enabled : 0x0
1h = Zero-Quanta Pause packet generation is disabled : 0x1
6-4PLTR/W0hPause Low Threshold
This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet.
The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot times), and PLT = 001, a second Pause packet is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256-28) slot times after the first Pause packet is transmitted.
The following list provides the threshold values for different values.
The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface.
This (approximate) computation is based on the packet size (64, 1518, 2000, 9018, 16384, or 32768) + 2 Pause Packet Size + IPG in Slot Times.
0h = Pause Time minus 4 Slot Times (PT -4 slot times) : 0x0
1h = Pause Time minus 28 Slot Times (PT -28 slot times) : 0x1
2h = Pause Time minus 36 Slot Times (PT -36 slot times) : 0x2
3h = Pause Time minus 144 Slot Times (PT -144 slot times) : 0x3
4h = Pause Time minus 256 Slot Times (PT -256 slot times) : 0x4
5h = Pause Time minus 512 Slot Times (PT -512 slot times) : 0x5
6h = Reserved : 0x6
3-2RESERVEDR0hReserved.
1TFER/W0hTransmit Flow Control Enable
Full-Duplex Mode:

In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to Tx Pause packets. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause packets.
Half-Duplex Mode:
In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled.
0h = Transmit Flow Control is disabled : 0x0
1h = Transmit Flow Control is enabled : 0x1
0FCB_BPAR/W0hFlow Control Busy or Backpressure Activate
This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set.
Full-Duplex Mode:

In the full-duplex mode, this bit should be read as 1'b0 before writing to this register. To initiate a Pause packet, the application must set this bit to 1'b1. During Control packet transfer, this bit continues to be set to indicate that a packet transmission is in progress. When Pause packet transmission is complete, the MAC resets this bit to 1'b0. You should not write to this register until this bit is cleared.
Half-Duplex Mode:
When this bit is set (and TFE bit is set) in the half-duplex mode, the MAC asserts the backpressure. During backpressure, when the MAC receives a new packet, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Flow Control Busy or Backpressure Activate is disabled : 0x0
1h = Flow Control Busy or Backpressure Activate is enabled : 0x1

43.7.3.13 MAC_Rx_Flow_Ctrl Register (Offset = 90h) [Reset = 0h]

MAC_Rx_Flow_Ctrl is shown in Figure 43-52 and described in Table 43-106.

Return to the Summary Table.

The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet.

Figure 43-52 MAC_Rx_Flow_Ctrl Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVED
R-0hR-0h
76543210
RESERVEDUPRFE
R-0hR/W-0hR/W-0h
Table 43-106 MAC_Rx_Flow_Ctrl Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved.
8RESERVEDR0hReserved.
7-2RESERVEDR0hReserved.
1UPR/W0hUnicast Pause Packet Detect
A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set, the MAC can also detect Pause packets with unicast address of the station. This unicast address should be as specified in MAC_Address0_High and MAC_Address0_Low.
When this bit is reset, the MAC only detects Pause packets with unique multicast address.
Note: The MAC does not process a Pause packet if the multicast address is different from the unique multicast address. This is also applicable to the received PFC packet when the Priority Flow Control (PFC) is enabled. The unique multicast address (0x01_80_C2_00_00_01) is as specified in IEEE 802.1 Qbb-2011.
0h = Unicast Pause Packet Detect disabled : 0x0
1h = Unicast Pause Packet Detect enabled : 0x1
0RFER/W0hReceive Flow Control Enable
When this bit is set and the MAC is operating in full-duplex mode, the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in half-duplex mode, the decode function of the Pause packet is disabled.
When PFC is enabled, flow control is enabled for PFC packets. The MAC decodes the received PFC packet and disables the Transmit queue, with matching priorities, for a duration of received Pause time.
0h = Receive Flow Control is disabled : 0x0
1h = Receive Flow Control is enabled : 0x1

43.7.3.14 MAC_RxQ_Ctrl4 Register (Offset = 94h) [Reset = 0h]

MAC_RxQ_Ctrl4 is shown in Figure 43-53 and described in Table 43-107.

Return to the Summary Table.

The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues.

Figure 43-53 MAC_RxQ_Ctrl4 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDVFFQVFFQE
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDMFFQMFFQE
R-0hR/W-0hR/W-0h
76543210
RESERVEDUFFQUFFQE
R-0hR/W-0hR/W-0h
Table 43-107 MAC_RxQ_Ctrl4 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved.
17VFFQR/W0hVLAN Tag Filter Fail Packets Queue
This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to. This field is valid only when the VFFQE bit is set.
16VFFQER/W0hVLAN Tag Filter Fail Packets Queuing Enable
When this bit is set, the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter, are routed to the Rx Queue Number programmed in the VFFQ. When this bit is reset, the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed based on other routing options. This bit is valid only when the RA bit of the MAC_Packet_Filter register is set.
0h = VLAN tag Filter Fail Packets Queuing is disabled : 0x0
1h = VLAN tag Filter Fail Packets Queuing is enabled : 0x1
15-10RESERVEDR0hReserved.
9MFFQR/W0hMulticast Address Filter Fail Packets Queue.
This field holds the Rx queue number to which the Multicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the MFFQE bit is set.
8MFFQER/W0hMulticast Address Filter Fail Packets Queuing Enable.
When this bit is set, the Multicast packets which fail the Destination or Source address filter is routed to the Rx Queue Number programmed in the MFFQ.
When this bit is reset, the Multicast packets which fail the Destination or Source address filter is routed based on other routing options.
This bit is valid only when the RA bit of the MAC_Packet_Filter register is set.
0h = Multicast Address Filter Fail Packets Queuing is disabled : 0x0
1h = Multicast Address Filter Fail Packets Queuing is enabled : 0x1
7-2RESERVEDR0hReserved.
1UFFQR/W0hUnicast Address Filter Fail Packets Queue.
This field holds the Rx queue number to which the Unicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the UFFQE bit is set.
0UFFQER/W0hUnicast Address Filter Fail Packets Queuing Enable.
When this bit is set, the Unicast packets which fail the Destination or Source address filter is routed to the Rx Queue Number programmed in the UFFQ.
When this bit is reset, the Unicast packets which fail the Destination or Source address filter is routed based on other routing options.
This bit is valid only when the RA bit of the MAC_Packet_Filter register is set.
0h = Unicast Address Filter Fail Packets Queuing is disabled : 0x0
1h = Unicast Address Filter Fail Packets Queuing is enabled : 0x1

43.7.3.15 MAC_RxQ_Ctrl0 Register (Offset = A0h) [Reset = 0h]

MAC_RxQ_Ctrl0 is shown in Figure 43-54 and described in Table 43-108.

Return to the Summary Table.

The Receive Queue Control 0 register controls the queue management in the MAC Receiver.
Note: In multiple Rx queues configuration, all the queues are disabled by default. Enable the Rx queue by programming the corresponding field in this register.

Figure 43-54 MAC_RxQ_Ctrl0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDRXQ1ENRXQ0EN
R-0hR-0hR/W-0hR/W-0h
Table 43-108 MAC_RxQ_Ctrl0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-14RESERVEDR0hReserved.
13-12RESERVEDR0hReserved.
11-10RESERVEDR0hReserved.
9-8RESERVEDR0hReserved.
7-6RESERVEDR0hReserved.
5-4RESERVEDR0hReserved.
3-2RXQ1ENR/W0hReceive Queue 1 Enable
This field is similar to the RXQ0EN field.
0h = Queue not enabled : 0x0
1h = Queue enabled for AV : 0x1
2h = Queue enabled for DCB/Generic : 0x2
3h = Reserved : 0x3
1-0RXQ0ENR/W0hReceive Queue 0 Enable
This field indicates whether Rx Queue 0 is enabled for AV or DCB.
0h = Queue not enabled : 0x0
1h = Queue enabled for AV : 0x1
2h = Queue enabled for DCB/Generic : 0x2
3h = Reserved : 0x3

43.7.3.16 MAC_RxQ_Ctrl1 Register (Offset = A4h) [Reset = 0h]

MAC_RxQ_Ctrl1 is shown in Figure 43-55 and described in Table 43-109.

Return to the Summary Table.

The Receive Queue Control 1 register controls the routing of multicast, broadcast, AV, DCB, and untagged packets to the Rx queues.

Figure 43-55 MAC_RxQ_Ctrl1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTPQCRESERVEDMCBCQENRESERVEDMCBCQ
R-0hR/W-0hR-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDUPQRESERVEDRESERVED
R-0hR/W-0hR-0hR-0h
76543210
RESERVEDPTPQRESERVEDRESERVED
R-0hR/W-0hR-0hR-0h
Table 43-109 MAC_RxQ_Ctrl1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23RESERVEDR0hReserved.
22TPQCR/W0hTagged PTP over Ethernet Packets Queuing Control.
This field controls the routing of the VLAN Tagged PTPoE packets.
If DWC_EQOS_AV_ENABLE is selected in the configuration, the following programmable options are allowed.
- 2'b00: VLAN Tagged PTPoE packets are routed as generic VLAN Tagged packet (based on PSRQ for only non-AV enabled Rx Queues).
- 2'b01: VLAN Tagged PTPoE packets are routed to Rx Queue specified by PTPQ field (That Rx Queue can be enabled for AV or non-AV traffic).
- 2'b10: VLAN Tagged PTPoE packets are routed to only AV enabled Rx Queues based on PSRQ.
- 2'b11: Reserved
If DWC_EQOS_AV_ENABLE is not selected in the configuration, the following programmable options are allowed.
- 1'b0: VLAN Tagged PTPoE packets are routed as generic VLAN Tagged packet (based on PSRQ for DCB/Generic enabled Rx Queues).
- 1'b1: VLAN Tagged PTPoE packets are routed to Rx Queues specified by PTPQ field.
21RESERVEDR0hReserved.
20MCBCQENR/W0hMulticast and Broadcast Queue Enable
This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field.
0h = Multicast and Broadcast Queue is disabled : 0x0
1h = Multicast and Broadcast Queue is enabled : 0x1
19RESERVEDR0hReserved.
18-16MCBCQR/W0hMulticast and Broadcast Queue
This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Multicast or Broadcast Packets.
0h = Receive Queue 0 : 0x0
1h = Receive Queue 1 : 0x1
2h = Receive Queue 2 : 0x2
3h = Receive Queue 3 : 0x3
4h = Receive Queue 4 : 0x4
5h = Receive Queue 5 : 0x5
6h = Receive Queue 6 : 0x6
7h = Receive Queue 7 : 0x7
15RESERVEDR0hReserved.
14-12UPQR/W0hUntagged Packet Queue
This field indicates the Rx Queue to which Untagged Packets are to be routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Untagged Packets.
0h = Receive Queue 0 : 0x0
1h = Receive Queue 1 : 0x1
2h = Receive Queue 2 : 0x2
3h = Receive Queue 3 : 0x3
4h = Receive Queue 4 : 0x4
5h = Receive Queue 5 : 0x5
6h = Receive Queue 6 : 0x6
7h = Receive Queue 7 : 0x7
11RESERVEDR0hReserved.
10-8RESERVEDR0hReserved.
7RESERVEDR0hReserved.
6-4PTPQR/W0hPTP Packets Queue
This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed.
When the AV8021ASMEN bit of MAC_Timestamp_Control register is set, only untagged PTP over Ethernet packets are routed on an Rx Queue. If the bit is not set, then based on programming of TPQC field, both tagged and untagged PTPoE packets can be routed to this Rx Queue.
0h = Receive Queue 0 : 0x0
1h = Receive Queue 1 : 0x1
2h = Receive Queue 2 : 0x2
3h = Receive Queue 3 : 0x3
4h = Receive Queue 4 : 0x4
5h = Receive Queue 5 : 0x5
6h = Receive Queue 6 : 0x6
7h = Receive Queue 7 : 0x7
3RESERVEDR0hReserved.
2-0RESERVEDR0hReserved.

43.7.3.17 MAC_RxQ_Ctrl2 Register (Offset = A8h) [Reset = 0h]

MAC_RxQ_Ctrl2 is shown in Figure 43-56 and described in Table 43-110.

Return to the Summary Table.

This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3.

Figure 43-56 MAC_RxQ_Ctrl2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDPSRQ1PSRQ0
R-0hR-0hR/W-0hR/W-0h
Table 43-110 MAC_RxQ_Ctrl2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23-16RESERVEDR0hReserved.
15-8PSRQ1R/W0hPriorities Selected in the Receive Queue 1
This field decides the priorities assigned to Rx Queue 1. All packets with priorities that match the values set in this field are routed to Rx Queue 1.
For example, if PSRQ1[4] is set, packets with USP field equal to 4 are routed to Rx Queue 1. The software must ensure that the content of this
field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues.


7-0PSRQ0R/W0hPriorities Selected in the Receive Queue 0
This field decides the priorities assigned to Rx Queue 0. All packets with priorities that match the values set in this field are routed to Rx Queue 0.
For example, if PSRQ0[5] is set, packets with USP field equal to 5 are routed to Rx Queue 0. The software must ensure that the content of this field is mutually exclusive to the PSRQ fields for other queues, that is, the same priority is not mapped to multiple Rx queues.


43.7.3.18 MAC_Interrupt_Status Register (Offset = B0h) [Reset = 0h]

MAC_Interrupt_Status is shown in Figure 43-57 and described in Table 43-111.

Return to the Summary Table.

The Interrupt Status register contains the status of interrupts.

Figure 43-57 MAC_Interrupt_Status Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDMDIOISRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRXSTSISTXSTSISTSISMMCRXIPISMMCTXISMMCRXISMMCIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDLPIISPMTISPHYISRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-111 MAC_Interrupt_Status Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved.
20RESERVEDR0hReserved.
19RESERVEDR0hReserved.
18MDIOISR0hMDIO Interrupt Status
This bit indicates an interrupt event after the completion of MDIO operation. To reset this bit, the application has to read this bit/Write 1 to this bit when RCWE bit of MAC_CSR_SW_Ctrl register is set.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = MDIO Interrupt status not active : 0x0
1h = MDIO Interrupt status active : 0x1
17RESERVEDR0hReserved.
16RESERVEDR0hReserved.
15RESERVEDR0hReserved.
14RXSTSISR0hReceive Status Interrupt
This bit indicates the status of received packets. This bit is set when the RWT bit is set in the MAC_Rx_Tx_Status register. This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set) in the MAC_Rx_Tx_Status register.
0h = Receive Interrupt status not active : 0x0
1h = Receive Interrupt status active : 0x1
13TXSTSISR0hTransmit Status Interrupt
This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the MAC_Rx_Tx_Status register:
- Excessive Collision (EXCOL)
- Late Collision (LCOL)
- Excessive Deferral (EXDEF)
- Loss of Carrier (LCARR)
- No Carrier (NCARR)
- Jabber Timeout (TJT)
This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set) in the MAC_Rx_Tx_Status register.
0h = Transmit Interrupt status not active : 0x0
1h = Transmit Interrupt status active : 0x1
12TSISR0hTimestamp Interrupt Status
If the Timestamp feature is enabled, this bit is set when any of the following conditions is true:
- The system time value is equal to or exceeds the value specified in the Target Time High and Low registers.
- There is an overflow in the Seconds register.
- The Target Time Error occurred, that is, programmed target time already elapsed.

If the Auxiliary Snapshot feature is enabled, this bit is set when the auxiliary snapshot trigger is asserted.

In configurations other than EQOS_CORE, when drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and Mac_TxTimestamp_Status_Seconds registers.
When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and MAC_Tx_Timestamp_Status_Seconds registers, for PTO generated Delay Request and Pdelay request packets.
This bit is cleared when the corresponding interrupt source bit is read (or corresponding interrupt source bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set) in the MAC_Timestamp_Status register.
0h = Timestamp Interrupt status not active : 0x0
1h = Timestamp Interrupt status active : 0x1
11MMCRXIPISR0hMMC Receive Checksum Offload Interrupt Status
This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared.
This bit is valid only when you select the Enable MAC Management Counters (MMC) and Enable Receive TCP/IP Checksum Check options.
0h = MMC Receive Checksum Offload Interrupt status not active : 0x0
1h = MMC Receive Checksum Offload Interrupt status active : 0x1
10MMCTXISR0hMMC Transmit Interrupt Status
This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared.
This bit is valid only when you select the Enable MAC Management Counters (MMC) option.
0h = MMC Transmit Interrupt status not active : 0x0
1h = MMC Transmit Interrupt status active : 0x1
9MMCRXISR0hMMC Receive Interrupt Status
This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared.
This bit is valid only when you select the Enable MAC Management Counters (MMC) option.
0h = MMC Receive Interrupt status not active : 0x0
1h = MMC Receive Interrupt status active : 0x1
8MMCISR0hMMC Interrupt Status
This bit is set high when Bit 11, Bit 10, or Bit 9 is set high. This bit is cleared only when all these bits are low. This bit is valid only when you select the Enable MAC Management Counters (MMC) option.
0h = MMC Interrupt status not active : 0x0
1h = MMC Interrupt status active : 0x1
7-6RESERVEDR0hReserved.
5LPIISR0hLPI Interrupt Status
When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the corresponding interrupt source bit of MAC_LPI_Control_Status register is read (or corresponding interrupt source bit of MAC_LPI_Control_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).
0h = LPI Interrupt status not active : 0x0
1h = LPI Interrupt status active : 0x1
4PMTISR0hPMT Interrupt Status
This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register). This bit is cleared when corresponding interrupt source bit are cleared because of a Read operation to the MAC_PMT_Control_Status register (or corresponding interrupt source bit of MAC_PMT_Control_Status register is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).
This bit is valid only when you select the Enable Power Management option.
0h = PMT Interrupt status not active : 0x0
1h = PMT Interrupt status active : 0x1
3PHYISR0hPHY Interrupt
This bit is set when rising edge is detected on the phy_intr_i input. This bit is cleared when this register is read (or this bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set).
0h = PHY Interrupt not detected : 0x0
1h = PHY Interrupt detected : 0x1
2RESERVEDR0hReserved.
1RESERVEDR0hReserved.
0RESERVEDR0hReserved.

43.7.3.19 MAC_Interrupt_Enable Register (Offset = B4h) [Reset = 0h]

MAC_Interrupt_Enable is shown in Figure 43-58 and described in Table 43-112.

Return to the Summary Table.

The Interrupt Enable register contains the masks for generating the interrupts.

Figure 43-58 MAC_Interrupt_Enable Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMDIOIERESERVEDRESERVED
R-0hR/W-0hR-0hR-0h
15141312111098
RESERVEDRXSTSIETXSTSIETSIERESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
76543210
RESERVEDLPIIEPMTIEPHYIERESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0hR-0hR-0h
Table 43-112 MAC_Interrupt_Enable Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved.
18MDIOIER/W0hMDIO Interrupt Enable
When this bit is set, it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register.
0h = MDIO Interrupt is disabled : 0x0
1h = MDIO Interrupt is enabled : 0x1
17RESERVEDR0hReserved.
16RESERVEDR0hReserved.
15RESERVEDR0hReserved.
14RXSTSIER/W0hReceive Status Interrupt Enable
When this bit is set, it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register.
0h = Receive Status Interrupt is disabled : 0x0
1h = Receive Status Interrupt is enabled : 0x1
13TXSTSIER/W0hTransmit Status Interrupt Enable
When this bit is set, it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register.
0h = Timestamp Status Interrupt is disabled : 0x0
1h = Timestamp Status Interrupt is enabled : 0x1
12TSIER/W0hTimestamp Interrupt Enable
When this bit is set, it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register.
0h = Timestamp Interrupt is disabled : 0x0
1h = Timestamp Interrupt is enabled : 0x1
11-6RESERVEDR0hReserved.
5LPIIER/W0hLPI Interrupt Enable
When this bit is set, it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register.
0h = LPI Interrupt is disabled : 0x0
1h = LPI Interrupt is enabled : 0x1
4PMTIER/W0hPMT Interrupt Enable
When this bit is set, it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register.
0h = PMT Interrupt is disabled : 0x0
1h = PMT Interrupt is enabled : 0x1
3PHYIER/W0hPHY Interrupt Enable
When this bit is set, it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register.
0h = PHY Interrupt is disabled : 0x0
1h = PHY Interrupt is enabled : 0x1
2RESERVEDR0hReserved.
1RESERVEDR0hReserved.
0RESERVEDR0hReserved.

43.7.3.20 MAC_Rx_Tx_Status Register (Offset = B8h) [Reset = 0h]

MAC_Rx_Tx_Status is shown in Figure 43-59 and described in Table 43-113.

Return to the Summary Table.

The Receive Transmit Status register contains the Receive and Transmit Error status.

Figure 43-59 MAC_Rx_Tx_Status Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRWT
R-0hR-0h
76543210
RESERVEDEXCOLLCOLEXDEFLCARRNCARRTJT
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-113 MAC_Rx_Tx_Status Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved.
8RWTR0hReceive Watchdog Timeout
This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register. This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the MAC_Configuration register.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = No receive watchdog timeout : 0x0
1h = Receive watchdog timed out : 0x1
7-6RESERVEDR0hReserved.
5EXCOLR0hExcessive Collisions
When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the MAC_Configuration register, this bit is set after the first collision and the packet transmission is aborted.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = No collision : 0x0
1h = Excessive collision is sensed : 0x1
4LCOLR0hLate Collision
When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode
512 bytes including Preamble and Carrier Extension in GMII mode).
This bit is not valid if the Underflow error occurs.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = No collision : 0x0
1h = Late collision is sensed : 0x1
3EXDEFR0hExcessive Deferral
When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or when Jumbo packet is enabled).
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = No Excessive deferral : 0x0
1h = Excessive deferral : 0x1
2LCARRR0hLoss of Carrier
When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Carrier is present : 0x0
1h = Loss of carrier : 0x1
1NCARRR0hNo Carrier
When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Carrier is present : 0x0
1h = No carrier : 0x1
0TJTR0hTransmit Jabber Timeout
This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the MAC_Configuration register.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = No Transmit Jabber Timeout : 0x0
1h = Transmit Jabber Timeout occured : 0x1

43.7.3.21 MAC_PMT_Control_Status Register (Offset = C0h) [Reset = 0h]

MAC_PMT_Control_Status is shown in Figure 43-60 and described in Table 43-114.

Return to the Summary Table.

The PMT Control and Status Register.

Figure 43-60 MAC_PMT_Control_Status Register
3130292827262524
RWKFILTRSTRESERVEDRWKPTR
R/W-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRWKPFEGLBLUCASTRESERVED
R-0hR/W-0hR/W-0hR-0h
76543210
RESERVEDRWKPRCVDMGKPRCVDRESERVEDRWKPKTENMGKPKTENPWRDWN
R-0hR-0hR-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-114 MAC_PMT_Control_Status Register Field Descriptions
BitFieldTypeResetDescription
31RWKFILTRSTR/W0hRemote Wake-Up Packet Filter Register Pointer Reset
When this bit is set, the remote wake-up packet filter register pointer is reset to 3'b000. It is automatically cleared after 1 clock cycle.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Remote Wake-Up Packet Filter Register Pointer is not Reset : 0x0
1h = Remote Wake-Up Packet Filter Register Pointer is Reset : 0x1
30-29RESERVEDR0hReserved.
28-24RWKPTRR0hRemote Wake-up FIFO Pointer
This field gives the current value (0 to 7, 15, or 31 when 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer. When the value of this pointer is equal to maximum for the selected number of Remote Wake-up Packet Filters, the contents of the Remote Wake-up Packet Filter Register are transferred to the clk_rx_i domain when a Write occurs to that register.
23-11RESERVEDR0hReserved.
10RWKPFER/W0hRemote Wake-up Packet Forwarding Enable
When this bit is set along with RWKPKTEN, the MAC receiver drops all received frames until it receives the expected Wake-up frame. All frames after that event including the received wake-up frame are forwarded to application. This bit is then self-cleared on receiving the wake-up packet.
The application can also clear this bit before the expected wake-up frame is received. In such cases, the MAC reverts to the default behavior where packets received are forwarded to the application. This bit must only be set when RWKPKTEN is set high and PWRDWN is set low. The setting of this bit has no effect when PWRDWN is set
high.
Note: If Magic Packet Enable and Wake-Up Frame Enable are both set along with setting of this bit and Magic Packet is received prior to wake-up frame, this bit is self-cleared on receiving Magic Packet, the received Magic packet is dropped, and all frames after received Magic Packet are forwarded to application.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Remote Wake-up Packet Forwarding is disabled : 0x0
1h = Remote Wake-up Packet Forwarding is enabled : 0x1
9GLBLUCASTR/W0hGlobal Unicast
When this bit set, any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet.
0h = Global unicast is disabled : 0x0
1h = Global unicast is enabled : 0x1
8-7RESERVEDR0hReserved.
6RWKPRCVDR0hRemote Wake-Up Packet Received
When this bit is set, it indicates that the power management event is generated because of the reception of a remote wake-up packet. This bit is cleared when this register is read.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Remote wake-up packet is received : 0x0
1h = Remote wake-up packet is received : 0x1
5MGKPRCVDR0hMagic Packet Received
When this bit is set, it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read.
Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = No Magic packet is received : 0x0
1h = Magic packet is received : 0x1
4-3RESERVEDR0hReserved.
2RWKPKTENR/W0hRemote Wake-Up Packet Enable
When this bit is set, a power management event is generated when the MAC receives a remote wake-up packet.
0h = Remote wake-up packet is disabled : 0x0
1h = Remote wake-up packet is enabled : 0x1
1MGKPKTENR/W0hMagic Packet Enable
When this bit is set, a power management event is generated when the MAC receives a magic packet.
0h = Magic Packet is disabled : 0x0
1h = Magic Packet is enabled : 0x1
0PWRDWNR/W0hPower Down
When this bit is set, the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet. This bit is then self-cleared and the power-down mode is disabled. The software can clear this bit before the expected magic packet or remote wake-up packet is received. The packets received by the MAC after this bit is cleared are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Packet Enable bit is set high.
Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Power down is disabled : 0x0
1h = Power down is enabled : 0x1

43.7.3.22 MAC_RWK_Packet_Filter Register (Offset = C4h) [Reset = 0h]

MAC_RWK_Packet_Filter is shown in Figure 43-61 and described in Table 43-115.

Return to the Summary Table.

The wkuppktfilter_reg register at address 0C4H loads the Wake-up Packet Filter register.
To load values in a Wake-up Packet Filter register, the entire register (wkuppktfilter_reg) must be written. The wkuppktfilter_reg register is loaded by sequentially loading the eight, sixteen or thirty two register values in address (0C4H) for wkuppktfilter_reg0, wkuppktfilter_reg1,.. wkuppktfilter_reg31, respectively. The wkuppktfilter_reg register is read in a similar way. The DWC_ether_qos updates the wkuppktfilter_reg register current pointer value in Bits[26:24] of MAC_PMT_Control_Status register.
Filter i Byte Mask: The filter i byte mask register defines the bytes of the packet that are examined by filter i (0, 1, 2, 3,..,15) to determine whether or not a packet is a wake-up packet.
- The MSB (31st bit) must be zero.
- Bit j[30:0] is the byte mask.
- If Bit j (byte number) of the byte mask is set, the CRC block processes the Filter i Offset + j of the incoming packet
otherwise Filter i Offset + j is ignored.
Filter i Command: The 4-bit filter i command controls the filter i operation.
- Bit 3 specifies the address type, defining the destination address type of the pattern. When the bit is set, the pattern applies to only multicast packets
when the bit is reset, the pattern applies only to unicast packet.
- Bit 2 (Inverse Mode), when set, reverses the logic of the CRC16 hash function signal, to reject a packet with matching CRC_16 value.
- Bit 2, along with Bit 1, allows a MAC to reject a subset of remote wake-up packets by creating filter logic such as "Pattern 1 AND NOT Pattern 2".
- Bit 1 (And_Previous) implements the Boolean logic. When set, the result of the current entry is logically ANDed with the result of the previous filter. This AND logic allows a filter pattern longer than 32 bytes by splitting the mask among two, three, or four filters. This depends on the number of filters that have the And_Previous bit set.
- Bit 0 is the enable for filter i. If Bit 0 is not set, filter i is disabled.
Filter i Offset: This filter i offset register defines the offset (within the packet) from which the filter i examines the packets.
- This 8-bit pattern-offset is the offset for the filter i first byte to be examined.
- The minimum allowed offset is 12, which refers to the 13th byte of the packet.
- The offset value 0 refers to the first byte of the packet.
Filter i CRC-16: This filter i CRC-16 register contains the CRC_16 value calculated from the pattern and also the byte mask programmed to the wake-up filter register block.
- The 16-bit CRC calculation uses the following polynomial:
G(x) = x^16 + x^15 + x^2 + 1
Each mask, used in the hash function calculation, is compared with a 16-bit value associated with that mask. Each filter has the following:
- 32-bit Mask: Each bit in this mask corresponds to one byte in the detected packet. If the bit is 1', the corresponding byte is taken into the CRC16 calculation.
- 8-bit Offset Pointer: Specifies the byte to start the CRC16 computation.
The pointer and the mask are used together to locate the bytes to be used in the CRC16 calculations.
- Note: If you are accessing these registers in byte or half-word mode, the internal counter to access the appropriate wkuppktfilter_reg is incremented when CPU accesses Lane 3 (or Lane 0 in big-endian mode).
- Note: When any Register content is being transferred to a different clock domain after a write operation, there should not be any further writes to the same location until the first write is updated. Otherwise, the second write operation does not get updated to the destination clock domain. Therefore, the delay between two writes to the same register location should be at least 4 cycles of the destination clock (PHY receive clock, PHY transmit clock, or PTP clock).
Notes on And_Previous bit setting
The And_Previous bit setting is applicable within a set of 4 filters.
- Setting of And_Previous bit of filter that is not enabled has no effect. In other words, setting And_Previous bit of lowest number filter in the set of 4 filters has no effect. For example, setting of And_Previous bit of Filter 0 has no effect.
- If And_Previous bit is set for filter to form AND chained filter, the AND chain breaks at the point any filter is not enabled. For example:
If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set) but Filter 1 is not enabled (bit 0 of in Filter 1 command is reset), then only Filter 2 result is considered.
If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 3 And_Previous bit is set (bit 1 of Filter 3 command is set), but Filter 1 is not enabled (bit 0 of in Filter 1 command is reset), then only Filter 2 result ANDed with Filter 3
result is considered.
If Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 3 And_Previous bit is set (bit 1 of Filter 3 command is set), but Filter 2 is not enabled (bit 0 of in Filter 2 command is reset), then since setting of Filter 2 And_Previous bit
has no effect only Filter 1 result ORed with Filter 3 result is considered.
- If filters chained by And_Previous bit setting have complementary programming, then a frame may never pass the AND chained filter. For example, if Filter 2 And_Previous bit is set (bit 1 of Filter 2 command is set), Filter 1 Address_Type bit is set (bit 3 of Filter 1 command is set) indicating multicast detection and Filter 2 Address_Type bit is reset (bit 3 of Filter 2 command is reset) indicating unicast detection or vice versa, a remote wakeup frame does not pass the AND chained filter as a remote wakeup frame cannot be of both unicast and multicast address type.

Figure 43-61 MAC_RWK_Packet_Filter Register
313029282726252423222120191817161514131211109876543210
WKUPFRMFTR
R/W-0h
Table 43-115 MAC_RWK_Packet_Filter Register Field Descriptions
BitFieldTypeResetDescription
31-0WKUPFRMFTRR/W0hRWK Packet Filter
This field contains the various controls of RWK Packet filter.

43.7.3.23 MAC_LPI_Control_Status Register (Offset = D0h) [Reset = 0h]

MAC_LPI_Control_Status is shown in Figure 43-62 and described in Table 43-116.

Return to the Summary Table.

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.

Figure 43-62 MAC_LPI_Control_Status Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLPITCSELPIATELPITXARESERVEDPLSLPIEN
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
15141312111098
RESERVEDRLPISTTLPIST
R-0hR-0hR-0h
76543210
RESERVEDRLPIEXRLPIENTLPIEXTLPIEN
R-0hR-0hR-0hR-0hR-0h
Table 43-116 MAC_LPI_Control_Status Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved.
21LPITCSER/W0hLPI Tx Clock Stop Enable
When this bit is set, the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
When this bit is reset, the MAC does not assert sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode.
If RGMII Interface is selected, the Tx clock is required for transmitting the LPI
pattern. The Tx Clock cannot be gated and so the LPITCSE bit cannot be
programmed.
0h = LPI Tx Clock Stop is disabled : 0x0
1h = LPI Tx Clock Stop is enabled : 0x1
20LPIATER/W0hLPI Timer Enable
This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPIATE, LPITXA and LPIEN bits are set, the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for a period indicated by the MAC_LPI_Entry_Timer register.
After entering LPI state, if the data path becomes non-IDLE (due to a new packet being accepted for transmission), the Transmitter exits LPI state but does not clear LPIEN bit. This enables the re-entry into LPI state when it is IDLE again.
When LPIATE is 0, the LPI Auto timer is disabled and MAC Transmitter enters LPI state based on the settings of LPITXA and LPIEN bit descriptions.
0h = LPI Timer is disabled : 0x0
1h = LPI Timer is enabled : 0x1
19LPITXAR/W0hLPI Tx Automate
This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. This bit is not functional in the EQOS-CORE configurations in which the Tx clock gating is done during the LPI mode.
If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding packets (in the core) and pending packets (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any packet for transmission or the application issues a Tx FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If Tx FIFO Flush is set in the FTQ bit of MTL_TxQ0_Operation_Mode register, when the MAC is in the LPI mode, it exits the LPI mode.
When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.
0h = LPI Tx Automate is disabled : 0x0
1h = LPI Tx Automate is enabled : 0x1
18RESERVEDR0hReserved.
17PLSR/W0hPHY Link Status
This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER.
When this bit is set, the link is considered to be okay (UP) and when this bit is reset, the link is considered to be down.
0h = link is down : 0x0
1h = link is okay (UP) : 0x1
16LPIENR/W0hLPI Enable
When this bit is set, it instructs the MAC Transmitter to enter the LPI state. When this bit is reset, it instructs the MAC to exit the LPI state and resume normal transmission.
This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.
0h = LPI state is disabled : 0x0
1h = LPI state is enabled : 0x1
15-10RESERVEDR0hReserved.
9RLPISTR0hReceive LPI State
When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface.
0h = Receive LPI state not detected : 0x0
1h = Receive LPI state detected : 0x1
8TLPISTR0hTransmit LPI State
When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface.
0h = Transmit LPI state not detected : 0x0
1h = Transmit LPI state detected : 0x1
7-4RESERVEDR0hReserved.
3RLPIEXR0hReceive LPI Exit
When this bit is set, it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).
Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock.
0h = Receive LPI exit not detected : 0x0
1h = Receive LPI exit detected : 0x1
2RLPIENR0hReceive LPI Entry
When this bit is set, it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).
Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than three clock cycles of CSR clock.
0h = Receive LPI entry not detected : 0x0
1h = Receive LPI entry detected : 0x1
1TLPIEXR0hTransmit LPI Exit
When this bit is set, it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).
0h = Transmit LPI exit not detected : 0x0
1h = Transmit LPI exit detected : 0x1
0TLPIENR0hTransmit LPI Entry
When this bit is set, it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set).
0h = Transmit LPI entry not detected : 0x0
1h = Transmit LPI entry detected : 0x1

43.7.3.24 MAC_LPI_Timers_Control Register (Offset = D4h) [Reset = 03E80000h]

MAC_LPI_Timers_Control is shown in Figure 43-63 and described in Table 43-117.

Return to the Summary Table.

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.

Figure 43-63 MAC_LPI_Timers_Control Register
31302928272625242322212019181716
RESERVEDLST
R-0hR/W-3E8h
1514131211109876543210
TWT
R/W-0h
Table 43-117 MAC_LPI_Timers_Control Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved.
25-16LSTR/W3E8hLPI LS Timer
This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard.
15-0TWTR/W0hLPI TW Timer
This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.

43.7.3.25 MAC_LPI_Entry_Timer Register (Offset = D8h) [Reset = 0h]

MAC_LPI_Entry_Timer is shown in Figure 43-64 and described in Table 43-118.

Return to the Summary Table.

This register controls the Tx LPI entry timer. This counter is enabled only when bit[20](LPITE) bit of MAC_LPI_Control_Status is set to 1.

Figure 43-64 MAC_LPI_Entry_Timer Register
31302928272625242322212019181716
RESERVEDLPIET
R-0hR/W-0h
1514131211109876543210
LPIETRESERVED
R/W-0hR-0h
Table 43-118 MAC_LPI_Entry_Timer Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved.
19-3LPIETR/W0hLPI Entry Timer
This field specifies the time in microseconds the MAC waits to enter LPI mode, after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1.
Bits [2:0] are read-only so that the granularity of this timer is in steps of 8 micro-seconds.
2-0RESERVEDR0hReserved.

43.7.3.26 MAC_1US_Tic_Counter Register (Offset = DCh) [Reset = 63h]

MAC_1US_Tic_Counter is shown in Figure 43-65 and described in Table 43-119.

Return to the Summary Table.

This register controls the generation of the Reference time (1 microsecond tic) for all the LPI timers. This timer has to be programmed by the software initially.

Figure 43-65 MAC_1US_Tic_Counter Register
313029282726252423222120191817161514131211109876543210
RESERVEDTIC_1US_CNTR
R-0hR/W-63h
Table 43-119 MAC_1US_Tic_Counter Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved.
11-0TIC_1US_CNTRR/W63h1US TIC Counter
The application must program this counter so that the number of clock cycles of CSR clock is 1us.
(Subtract 1 from the value before programming).
For example if the CSR clock is 100MHz then this field needs to be programmed to value 100 - 1 = 99 (which is 0x63).
This is required to generate the 1US events that are used to update some of the EEE related counters.

43.7.3.27 MAC_Version Register (Offset = 110h) [Reset = 50h]

MAC_Version is shown in Figure 43-66 and described in Table 43-120.

Return to the Summary Table.

The version register identifies the version of the DWC_ether_qos. This register contains two bytes: one that Synopsys uses to identify the core release number, and the other that you set while configuring the core.

Figure 43-66 MAC_Version Register
313029282726252423222120191817161514131211109876543210
RESERVEDUSERVERSNPSVER
R-0hR-0hR-50h
Table 43-120 MAC_Version Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-8USERVERR0hUser-defined Version (configured with coreConsultant)
7-0SNPSVERR50hSynopsys-defined Version

43.7.3.28 MAC_Debug Register (Offset = 114h) [Reset = 0h]

MAC_Debug is shown in Figure 43-67 and described in Table 43-121.

Return to the Summary Table.

The Debug register provides the debug status of various MAC blocks.

Figure 43-67 MAC_Debug Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTFCSTSTPESTS
R-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRFCFCSTSRPESTS
R-0hR-0hR-0h
Table 43-121 MAC_Debug Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved.
18-17TFCSTSR0hMAC Transmit Packet Controller Status
This field indicates the state of the MAC Transmit Packet Controller module.
0h = Idle state : 0x0
1h = Waiting for one of the following: Status of the previous packet OR IPG or backoff period to be over : 0x1
2h = Generating and transmitting a Pause control packet (in full-duplex mode) : 0x2
3h = Transferring input packet for transmission : 0x3
16TPESTSR0hMAC GMII or MII Transmit Protocol Engine Status
When this bit is set, it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in the Idle state.
0h = MAC GMII or MII Transmit Protocol Engine Status not detected : 0x0
1h = MAC GMII or MII Transmit Protocol Engine Status detected : 0x1
15-3RESERVEDR0hReserved.
2-1RFCFCSTSR0hMAC Receive Packet Controller FIFO Status
When this bit is set, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module.
0RPESTSR0hMAC GMII or MII Receive Protocol Engine Status
When this bit is set, it indicates that the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the Idle state.
0h = MAC GMII or MII Receive Protocol Engine Status not detected : 0x0
1h = MAC GMII or MII Receive Protocol Engine Status detected : 0x1

43.7.3.29 MAC_HW_Feature0 Register (Offset = 11Ch) [Reset = 0E1D73F5h]

MAC_HW_Feature0 is shown in Figure 43-68 and described in Table 43-122.

Return to the Summary Table.

This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
Note: All bits are set or reset according to the features selected while configuring the core in coreConsultant.

Figure 43-68 MAC_HW_Feature0 Register
3130292827262524
RESERVEDACTPHYSELSAVLANINSTSSTSSELMACADR64SEL
R-0hR-0hR-1hR-3hR-0h
2322212019181716
MACADR32SELADDMACADRSELRESERVEDRXCOESEL
R-0hR-7hR-0hR-1h
15141312111098
RESERVEDTXCOESELEEESELTSSELRESERVEDARPOFFSELMMCSEL
R-0hR-1hR-1hR-1hR-0hR-1hR-1h
76543210
MGKSELRWKSELSMASELVLHASHPCSSELHDSELGMIISELMIISEL
R-1hR-1hR-1hR-1hR-0hR-1hR-0hR-1h
Table 43-122 MAC_HW_Feature0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30-28ACTPHYSELR0hActive PHY Selected
When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
0h = GMII or MII : 0x0
1h = RGMII : 0x1
2h = SGMII : 0x2
3h = TBI : 0x3
4h = RMII : 0x4
5h = RTBI : 0x5
6h = SMII : 0x6
7h = RevMII : 0x7
27SAVLANINSR1hSource Address or VLAN Insertion Enable
This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected
0h = Source Address or VLAN Insertion Enable option is not selected : 0x0
1h = Source Address or VLAN Insertion Enable option is selected : 0x1
26-25TSSTSSELR3hTimestamp System Time Source
This bit indicates the source of the Timestamp system time:
This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
0h = Internal : 0x0
1h = External : 0x1
2h = Both : 0x2
3h = Reserved : 0x3
24MACADR64SELR0hMAC Addresses 64-127 Selected
This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected
0h = MAC Addresses 64-127 Select option is not selected : 0x0
1h = MAC Addresses 64-127 Select option is selected : 0x1
23MACADR32SELR0hMAC Addresses 32-63 Selected
This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected
0h = MAC Addresses 32-63 Select option is not selected : 0x0
1h = MAC Addresses 32-63 Select option is selected : 0x1
22-18ADDMACADRSELR7hMAC Addresses 1-31 Selected
This bit is set to 1 when the Enable Additional 1-31 MAC Address Registers option is selected
17RESERVEDR0hReserved.
16RXCOESELR1hReceive Checksum Offload Enabled
This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
0h = Receive Checksum Offload Enable option is not selected : 0x0
1h = Receive Checksum Offload Enable option is selected : 0x1
15RESERVEDR0hReserved.
14TXCOESELR1hTransmit Checksum Offload Enabled
This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected
0h = Transmit Checksum Offload Enable option is not selected : 0x0
1h = Transmit Checksum Offload Enable option is selected : 0x1
13EEESELR1hEnergy Efficient Ethernet Enabled
This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected
0h = Energy Efficient Ethernet Enable option is not selected : 0x0
1h = Energy Efficient Ethernet Enable option is selected : 0x1
12TSSELR1hIEEE 1588-2008 Timestamp Enabled
This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
0h = IEEE 1588-2008 Timestamp Enable option is not selected : 0x0
1h = IEEE 1588-2008 Timestamp Enable option is selected : 0x1
11-10RESERVEDR0hReserved.
9ARPOFFSELR1hARP Offload Enabled
This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
0h = ARP Offload Enable option is not selected : 0x0
1h = ARP Offload Enable option is selected : 0x1
8MMCSELR1hRMON Module Enable
This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
0h = RMON Module Enable option is not selected : 0x0
1h = RMON Module Enable option is selected : 0x1
7MGKSELR1hPMT Magic Packet Enable
This bit is set to 1 when the Enable Magic Packet Detection option is selected
0h = PMT Magic Packet Enable option is not selected : 0x0
1h = PMT Magic Packet Enable option is selected : 0x1
6RWKSELR1hPMT Remote Wake-up Packet Enable
This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
0h = PMT Remote Wake-up Packet Enable option is not selected : 0x0
1h = PMT Remote Wake-up Packet Enable option is selected : 0x1
5SMASELR1hSMA (MDIO) Interface
This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
0h = SMA (MDIO) Interface not selected : 0x0
1h = SMA (MDIO) Interface selected : 0x1
4VLHASHR1hVLAN Hash Filter Selected
This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
0h = VLAN Hash Filter not selected : 0x0
1h = VLAN Hash Filter selected : 0x1
3PCSSELR0hPCS Registers (TBI, SGMII, or RTBI PHY interface)
This bit is set to 1 when the TBI, SGMII, or RTBI PHY interface option is selected
0h = No PCS Registers (TBI, SGMII, or RTBI PHY interface) : 0x0
1h = PCS Registers (TBI, SGMII, or RTBI PHY interface) : 0x1
2HDSELR1hHalf-duplex Support
This bit is set to 1 when the half-duplex mode is selected
0h = No Half-duplex support : 0x0
1h = Half-duplex support : 0x1
1GMIISELR0h1000 Mbps Support
This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
0h = No 1000 Mbps support : 0x0
1h = 1000 Mbps support : 0x1
0MIISELR1h10 or 100 Mbps Support
This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
0h = No 10 or 100 Mbps support : 0x0
1h = 10 or 100 Mbps support : 0x1

43.7.3.30 MAC_HW_Feature1 Register (Offset = 120h) [Reset = 218E3965h]

MAC_HW_Feature1 is shown in Figure 43-69 and described in Table 43-123.

Return to the Summary Table.

This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
Note: All bits are set or reset according to the features selected while configuring the core in coreConsultant.

Figure 43-69 MAC_HW_Feature1 Register
3130292827262524
RESERVEDL3L4FNUMRESERVEDHASHTBLSZ
R-0hR-4hR-0hR-1h
2322212019181716
POUOSTRESERVEDRAVSELAVSELDBGMEMATSOENSPHENDCBEN
R-1hR-0hR-0hR-0hR-1hR-1hR-1hR-0h
15141312111098
ADDR64ADVTHWORDPTOENOSTENTXFIFOSIZE
R-0hR-1hR-1hR-1hR-5h
76543210
TXFIFOSIZESPRAMRXFIFOSIZE
R-5hR-1hR-5h
Table 43-123 MAC_HW_Feature1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30-27L3L4FNUMR4hTotal number of L3 or L4 Filters
This field indicates the total number of L3 or L4 filters:
0h = No L3 or L4 Filter : 0x0
1h = 1 L3 or L4 Filter : 0x1
2h = 2 L3 or L4 Filters : 0x2
3h = 3 L3 or L4 Filters : 0x3
4h = 4 L3 or L4 Filters : 0x4
5h = 5 L3 or L4 Filters : 0x5
6h = 6 L3 or L4 Filters : 0x6
7h = 7 L3 or L4 Filters : 0x7
8h = 8 L3 or L4 Filters : 0x8
26RESERVEDR0hReserved.
25-24HASHTBLSZR1hHash Table Size
This field indicates the size of the hash table:
0h = No hash table : 0x0
1h = 64 : 0x1
2h = 128 : 0x2
3h = 256 : 0x3
23POUOSTR1hOne Step for PTP over UDP/IP Feature Enable
This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected.
0h = One Step for PTP over UDP/IP Feature is not selected : 0x0
1h = One Step for PTP over UDP/IP Feature is selected : 0x1
22RESERVEDR0hReserved.
21RAVSELR0hRx Side Only AV Feature Enable
This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected.
0h = Rx Side Only AV Feature is not selected : 0x0
1h = Rx Side Only AV Feature is selected : 0x1
20AVSELR0hAV Feature Enable
This bit is set to 1 when the Enable Audio Video Bridging option is selected.
0h = AV Feature is not selected : 0x0
1h = AV Feature is selected : 0x1
19DBGMEMAR1hDMA Debug Registers Enable
This bit is set to 1 when the Debug Mode Enable option is selected
0h = DMA Debug Registers option is not selected : 0x0
1h = DMA Debug Registers option is selected : 0x1
18TSOENR1hTCP Segmentation Offload Enable
This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected
0h = TCP Segmentation Offload Feature is not selected : 0x0
1h = TCP Segmentation Offload Feature is selected : 0x1
17SPHENR1hSplit Header Feature Enable
This bit is set to 1 when the Enable Split Header Structure option is selected
0h = Split Header Feature is not selected : 0x0
1h = Split Header Feature is selected : 0x1
16DCBENR0hDCB Feature Enable
This bit is set to 1 when the Enable Data Center Bridging option is selected
0h = DCB Feature is not selected : 0x0
1h = DCB Feature is selected : 0x1
15-14ADDR64R0hAddress Width.
This field indicates the configured address width:
0h = 32 : 0x0
1h = 40 : 0x1
2h = 48 : 0x2
3h = Reserved : 0x3
13ADVTHWORDR1hIEEE 1588 High Word Register Enable
This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
0h = IEEE 1588 High Word Register option is not selected : 0x0
1h = IEEE 1588 High Word Register option is selected : 0x1
12PTOENR1hPTP Offload Enable
This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
0h = PTP Offload feature is not selected : 0x0
1h = PTP Offload feature is selected : 0x1
11OSTENR1hOne-Step Timestamping Enable
This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
0h = One-Step Timestamping feature is not selected : 0x0
1h = One-Step Timestamping feature is selected : 0x1
10-6TXFIFOSIZER5hMTL Transmit FIFO Size
This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
0h = 128 bytes : 0x0
1h = 256 bytes : 0x1
2h = 512 bytes : 0x2
3h = 1024 bytes : 0x3
4h = 2048 bytes : 0x4
5h = 4096 bytes : 0x5
6h = 8192 bytes : 0x6
7h = 16384 bytes : 0x7
8h = 32 KB : 0x8
9h = 64 KB : 0x9
Ah = 128 KB : 0xa
Bh = Reserved : 0xb
5SPRAMR1hSingle Port RAM Enable
This bit is set to 1 when the Use single port RAM Feature is selected.
0h = Single Port RAM feature is not selected : 0x0
1h = Single Port RAM feature is selected : 0x1
4-0RXFIFOSIZER5hMTL Receive FIFO Size
This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
0h = 128 bytes : 0x0
1h = 256 bytes : 0x1
2h = 512 bytes : 0x2
3h = 1024 bytes : 0x3
4h = 2048 bytes : 0x4
5h = 4096 bytes : 0x5
6h = 8192 bytes : 0x6
7h = 16384 bytes : 0x7
8h = 32 KB : 0x8
9h = 64 KB : 0x9
Ah = 128 KB : 0xa
Bh = 256 KB : 0xb
Ch = Reserved : 0xc

43.7.3.31 MAC_HW_Feature2 Register (Offset = 124h) [Reset = 22041041h]

MAC_HW_Feature2 is shown in Figure 43-70 and described in Table 43-124.

Return to the Summary Table.

This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Figure 43-70 MAC_HW_Feature2 Register
3130292827262524
RESERVEDAUXSNAPNUMRESERVEDPPSOUTNUM
R-0hR-2hR-0hR-2h
2322212019181716
RESERVEDTXCHCNTRESERVED
R-0hR-1hR-0h
15141312111098
RXCHCNTRESERVEDTXQCNT
R-1hR-0hR-1h
76543210
TXQCNTRESERVEDRXQCNT
R-1hR-0hR-1h
Table 43-124 MAC_HW_Feature2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30-28AUXSNAPNUMR2hNumber of Auxiliary Snapshot Inputs
This field indicates the number of auxiliary snapshot inputs:
0h = No auxiliary input : 0x0
1h = 1 auxiliary input : 0x1
2h = 2 auxiliary input : 0x2
3h = 3 auxiliary input : 0x3
4h = 4 auxiliary input : 0x4
5h = Reserved : 0x5
27RESERVEDR0hReserved.
26-24PPSOUTNUMR2hNumber of PPS Outputs
This field indicates the number of PPS outputs:
0h = No PPS output : 0x0
1h = 1 PPS output : 0x1
2h = 2 PPS output : 0x2
3h = 3 PPS output : 0x3
4h = 4 PPS output : 0x4
5h = Reserved : 0x5
23-22RESERVEDR0hReserved.
21-18TXCHCNTR1hNumber of DMA Transmit Channels
This field indicates the number of DMA Transmit channels:
0h = 1 MTL Tx Channel : 0x0
1h = 2 MTL Tx Channels : 0x1
2h = 3 MTL Tx Channels : 0x2
3h = 4 MTL Tx Channels : 0x3
4h = 5 MTL Tx Channels : 0x4
5h = 6 MTL Tx Channels : 0x5
6h = 7 MTL Tx Channels : 0x6
7h = 8 MTL Tx Channels : 0x7
17-16RESERVEDR0hReserved.
15-12RXCHCNTR1hNumber of DMA Receive Channels
This field indicates the number of DMA Receive channels:
0h = 1 MTL Rx Channel : 0x0
1h = 2 MTL Rx Channels : 0x1
2h = 3 MTL Rx Channels : 0x2
3h = 4 MTL Rx Channels : 0x3
4h = 5 MTL Rx Channels : 0x4
5h = 6 MTL Rx Channels : 0x5
6h = 7 MTL Rx Channels : 0x6
7h = 8 MTL Rx Channels : 0x7
11-10RESERVEDR0hReserved.
9-6TXQCNTR1hNumber of MTL Transmit Queues
This field indicates the number of MTL Transmit queues:
0h = 1 MTL Tx Queue : 0x0
1h = 2 MTL Tx Queues : 0x1
2h = 3 MTL Tx Queues : 0x2
3h = 4 MTL Tx Queues : 0x3
4h = 5 MTL Tx Queues : 0x4
5h = 6 MTL Tx Queues : 0x5
6h = 7 MTL Tx Queues : 0x6
7h = 8 MTL Tx Queues : 0x7
5-4RESERVEDR0hReserved.
3-0RXQCNTR1hNumber of MTL Receive Queues
This field indicates the number of MTL Receive queues:
0h = 1 MTL Rx Queue : 0x0
1h = 2 MTL Rx Queues : 0x1
2h = 3 MTL Rx Queues : 0x2
3h = 4 MTL Rx Queues : 0x3
4h = 5 MTL Rx Queues : 0x4
5h = 6 MTL Rx Queues : 0x5
6h = 7 MTL Rx Queues : 0x6
7h = 8 MTL Rx Queues : 0x7

43.7.3.32 MAC_HW_Feature3 Register (Offset = 128h) [Reset = 00320031h]

MAC_HW_Feature3 is shown in Figure 43-71 and described in Table 43-125.

Return to the Summary Table.

This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Figure 43-71 MAC_HW_Feature3 Register
3130292827262524
RESERVEDTBSSELFPESELRESERVEDESTTISW
R-0hR-0hR-0hR-0hR-0h
2322212019181716
ESTTISWRESERVEDESTWIDESTDEPESTSEL
R-0hR-0hR-3hR-1hR-0h
15141312111098
RESERVEDPDUPSELDBGSSEL
R-0hR-0hR-0h
76543210
RESERVEDDVLANCBTISELRESERVEDNRVF
R-0hR-1hR-1hR-0hR-1h
Table 43-125 MAC_HW_Feature3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27TBSSELR0hTime Based Scheduling Enable
This bit is set to 1 when the Time Based Scheduling feature is selected.
0h = Time Based Scheduling Enable feature is not selected : 0x0
1h = Time Based Scheduling Enable feature is selected : 0x1
26FPESELR0hFrame Preemption Enable
This bit is set to 1 when the Enable Frame preemption feature is selected.
0h = Frame Preemption Enable feature is not selected : 0x0
1h = Frame Preemption Enable feature is selected : 0x1
25RESERVEDR0hReserved.
24-23ESTTISWR0hWidth of the Left Shift Amount for Time Interval
This field indicates the width of programmable left shift field for Time Interval
0h = 0 : 0x0
1h = 1 : 0x1
2h = 2 : 0x2
3h = 3 : 0x3
22RESERVEDR0hReserved.
21-20ESTWIDR3hWidth of the Time Interval field in the Gate Control List
This field indicates the width of the Configured Time Interval Field
0h = Width not configured : 0x0
1h = 16 : 0x1
2h = 20 : 0x2
3h = 24 : 0x3
19-17ESTDEPR1hDepth of the Gate Control List
This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
0h = No Depth configured : 0x0
1h = 64 : 0x1
2h = 128 : 0x2
3h = 256 : 0x3
4h = 512 : 0x4
5h = 1024 : 0x5
6h = Reserved : 0x6
16ESTSELR0hEnhancements to Scheduling Traffic Enable
This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected.
0h = Enable Enhancements to Scheduling Traffic feature is not selected : 0x0
1h = Enable Enhancements to Scheduling Traffic feature is selected : 0x1
15-10RESERVEDR0hReserved.
9PDUPSELR0hBroadcast/Multicast Packet Duplication
This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected.
0h = Broadcast/Multicast Packet Duplication feature is not selected : 0x0
1h = Broadcast/Multicast Packet Duplication feature is selected : 0x1
8DBGSSELR0hDebug Bus Support Enable
This bit is set to 1 when the Enable Debug Bus Support feature is selected.
0h = Debug Bus Support Enable feature is not selected : 0x0
1h = Debug Bus Support Enable feature is selected : 0x1
7-6RESERVEDR0hReserved.
5DVLANR1h
4CBTISELR1hQueue/Channel based VLAN tag insertion on Tx Enable
This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
0h = Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected : 0x0
1h = Enable Queue/Channel based VLAN tag insertion on Tx feature is selected : 0x1
3RESERVEDR0hReserved.
2-0NRVFR1hNumber of Extended VLAN Tag Filters Enabled
This field indicates the Number of Extended VLAN Tag Filters selected:
0h = No Extended Rx VLAN Filters : 0x0
1h = 4 Extended Rx VLAN Filters : 0x1
2h = 8 Extended Rx VLAN Filters : 0x2
3h = 16 Extended Rx VLAN Filters : 0x3
4h = 24 Extended Rx VLAN Filters : 0x4
5h = 32 Extended Rx VLAN Filters : 0x5
6h = Reserved : 0x6

43.7.3.33 MAC_MDIO_Address Register (Offset = 200h) [Reset = 0h]

MAC_MDIO_Address is shown in Figure 43-72 and described in Table 43-126.

Return to the Summary Table.

The MDIO Address register controls the management cycles to external PHY through a management interface.

Figure 43-72 MAC_MDIO_Address Register
3130292827262524
RESERVEDPSEBTBPA
R-0hR/W-0hR/W-0hR/W-0h
2322212019181716
PARDA
R/W-0hR/W-0h
15141312111098
RESERVEDNTCCR
R-0hR/W-0hR/W-0h
76543210
RESERVEDSKAPGOC_1GOC_0C45EGB
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-126 MAC_MDIO_Address Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27PSER/W0hPreamble Suppression Enable
When this bit is set, the SMA suppresses the 32-bit preamble and transmits
MDIO frames with only 1 preamble bit.
When this bit is 0, the MDIO frame always has 32 bits of preamble as defined
in the IEEE specifications.
0h = Preamble Suppression disabled : 0x0
1h = Preamble Suppression enabled : 0x1
26BTBR/W0hBack to Back transactions
When this bit is set and the NTC has value greater than 0, then the MAC
informs the completion of a read or write command at the end of frame transfer
(before the trailing clocks are transmitted). The software can thus initiate the
next command which is executed immediately irrespective of the number
trailing clocks generated for the previous frame.
When this bit is reset, then the read/write command completion (GB is
cleared)only after the trailing clocks are generated. In this mode, it is ensured
that the NTC is always generated after each frame.
This bit must not be set when NTC=0.
0h = Back to Back transactions disabled : 0x0
1h = Back to Back transactions enabled : 0x1
25-21PAR/W0hPhysical Layer Address
This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. For RevMII, this field gives the PHY Address of the RevMII module. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing.
20-16RDAR/W0hRegister/Device Address
These bits select the PHY register in selected Clause 22 PHY device. For RevMII, these bits select the CSR register in the RevMII Registers set. These bits select the Device (MMD) in selected Clause 45 capable PHY.
15RESERVEDR0hReserved.
14-12NTCR/W0hNumber of Trailing Clocks
This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 3'h3 indicates that there are additional three clock cycles on the MDC line after the end of MDIO frame transfer.
11-8CRR/W0hCSR Clock Range
The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design:
- 0000: CSR clock = 60-100 MHz
MDC clock = CSR clock/42
- 0001: CSR clock = 100-150 MHz
MDC clock = CSR clock/62
- 0010: CSR clock = 20-35 MHz
MDC clock = CSR clock/16
- 0011: CSR clock = 35-60 MHz
MDC clock = CSR clock/26
- 0100: CSR clock = 150-250 MHz
MDC clock = CSR clock/102
- 0101: CSR clock = 250-300 MHz
MDC clock = CSR clock/124
- 0110: CSR clock = 300-500 MHz
MDC clock = CSR clock/204
- 0111: CSR clock = 500-800 MHz
MDC clock = CSR clock/324
The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz freqency range.
When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, the resultant MDC clock is of 12.5 MHz which is above the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks:
- 1000: CSR clock/4
- 1001: CSR clock/6
- 1010: CSR clock/8
- 1011: CSR clock/10
- 1100: CSR clock/12
- 1101: CSR clock/14
- 1110: CSR clock/16
- 1111: CSR clock/18
These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface.
7-5RESERVEDR0hReserved.
4SKAPR/W0hSkip Address Packet
When this bit is set, the SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set.
0h = Skip Address Packet is disabled : 0x0
1h = Skip Address Packet is enabled : 0x1
3GOC_1R/W0hGMII Operation Command 1
This bit is higher bit of the operation command to the PHY or RevMII, GOC_1 and GOC_O is encoded as follows:
- 00: Reserved
- 01: Write
- 10: Post Read Increment Address for Clause 45 PHY
- 11: Read
When Clause 22 PHY or RevMII is enabled, only Write and Read commands are valid.
0h = GMII Operation Command 1 is disabled : 0x0
1h = GMII Operation Command 1 is enabled : 0x1
2GOC_0R/W0hGMII Operation Command 0
This is the lower bit of the operation command to the PHY or RevMII. When in SMA mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY.
When only RevMII is selected in configuration this bit is read-only and tied to 1.
0h = GMII Operation Command 0 is disabled : 0x0
1h = GMII Operation Command 0 is enabled : 0x1
1C45ER/W0hClause 45 PHY Enable
When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO.
0h = Clause 45 PHY is disabled : 0x0
1h = Clause 45 PHY is enabled : 0x1
0GBR/W0hGMII Busy
The application sets this bit to instruct the SMA to initiate a Read or Write
access to the MDIO slave. The MAC clears this bit after the MDIO frame
transfer is completed. Hence the software must not write or change any of the
fields in MAC_MDIO_Address and MAC_MDIO_Data registers as long as this
bit is set.
For write transfers, the application must first write 16-bit data in the GDl field (and also RA field when C45E is set) in MAC_MDIO_Data register before
setting this bit. When C45E is set, it should also write into the RA field of
MAC_MDIO_Data register before initiating a read transfer. When a read
transfer is completed (GB=0), the data read from the PHY register is valid in
the GD field of the MAC_MDIO_Data register.
Note: Even if the addressed PHY is not present, there is no change in the functionality of this bit.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = GMII Busy is disabled : 0x0
1h = GMII Busy is enabled : 0x1

43.7.3.34 MAC_MDIO_Data Register (Offset = 204h) [Reset = 0h]

MAC_MDIO_Data is shown in Figure 43-73 and described in Table 43-127.

Return to the Summary Table.

The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register.

Figure 43-73 MAC_MDIO_Data Register
313029282726252423222120191817161514131211109876543210
RAGD
R/W-0hR/W-0h
Table 43-127 MAC_MDIO_Data Register Field Descriptions
BitFieldTypeResetDescription
31-16RAR/W0hRegister Address
This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for.
15-0GDR/W0hGMII Data
This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation.

43.7.3.35 MAC_ARP_Address Register (Offset = 210h) [Reset = 0h]

MAC_ARP_Address is shown in Figure 43-74 and described in Table 43-128.

Return to the Summary Table.

The ARP Address register contains the IPv4 Destination Address of the MAC. Note: IP address should be written to this register in host byte order format.

Figure 43-74 MAC_ARP_Address Register
313029282726252423222120191817161514131211109876543210
ARPPA
R/W-0h
Table 43-128 MAC_ARP_Address Register Field Descriptions
BitFieldTypeResetDescription
31-0ARPPAR/W0hARP Protocol Address
This field contains the IPv4 Destination Address of the MAC. This address is used for perfect match with the Protocol Address of Target field in the received ARP packet.
This field is available only when the Enable IPv4 ARP Offload option is selected.

43.7.3.36 MAC_CSR_SW_Ctrl Register (Offset = 230h) [Reset = 0h]

MAC_CSR_SW_Ctrl is shown in Figure 43-75 and described in Table 43-129.

Return to the Summary Table.

This register contains SW programmable controls for changing the CSR access response and status bits clearing.

Figure 43-75 MAC_CSR_SW_Ctrl Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVED
R-0hR-0h
76543210
RESERVEDRCWE
R-0hR/W-0h
Table 43-129 MAC_CSR_SW_Ctrl Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved.
8RESERVEDR0hReserved.
7-1RESERVEDR0hReserved.
0RCWER/W0hRegister Clear on Write 1 Enable
When this bit is set, the access mode of some register fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to clear it.
When this bit is reset, the access mode of these register fields remain as Clear on Read.
0h = Register Clear on Write 1 is disabled : 0x0
1h = Register Clear on Write 1 is enabled : 0x1

43.7.3.37 MAC_Ext_Cfg1 Register (Offset = 238h) [Reset = 2h]

MAC_Ext_Cfg1 is shown in Figure 43-76 and described in Table 43-130.

Return to the Summary Table.

This register contains Split mode control field and offset field for Split Header feature.

Figure 43-76 MAC_Ext_Cfg1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSPLM
R-0hR/W-0h
76543210
RESERVEDSPLOFST
R-0hR/W-2h
Table 43-130 MAC_Ext_Cfg1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved.
9-8SPLMR/W0hSplit Mode
These bits indicate the mode of splitting the incoming Rx packets. They are
0h = Split at L3/L4 header : 0x0
1h = Split at L2 header with an offset. Always Split at SPLOFST bytes from the beginning of Length/Type field of the Frame : 0x1
2h = Combination mode: Split similar to SPLM=00 for IP packets that are untagged or tagged and VLAN stripped : 0x2
3h = Reserved : 0x3
7RESERVEDR0hReserved.
6-0SPLOFSTR/W2hSplit Offset
These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected. The reset value of this field is 2 bytes indicating a split at L2 header. Value is in terms of bytes.

43.7.3.38 MAC_Address0_High Register (Offset = 300h) [Reset = 8000FFFFh]

MAC_Address0_High is shown in Figure 43-77 and described in Table 43-131.

Return to the Summary Table.

The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-77 MAC_Address0_High Register
31302928272625242322212019181716
AERESERVEDDCS
R-1hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-131 MAC_Address0_High Register Field Descriptions
BitFieldTypeResetDescription
31AER1hAddress Enable
This bit is always set to 1.
0h = INVALID : This bit must be always set to 1 : 0x0
1h = This bit is always set to 1 : 0x1
30-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address0[47:32]
This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets.

43.7.3.39 MAC_Address0_Low Register (Offset = 304h) [Reset = FFFFFFFFh]

MAC_Address0_Low is shown in Figure 43-78 and described in Table 43-132.

Return to the Summary Table.

The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station.

Figure 43-78 MAC_Address0_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-132 MAC_Address0_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address0[31:0]
This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets.

43.7.3.40 MAC_Address1_High Register (Offset = 308h) [Reset = FFFFh]

MAC_Address1_High is shown in Figure 43-79 and described in Table 43-133.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-79 MAC_Address1_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-133 MAC_Address1_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.41 MAC_Address1_Low Register (Offset = 30Ch) [Reset = FFFFFFFFh]

MAC_Address1_Low is shown in Figure 43-80 and described in Table 43-134.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-80 MAC_Address1_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-134 MAC_Address1_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.42 MAC_Address2_High Register (Offset = 310h) [Reset = FFFFh]

MAC_Address2_High is shown in Figure 43-81 and described in Table 43-135.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-81 MAC_Address2_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-135 MAC_Address2_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.43 MAC_Address2_Low Register (Offset = 314h) [Reset = FFFFFFFFh]

MAC_Address2_Low is shown in Figure 43-82 and described in Table 43-136.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-82 MAC_Address2_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-136 MAC_Address2_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.44 MAC_Address3_High Register (Offset = 318h) [Reset = FFFFh]

MAC_Address3_High is shown in Figure 43-83 and described in Table 43-137.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-83 MAC_Address3_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-137 MAC_Address3_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.45 MAC_Address3_Low Register (Offset = 31Ch) [Reset = FFFFFFFFh]

MAC_Address3_Low is shown in Figure 43-84 and described in Table 43-138.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-84 MAC_Address3_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-138 MAC_Address3_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.46 MAC_Address4_High Register (Offset = 320h) [Reset = FFFFh]

MAC_Address4_High is shown in Figure 43-85 and described in Table 43-139.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-85 MAC_Address4_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-139 MAC_Address4_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.47 MAC_Address4_Low Register (Offset = 324h) [Reset = FFFFFFFFh]

MAC_Address4_Low is shown in Figure 43-86 and described in Table 43-140.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-86 MAC_Address4_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-140 MAC_Address4_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.48 MAC_Address5_High Register (Offset = 328h) [Reset = FFFFh]

MAC_Address5_High is shown in Figure 43-87 and described in Table 43-141.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-87 MAC_Address5_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-141 MAC_Address5_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.49 MAC_Address5_Low Register (Offset = 32Ch) [Reset = FFFFFFFFh]

MAC_Address5_Low is shown in Figure 43-88 and described in Table 43-142.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-88 MAC_Address5_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-142 MAC_Address5_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.50 MAC_Address6_High Register (Offset = 330h) [Reset = FFFFh]

MAC_Address6_High is shown in Figure 43-89 and described in Table 43-143.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-89 MAC_Address6_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-143 MAC_Address6_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.51 MAC_Address6_Low Register (Offset = 334h) [Reset = FFFFFFFFh]

MAC_Address6_Low is shown in Figure 43-90 and described in Table 43-144.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-90 MAC_Address6_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-144 MAC_Address6_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.52 MAC_Address7_High Register (Offset = 338h) [Reset = FFFFh]

MAC_Address7_High is shown in Figure 43-91 and described in Table 43-145.

Return to the Summary Table.

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Figure 43-91 MAC_Address7_High Register
31302928272625242322212019181716
AESAMBCRESERVEDDCS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
ADDRHI
R/W-FFFFh
Table 43-145 MAC_Address7_High Register Field Descriptions
BitFieldTypeResetDescription
31AER/W0hAddress Enable
When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
0h = Address is ignored : 0x0
1h = Address is enabled : 0x1
30SAR/W0hSource Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received packet.
0h = Compare with Destination Address : 0x0
1h = Compare with Source Address : 0x1
29-24MBCR/W0hMask Byte Control
These bits are mask control bits for comparing each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
- Bit 29: Register 194[15:8]
- Bit 28: Register 194[7:0]
- Bit 27: Register 195[31:24]
- ..
- Bit 24: Register 195[7:0]
You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.
23-17RESERVEDR0hReserved.
16DCSR/W0hDMA Channel Select
This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#) content is routed.
15-0ADDRHIR/WFFFFhMAC Address1 [47:32]
This field contains the upper 16 bits[47:32] of the second 6-byte MAC address.

43.7.3.53 MAC_Address7_Low Register (Offset = 33Ch) [Reset = FFFFFFFFh]

MAC_Address7_Low is shown in Figure 43-92 and described in Table 43-146.

Return to the Summary Table.

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.

Figure 43-92 MAC_Address7_Low Register
313029282726252423222120191817161514131211109876543210
ADDRLO
R/W-FFFFFFFFh
Table 43-146 MAC_Address7_Low Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRLOR/WFFFFFFFFhMAC Address1 [31:0]
This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process.

43.7.3.54 MMC_Control Register (Offset = 700h) [Reset = 0h]

MMC_Control is shown in Figure 43-93 and described in Table 43-147.

Return to the Summary Table.

This register establishes the operating mode of MMC.

Figure 43-93 MMC_Control Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUCDBC
R-0hR/W-0h
76543210
RESERVEDCNTPRSTLVLCNTPRSTCNTFREEZRSTONRDCNTSTOPROCNTRST
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-147 MMC_Control Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved.
8UCDBCR/W0hUpdate MMC Counters for Dropped Broadcast Packets
Note: The CNTRST bit has a higher priority than the CNTPRST bit. Therefore, when the software tries to set both bits in the same write cycle, all counters are cleared and the CNTPRST bit is not set.
When set, the MAC updates all related MMC Counters for Broadcast packets that are dropped because of the setting of the DBF bit of MAC_Packet_Filter register.
When reset, the MMC Counters are not updated for dropped Broadcast packets.

0h = Update MMC Counters for Dropped Broadcast Packets is disabled : 0x0
1h = Update MMC Counters for Dropped Broadcast Packets is enabled : 0x1
7-6RESERVEDR0hReserved.
5CNTPRSTLVLR/W0hFull-Half Preset
When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2KBytes) and all packet-counters gets preset to 0x7FFF_FFF0 (Half 16).
When this bit is high and the CNTPRST bit is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (Full 2KBytes) and all packet-counters gets preset to 0xFFFF_FFF0 (Full 16).
For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and packet counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0.

0h = Full-Half Preset is disabled : 0x0
1h = Full-Half Preset is enabled : 0x1
4CNTPRSTR/W0hCounters Preset
When this bit is set, all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle.
This bit, along with the CNTPRSTLVL bit, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full.
Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

0h = Counters Preset is disabled : 0x0
1h = Counters Preset is enabled : 0x1
3CNTFREEZR/W0hMMC Counter Freeze
When this bit is set, it freezes all MMC counters to their current value.
Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode.

0h = MMC Counter Freeze is disabled : 0x0
1h = MMC Counter Freeze is enabled : 0x1
2RSTONRDR/W0hReset on Read
When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read.

0h = Reset on Read is disabled : 0x0
1h = Reset on Read is enabled : 0x1
1CNTSTOPROR/W0hCounter Stop Rollover
When this bit is set, the counter does not roll over to zero after reaching the maximum value.

0h = Counter Stop Rollover is disabled : 0x0
1h = Counter Stop Rollover is enabled : 0x1
0CNTRSTR/W0hCounters Reset
When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.
Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.

0h = Counters are not reset : 0x0
1h = All counters are reset : 0x1

43.7.3.55 MMC_Rx_Interrupt Register (Offset = 704h) [Reset = 0h]

MMC_Rx_Interrupt is shown in Figure 43-94 and described in Table 43-148.

Return to the Summary Table.

This register maintains the interrupts generated from all Receive statistics counters.
The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur:
- Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter).
- Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter).
When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register
is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.
Note: R_SS_RC means that this register bit is set internally, and it is cleared when the Counter register is read.

Figure 43-94 MMC_Rx_Interrupt Register
3130292827262524
RESERVEDRXLPITRCISRXLPIUSCISRXCTRLPISRXRCVERRPIS
R-0hR-0hR-0hR-0hR-0h
2322212019181716
RXWDOGPISRXVLANGBPISRXFOVPISRXPAUSPISRXORANGEPISRXLENERPISRXUCGPISRX1024TMAXOCTGBPIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RX512T1023OCTGBPISRX256T511OCTGBPISRX128T255OCTGBPISRX65T127OCTGBPISRX64OCTGBPISRXOSIZEGPISRXUSIZEGPISRXJABERPIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RXRUNTPISRXALGNERPISRXCRCERPISRXMCGPISRXBCGPISRXGOCTISRXGBOCTISRXGBPKTIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-148 MMC_Rx_Interrupt Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27RXLPITRCISR0hMMC Receive LPI transition counter interrupt status
This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive LPI transition Counter Interrupt Status not detected : 0x0
1h = MMC Receive LPI transition Counter Interrupt Status detected : 0x1
26RXLPIUSCISR0hMMC Receive LPI microsecond counter interrupt status
This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive LPI microsecond Counter Interrupt Status not detected : 0x0
1h = MMC Receive LPI microsecond Counter Interrupt Status detected : 0x1
25RXCTRLPISR0hMMC Receive Control Packet Counter Interrupt Status
This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Control Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Control Packet Counter Interrupt Status detected : 0x1
24RXRCVERRPISR0hMMC Receive Error Packet Counter Interrupt Status
This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Error Packet Counter Interrupt Status detected : 0x1
23RXWDOGPISR0hMMC Receive Watchdog Error Packet Counter Interrupt Status
This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Watchdog Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Watchdog Error Packet Counter Interrupt Status detected : 0x1
22RXVLANGBPISR0hMMC Receive VLAN Good Bad Packet Counter Interrupt Status
This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected : 0x1
21RXFOVPISR0hMMC Receive FIFO Overflow Packet Counter Interrupt Status
This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive FIFO Overflow Packet Counter Interrupt Status detected : 0x1
20RXPAUSPISR0hMMC Receive Pause Packet Counter Interrupt Status
This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Pause Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Pause Packet Counter Interrupt Status detected : 0x1
19RXORANGEPISR0hMMC Receive Out Of Range Error Packet Counter Interrupt Status.
This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Out Of Range Error Packet Counter Interrupt Status detected : 0x1
18RXLENERPISR0hMMC Receive Length Error Packet Counter Interrupt Status
This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Length Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Length Error Packet Counter Interrupt Status detected : 0x1
17RXUCGPISR0hMMC Receive Unicast Good Packet Counter Interrupt Status
This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Unicast Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Unicast Good Packet Counter Interrupt Status detected : 0x1
16RX1024TMAXOCTGBPISR0hMMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected : 0x1
15RX512T1023OCTGBPISR0hMMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
14RX256T511OCTGBPISR0hMMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
13RX128T255OCTGBPISR0hMMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
12RX65T127OCTGBPISR0hMMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
11RX64OCTGBPISR0hMMC Receive 64 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
10RXOSIZEGPISR0hMMC Receive Oversize Good Packet Counter Interrupt Status
This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Oversize Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Oversize Good Packet Counter Interrupt Status detected : 0x1
9RXUSIZEGPISR0hMMC Receive Undersize Good Packet Counter Interrupt Status
This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Undersize Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Undersize Good Packet Counter Interrupt Status detected : 0x1
8RXJABERPISR0hMMC Receive Jabber Error Packet Counter Interrupt Status
This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Jabber Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Jabber Error Packet Counter Interrupt Status detected : 0x1
7RXRUNTPISR0hMMC Receive Runt Packet Counter Interrupt Status
This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Runt Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Runt Packet Counter Interrupt Status detected : 0x1
6RXALGNERPISR0hMMC Receive Alignment Error Packet Counter Interrupt Status
This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Alignment Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Alignment Error Packet Counter Interrupt Status detected : 0x1
5RXCRCERPISR0hMMC Receive CRC Error Packet Counter Interrupt Status
This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive CRC Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive CRC Error Packet Counter Interrupt Status detected : 0x1
4RXMCGPISR0hMMC Receive Multicast Good Packet Counter Interrupt Status
This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Multicast Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Multicast Good Packet Counter Interrupt Status detected : 0x1
3RXBCGPISR0hMMC Receive Broadcast Good Packet Counter Interrupt Status
This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Broadcast Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Broadcast Good Packet Counter Interrupt Status detected : 0x1
2RXGOCTISR0hMMC Receive Good Octet Counter Interrupt Status
This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Good Octet Counter Interrupt Status detected : 0x1
1RXGBOCTISR0hMMC Receive Good Bad Octet Counter Interrupt Status
This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Good Bad Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Good Bad Octet Counter Interrupt Status detected : 0x1
0RXGBPKTISR0hMMC Receive Good Bad Packet Counter Interrupt Status
This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive Good Bad Packet Counter Interrupt Status detected : 0x1

43.7.3.56 MMC_Tx_Interrupt Register (Offset = 708h) [Reset = 0h]

MMC_Tx_Interrupt is shown in Figure 43-95 and described in Table 43-149.

Return to the Summary Table.

This register maintains the interrupts generated from all Transmit statistics counters.
The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values
(0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter).
When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones.
The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read.
The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.

Figure 43-95 MMC_Tx_Interrupt Register
3130292827262524
RESERVEDTXLPITRCISTXLPIUSCISTXOSIZEGPISTXVLANGPIS
R-0hR-0hR-0hR-0hR-0h
2322212019181716
TXPAUSPISTXEXDEFPISTXGPKTISTXGOCTISTXCARERPISTXEXCOLPISTXLATCOLPISTXDEFPIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TXMCOLGPISTXSCOLGPISTXUFLOWERPISTXBCGBPISTXMCGBPISTXUCGBPISTX1024TMAXOCTGBPISTX512T1023OCTGBPIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TX256T511OCTGBPISTX128T255OCTGBPISTX65T127OCTGBPISTX64OCTGBPISTXMCGPISTXBCGPISTXGBPKTISTXGBOCTIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-149 MMC_Tx_Interrupt Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27TXLPITRCISR0hMMC Transmit LPI transition counter interrupt status
This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit LPI transition Counter Interrupt Status not detected : 0x0
1h = MMC Transmit LPI transition Counter Interrupt Status detected : 0x1
26TXLPIUSCISR0hMMC Transmit LPI microsecond counter interrupt status
This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit LPI microsecond Counter Interrupt Status not detected : 0x0
1h = MMC Transmit LPI microsecond Counter Interrupt Status detected : 0x1
25TXOSIZEGPISR0hMMC Transmit Oversize Good Packet Counter Interrupt Status
This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Oversize Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Oversize Good Packet Counter Interrupt Status detected : 0x1
24TXVLANGPISR0hMMC Transmit VLAN Good Packet Counter Interrupt Status
This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit VLAN Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit VLAN Good Packet Counter Interrupt Status detected : 0x1
23TXPAUSPISR0hMMC Transmit Pause Packet Counter Interrupt Status
This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Pause Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Pause Packet Counter Interrupt Status detected : 0x1
22TXEXDEFPISR0hMMC Transmit Excessive Deferral Packet Counter Interrupt Status
This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected : 0x1
21TXGPKTISR0hMMC Transmit Good Packet Counter Interrupt Status
This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Good Packet Counter Interrupt Status detected : 0x1
20TXGOCTISR0hMMC Transmit Good Octet Counter Interrupt Status
This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Good Octet Counter Interrupt Status detected : 0x1
19TXCARERPISR0hMMC Transmit Carrier Error Packet Counter Interrupt Status
This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Carrier Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Carrier Error Packet Counter Interrupt Status detected : 0x1
18TXEXCOLPISR0hMMC Transmit Excessive Collision Packet Counter Interrupt Status
This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Excessive Collision Packet Counter Interrupt Status detected : 0x1
17TXLATCOLPISR0hMMC Transmit Late Collision Packet Counter Interrupt Status
This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Late Collision Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Late Collision Packet Counter Interrupt Status detected : 0x1
16TXDEFPISR0hMMC Transmit Deferred Packet Counter Interrupt Status
This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Deferred Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Deferred Packet Counter Interrupt Status detected : 0x1
15TXMCOLGPISR0hMMC Transmit Multiple Collision Good Packet Counter Interrupt Status
This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected : 0x1
14TXSCOLGPISR0hMMC Transmit Single Collision Good Packet Counter Interrupt Status
This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Single Collision Good Packet Counter Interrupt Status detected : 0x1
13TXUFLOWERPISR0hMMC Transmit Underflow Error Packet Counter Interrupt Status
This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Underflow Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Underflow Error Packet Counter Interrupt Status detected : 0x1
12TXBCGBPISR0hMMC Transmit Broadcast Good Bad Packet Counter Interrupt Status
This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected : 0x1
11TXMCGBPISR0hMMC Transmit Multicast Good Bad Packet Counter Interrupt Status
The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected : 0x1
10TXUCGBPISR0hMMC Transmit Unicast Good Bad Packet Counter Interrupt Status
This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected : 0x1
9TX1024TMAXOCTGBPISR0hMMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected : 0x1
8TX512T1023OCTGBPISR0hMMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
7TX256T511OCTGBPISR0hMMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
6TX128T255OCTGBPISR0hMMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
5TX65T127OCTGBPISR0hMMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
4TX64OCTGBPISR0hMMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status
This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected : 0x1
3TXMCGPISR0hMMC Transmit Multicast Good Packet Counter Interrupt Status
This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Multicast Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Multicast Good Packet Counter Interrupt Status detected : 0x1
2TXBCGPISR0hMMC Transmit Broadcast Good Packet Counter Interrupt Status
This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Broadcast Good Packet Counter Interrupt Status detected : 0x1
1TXGBPKTISR0hMMC Transmit Good Bad Packet Counter Interrupt Status
This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Good Bad Packet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Good Bad Packet Counter Interrupt Status detected : 0x1
0TXGBOCTISR0hMMC Transmit Good Bad Octet Counter Interrupt Status
This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Transmit Good Bad Octet Counter Interrupt Status not detected : 0x0
1h = MMC Transmit Good Bad Octet Counter Interrupt Status detected : 0x1

43.7.3.57 MMC_Rx_Interrupt_Mask Register (Offset = 70Ch) [Reset = 0h]

MMC_Rx_Interrupt_Mask is shown in Figure 43-96 and described in Table 43-150.

Return to the Summary Table.

This register maintains the masks for interrupts generated from all Receive statistics counters.
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values.
This register is 32 bit wide.

Figure 43-96 MMC_Rx_Interrupt_Mask Register
3130292827262524
RESERVEDRXLPITRCIMRXLPIUSCIMRXCTRLPIMRXRCVERRPIM
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RXWDOGPIMRXVLANGBPIMRXFOVPIMRXPAUSPIMRXORANGEPIMRXLENERPIMRXUCGPIMRX1024TMAXOCTGBPIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RX512T1023OCTGBPIMRX256T511OCTGBPIMRX128T255OCTGBPIMRX65T127OCTGBPIMRX64OCTGBPIMRXOSIZEGPIMRXUSIZEGPIMRXJABERPIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RXRUNTPIMRXALGNERPIMRXCRCERPIMRXMCGPIMRXBCGPIMRXGOCTIMRXGBOCTIMRXGBPKTIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-150 MMC_Rx_Interrupt_Mask Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27RXLPITRCIMR/W0hMMC Receive LPI transition counter interrupt Mask
Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.

0h = MMC Receive LPI transition counter interrupt Mask is disabled : 0x0
1h = MMC Receive LPI transition counter interrupt Mask is enabled : 0x1
26RXLPIUSCIMR/W0hMMC Receive LPI microsecond counter interrupt Mask
Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.

0h = MMC Receive LPI microsecond counter interrupt Mask is disabled : 0x0
1h = MMC Receive LPI microsecond counter interrupt Mask is enabled : 0x1
25RXCTRLPIMR/W0hMMC Receive Control Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Control Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Control Packet Counter Interrupt Mask is enabled : 0x1
24RXRCVERRPIMR/W0hMMC Receive Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Error Packet Counter Interrupt Mask is enabled : 0x1
23RXWDOGPIMR/W0hMMC Receive Watchdog Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled : 0x1
22RXVLANGBPIMR/W0hMMC Receive VLAN Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled : 0x1
21RXFOVPIMR/W0hMMC Receive FIFO Overflow Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.

0h = MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled : 0x1
20RXPAUSPIMR/W0hMMC Receive Pause Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Pause Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Pause Packet Counter Interrupt Mask is enabled : 0x1
19RXORANGEPIMR/W0hMMC Receive Out Of Range Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled : 0x1
18RXLENERPIMR/W0hMMC Receive Length Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Length Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Length Error Packet Counter Interrupt Mask is enabled : 0x1
17RXUCGPIMR/W0hMMC Receive Unicast Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled : 0x1
16RX1024TMAXOCTGBPIMR/W0hMMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
15RX512T1023OCTGBPIMR/W0hMMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
14RX256T511OCTGBPIMR/W0hMMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
13RX128T255OCTGBPIMR/W0hMMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
12RX65T127OCTGBPIMR/W0hMMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
11RX64OCTGBPIMR/W0hMMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
10RXOSIZEGPIMR/W0hMMC Receive Oversize Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled : 0x1
9RXUSIZEGPIMR/W0hMMC Receive Undersize Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled : 0x1
8RXJABERPIMR/W0hMMC Receive Jabber Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled : 0x1
7RXRUNTPIMR/W0hMMC Receive Runt Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Runt Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Runt Packet Counter Interrupt Mask is enabled : 0x1
6RXALGNERPIMR/W0hMMC Receive Alignment Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled : 0x1
5RXCRCERPIMR/W0hMMC Receive CRC Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.

0h = MMC Receive CRC Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive CRC Error Packet Counter Interrupt Mask is enabled : 0x1
4RXMCGPIMR/W0hMMC Receive Multicast Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled : 0x1
3RXBCGPIMR/W0hMMC Receive Broadcast Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled : 0x1
2RXGOCTIMR/W0hMMC Receive Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Good Octet Counter Interrupt Mask is enabled : 0x1
1RXGBOCTIMR/W0hMMC Receive Good Bad Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Good Bad Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Good Bad Octet Counter Interrupt Mask is enabled : 0x1
0RXGBPKTIMR/W0hMMC Receive Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.

0h = MMC Receive Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive Good Bad Packet Counter Interrupt Mask is enabled : 0x1

43.7.3.58 MMC_Tx_Interrupt_Mask Register (Offset = 710h) [Reset = 0h]

MMC_Tx_Interrupt_Mask is shown in Figure 43-97 and described in Table 43-151.

Return to the Summary Table.

This register maintains the masks for interrupts generated from all Transmit statistics counters.
The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide.

Figure 43-97 MMC_Tx_Interrupt_Mask Register
3130292827262524
RESERVEDTXLPITRCIMTXLPIUSCIMTXOSIZEGPIMTXVLANGPIM
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TXPAUSPIMTXEXDEFPIMTXGPKTIMTXGOCTIMTXCARERPIMTXEXCOLPIMTXLATCOLPIMTXDEFPIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TXMCOLGPIMTXSCOLGPIMTXUFLOWERPIMTXBCGBPIMTXMCGBPIMTXUCGBPIMTX1024TMAXOCTGBPIMTX512T1023OCTGBPIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TX256T511OCTGBPIMTX128T255OCTGBPIMTX65T127OCTGBPIMTX64OCTGBPIMTXMCGPIMTXBCGPIMTXGBPKTIMTXGBOCTIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-151 MMC_Tx_Interrupt_Mask Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27TXLPITRCIMR/W0hMMC Transmit LPI transition counter interrupt Mask
Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit LPI transition counter interrupt Mask is disabled : 0x0
1h = MMC Transmit LPI transition counter interrupt Mask is enabled : 0x1
26TXLPIUSCIMR/W0hMMC Transmit LPI microsecond counter interrupt Mask
Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit LPI microsecond counter interrupt Mask is disabled : 0x0
1h = MMC Transmit LPI microsecond counter interrupt Mask is enabled : 0x1
25TXOSIZEGPIMR/W0hMMC Transmit Oversize Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled : 0x1
24TXVLANGPIMR/W0hMMC Transmit VLAN Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled : 0x1
23TXPAUSPIMR/W0hMMC Transmit Pause Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Pause Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Pause Packet Counter Interrupt Mask is enabled : 0x1
22TXEXDEFPIMR/W0hMMC Transmit Excessive Deferral Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled : 0x1
21TXGPKTIMR/W0hMMC Transmit Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Good Packet Counter Interrupt Mask is enabled : 0x1
20TXGOCTIMR/W0hMMC Transmit Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Good Octet Counter Interrupt Mask is enabled : 0x1
19TXCARERPIMR/W0hMMC Transmit Carrier Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled : 0x1
18TXEXCOLPIMR/W0hMMC Transmit Excessive Collision Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled : 0x1
17TXLATCOLPIMR/W0hMMC Transmit Late Collision Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled : 0x1
16TXDEFPIMR/W0hMMC Transmit Deferred Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Deferred Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Deferred Packet Counter Interrupt Mask is enabled : 0x1
15TXMCOLGPIMR/W0hMMC Transmit Multiple Collision Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled : 0x1
14TXSCOLGPIMR/W0hMMC Transmit Single Collision Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled : 0x1
13TXUFLOWERPIMR/W0hMMC Transmit Underflow Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled : 0x1
12TXBCGBPIMR/W0hMMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled : 0x1
11TXMCGBPIMR/W0hMMC Transmit Multicast Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled : 0x1
10TXUCGBPIMR/W0hMMC Transmit Unicast Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled : 0x1
9TX1024TMAXOCTGBPIMR/W0hMMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
8TX512T1023OCTGBPIMR/W0hMMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
7TX256T511OCTGBPIMR/W0hMMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
6TX128T255OCTGBPIMR/W0hMMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
5TX65T127OCTGBPIMR/W0hMMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
4TX64OCTGBPIMR/W0hMMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled : 0x1
3TXMCGPIMR/W0hMMC Transmit Multicast Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled : 0x1
2TXBCGPIMR/W0hMMC Transmit Broadcast Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled : 0x1
1TXGBPKTIMR/W0hMMC Transmit Good Bad Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled : 0x1
0TXGBOCTIMR/W0hMMC Transmit Good Bad Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.


0h = MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled : 0x1

43.7.3.59 Tx_Octet_Count_Good_Bad Register (Offset = 714h) [Reset = 0h]

Tx_Octet_Count_Good_Bad is shown in Figure 43-98 and described in Table 43-152.

Return to the Summary Table.

This register provides the number of bytes transmitted by the DWC_ether_qos, exclusive of preamble and retried bytes, in good and bad packets.

Figure 43-98 Tx_Octet_Count_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TXOCTGB
R-0h
Table 43-152 Tx_Octet_Count_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TXOCTGBR0hTx Octet Count Good Bad
This field indicates the number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad packets.

43.7.3.60 Tx_Packet_Count_Good_Bad Register (Offset = 718h) [Reset = 0h]

Tx_Packet_Count_Good_Bad is shown in Figure 43-99 and described in Table 43-153.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos, exclusive of retried packets.

Figure 43-99 Tx_Packet_Count_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TXPKTGB
R-0h
Table 43-153 Tx_Packet_Count_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TXPKTGBR0hTx Packet Count Good Bad
This field indicates the number of good and bad packets transmitted, exclusive of retried packets.

43.7.3.61 Tx_Broadcast_Packets_Good Register (Offset = 71Ch) [Reset = 0h]

Tx_Broadcast_Packets_Good is shown in Figure 43-100 and described in Table 43-154.

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This register provides the number of good broadcast packets transmitted by DWC_ether_qos.

Figure 43-100 Tx_Broadcast_Packets_Good Register
313029282726252423222120191817161514131211109876543210
TXBCASTG
R-0h
Table 43-154 Tx_Broadcast_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0TXBCASTGR0hTx Broadcast Packets Good
This field indicates the number of good broadcast packets transmitted.

43.7.3.62 Tx_Multicast_Packets_Good Register (Offset = 720h) [Reset = 0h]

Tx_Multicast_Packets_Good is shown in Figure 43-101 and described in Table 43-155.

Return to the Summary Table.

This register provides the number of good multicast packets transmitted by DWC_ether_qos.

Figure 43-101 Tx_Multicast_Packets_Good Register
313029282726252423222120191817161514131211109876543210
TXMCASTG
R-0h
Table 43-155 Tx_Multicast_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0TXMCASTGR0hTx Multicast Packets Good
This field indicates the number of good multicast packets transmitted.

43.7.3.63 Tx_64Octets_Packets_Good_Bad Register (Offset = 724h) [Reset = 0h]

Tx_64Octets_Packets_Good_Bad is shown in Figure 43-102 and described in Table 43-156.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes, exclusive of preamble and retried packets.

Figure 43-102 Tx_64Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TX64OCTGB
R-0h
Table 43-156 Tx_64Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TX64OCTGBR0hTx 64Octets Packets Good_Bad
This field indicates the number of good and bad packets transmitted with length 64 bytes, exclusive of preamble and retried packets.

43.7.3.64 Tx_65To127Octets_Packets_Good_Bad Register (Offset = 728h) [Reset = 0h]

Tx_65To127Octets_Packets_Good_Bad is shown in Figure 43-103 and described in Table 43-157.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried packets.

Figure 43-103 Tx_65To127Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TX65_127OCTGB
R-0h
Table 43-157 Tx_65To127Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TX65_127OCTGBR0hTx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried packets.

43.7.3.65 Tx_128To255Octets_Packets_Good_Bad Register (Offset = 72Ch) [Reset = 0h]

Tx_128To255Octets_Packets_Good_Bad is shown in Figure 43-104 and described in Table 43-158.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes, exclusive of preamble and retried packets.

Figure 43-104 Tx_128To255Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TX128_255OCTGB
R-0h
Table 43-158 Tx_128To255Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TX128_255OCTGBR0hTx 128To255Octets Packets Good Bad
This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried packets.

43.7.3.66 Tx_256To511Octets_Packets_Good_Bad Register (Offset = 730h) [Reset = 0h]

Tx_256To511Octets_Packets_Good_Bad is shown in Figure 43-105 and described in Table 43-159.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes, exclusive of preamble and retried packets.

Figure 43-105 Tx_256To511Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TX256_511OCTGB
R-0h
Table 43-159 Tx_256To511Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TX256_511OCTGBR0hTx 256To511Octets Packets Good Bad
This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried packets.

43.7.3.67 Tx_512To1023Octets_Packets_Good_Bad Register (Offset = 734h) [Reset = 0h]

Tx_512To1023Octets_Packets_Good_Bad is shown in Figure 43-106 and described in Table 43-160.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes, exclusive of preamble and retried packets.

Figure 43-106 Tx_512To1023Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TX512_1023OCTGB
R-0h
Table 43-160 Tx_512To1023Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TX512_1023OCTGBR0hTx 512To1023Octets Packets Good Bad
This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of preamble and retried packets.

43.7.3.68 Tx_1024ToMaxOctets_Packets_Good_Bad Register (Offset = 738h) [Reset = 0h]

Tx_1024ToMaxOctets_Packets_Good_Bad is shown in Figure 43-107 and described in Table 43-161.

Return to the Summary Table.

This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes, exclusive of preamble and retried packets.

Figure 43-107 Tx_1024ToMaxOctets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TX1024_MAXOCTGB
R-0h
Table 43-161 Tx_1024ToMaxOctets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TX1024_MAXOCTGBR0hTx 1024ToMaxOctets Packets Good Bad
This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of preamble and retried packets.

43.7.3.69 Tx_Unicast_Packets_Good_Bad Register (Offset = 73Ch) [Reset = 0h]

Tx_Unicast_Packets_Good_Bad is shown in Figure 43-108 and described in Table 43-162.

Return to the Summary Table.

This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos.

Figure 43-108 Tx_Unicast_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TXUCASTGB
R-0h
Table 43-162 Tx_Unicast_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TXUCASTGBR0hTx Unicast Packets Good Bad
This field indicates the number of good and bad unicast packets transmitted.

43.7.3.70 Tx_Multicast_Packets_Good_Bad Register (Offset = 740h) [Reset = 0h]

Tx_Multicast_Packets_Good_Bad is shown in Figure 43-109 and described in Table 43-163.

Return to the Summary Table.

This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos.

Figure 43-109 Tx_Multicast_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TXMCASTGB
R-0h
Table 43-163 Tx_Multicast_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TXMCASTGBR0hTx Multicast Packets Good Bad
This field indicates the number of good and bad multicast packets transmitted.

43.7.3.71 Tx_Broadcast_Packets_Good_Bad Register (Offset = 744h) [Reset = 0h]

Tx_Broadcast_Packets_Good_Bad is shown in Figure 43-110 and described in Table 43-164.

Return to the Summary Table.

This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos.

Figure 43-110 Tx_Broadcast_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
TXBCASTGB
R-0h
Table 43-164 Tx_Broadcast_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0TXBCASTGBR0hTx Broadcast Packets Good Bad
This field indicates the number of good and bad broadcast packets transmitted.

43.7.3.72 Tx_Underflow_Error_Packets Register (Offset = 748h) [Reset = 0h]

Tx_Underflow_Error_Packets is shown in Figure 43-111 and described in Table 43-165.

Return to the Summary Table.

This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error.

Figure 43-111 Tx_Underflow_Error_Packets Register
313029282726252423222120191817161514131211109876543210
TXUNDRFLW
R-0h
Table 43-165 Tx_Underflow_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXUNDRFLWR0hTx Underflow Error Packets
This field indicates the number of packets aborted because of packets underflow error.

43.7.3.73 Tx_Single_Collision_Good_Packets Register (Offset = 74Ch) [Reset = 0h]

Tx_Single_Collision_Good_Packets is shown in Figure 43-112 and described in Table 43-166.

Return to the Summary Table.

This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode.

Figure 43-112 Tx_Single_Collision_Good_Packets Register
313029282726252423222120191817161514131211109876543210
TXSNGLCOLG
R-0h
Table 43-166 Tx_Single_Collision_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXSNGLCOLGR0hTx Single Collision Good Packets
This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode.

43.7.3.74 Tx_Multiple_Collision_Good_Packets Register (Offset = 750h) [Reset = 0h]

Tx_Multiple_Collision_Good_Packets is shown in Figure 43-113 and described in Table 43-167.

Return to the Summary Table.

This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode.

Figure 43-113 Tx_Multiple_Collision_Good_Packets Register
313029282726252423222120191817161514131211109876543210
TXMULTCOLG
R-0h
Table 43-167 Tx_Multiple_Collision_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXMULTCOLGR0hTx Multiple Collision Good Packets
This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode.

43.7.3.75 Tx_Deferred_Packets Register (Offset = 754h) [Reset = 0h]

Tx_Deferred_Packets is shown in Figure 43-114 and described in Table 43-168.

Return to the Summary Table.

This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode.

Figure 43-114 Tx_Deferred_Packets Register
313029282726252423222120191817161514131211109876543210
TXDEFRD
R-0h
Table 43-168 Tx_Deferred_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXDEFRDR0hTx Deferred Packets
This field indicates the number of successfully transmitted after a deferral in the half-duplex mode.

43.7.3.76 Tx_Late_Collision_Packets Register (Offset = 758h) [Reset = 0h]

Tx_Late_Collision_Packets is shown in Figure 43-115 and described in Table 43-169.

Return to the Summary Table.

This register provides the number of packets aborted by DWC_ether_qos because of late collision error.

Figure 43-115 Tx_Late_Collision_Packets Register
313029282726252423222120191817161514131211109876543210
TXLATECOL
R-0h
Table 43-169 Tx_Late_Collision_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXLATECOLR0hTx Late Collision Packets
This field indicates the number of packets aborted because of late collision error.

43.7.3.77 Tx_Excessive_Collision_Packets Register (Offset = 75Ch) [Reset = 0h]

Tx_Excessive_Collision_Packets is shown in Figure 43-116 and described in Table 43-170.

Return to the Summary Table.

This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors.

Figure 43-116 Tx_Excessive_Collision_Packets Register
313029282726252423222120191817161514131211109876543210
TXEXSCOL
R-0h
Table 43-170 Tx_Excessive_Collision_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXEXSCOLR0hTx Excessive Collision Packets
This field indicates the number of packets aborted because of excessive (16) collision errors.

43.7.3.78 Tx_Carrier_Error_Packets Register (Offset = 760h) [Reset = 0h]

Tx_Carrier_Error_Packets is shown in Figure 43-117 and described in Table 43-171.

Return to the Summary Table.

This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier).

Figure 43-117 Tx_Carrier_Error_Packets Register
313029282726252423222120191817161514131211109876543210
TXCARR
R-0h
Table 43-171 Tx_Carrier_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXCARRR0hTx Carrier Error Packets
This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier).

43.7.3.79 Tx_Octet_Count_Good Register (Offset = 764h) [Reset = 0h]

Tx_Octet_Count_Good is shown in Figure 43-118 and described in Table 43-172.

Return to the Summary Table.

This register provides the number of bytes transmitted by DWC_ether_qos, exclusive of preamble, only in good packets.

Figure 43-118 Tx_Octet_Count_Good Register
313029282726252423222120191817161514131211109876543210
TXOCTG
R-0h
Table 43-172 Tx_Octet_Count_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0TXOCTGR0hTx Octet Count Good
This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets.

43.7.3.80 Tx_Packet_Count_Good Register (Offset = 768h) [Reset = 0h]

Tx_Packet_Count_Good is shown in Figure 43-119 and described in Table 43-173.

Return to the Summary Table.

This register provides the number of good packets transmitted by DWC_ether_qos.

Figure 43-119 Tx_Packet_Count_Good Register
313029282726252423222120191817161514131211109876543210
TXPKTG
R-0h
Table 43-173 Tx_Packet_Count_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0TXPKTGR0hTx Packet Count Good
This field indicates the number of good packets transmitted.

43.7.3.81 Tx_Excessive_Deferral_Error Register (Offset = 76Ch) [Reset = 0h]

Tx_Excessive_Deferral_Error is shown in Figure 43-120 and described in Table 43-174.

Return to the Summary Table.

This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times).

Figure 43-120 Tx_Excessive_Deferral_Error Register
313029282726252423222120191817161514131211109876543210
TXEXSDEF
R-0h
Table 43-174 Tx_Excessive_Deferral_Error Register Field Descriptions
BitFieldTypeResetDescription
31-0TXEXSDEFR0hTx Excessive Deferral Error
This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times).

43.7.3.82 Tx_Pause_Packets Register (Offset = 770h) [Reset = 0h]

Tx_Pause_Packets is shown in Figure 43-121 and described in Table 43-175.

Return to the Summary Table.

This register provides the number of good Pause packets transmitted by DWC_ether_qos.

Figure 43-121 Tx_Pause_Packets Register
313029282726252423222120191817161514131211109876543210
TXPAUSE
R-0h
Table 43-175 Tx_Pause_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0TXPAUSER0hTx Pause Packets
This field indicates the number of good Pause packets transmitted.

43.7.3.83 Tx_VLAN_Packets_Good Register (Offset = 774h) [Reset = 0h]

Tx_VLAN_Packets_Good is shown in Figure 43-122 and described in Table 43-176.

Return to the Summary Table.

This register provides the number of good VLAN packets transmitted by DWC_ether_qos.

Figure 43-122 Tx_VLAN_Packets_Good Register
313029282726252423222120191817161514131211109876543210
TXVLANG
R-0h
Table 43-176 Tx_VLAN_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0TXVLANGR0hTx VLAN Packets Good
This field provides the number of good VLAN packets transmitted.

43.7.3.84 Tx_OSize_Packets_Good Register (Offset = 778h) [Reset = 0h]

Tx_OSize_Packets_Good is shown in Figure 43-123 and described in Table 43-177.

Return to the Summary Table.

This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets
2000 bytes if enabled in S2KP bit of the MAC_Configuration register).

Figure 43-123 Tx_OSize_Packets_Good Register
313029282726252423222120191817161514131211109876543210
TXOSIZG
R-0h
Table 43-177 Tx_OSize_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0TXOSIZGR0hTx OSize Packets Good
This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets
2000 bytes if enabled in S2KP bit of the MAC_Configuration register).

43.7.3.85 Rx_Packets_Count_Good_Bad Register (Offset = 780h) [Reset = 0h]

Rx_Packets_Count_Good_Bad is shown in Figure 43-124 and described in Table 43-178.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos.

Figure 43-124 Rx_Packets_Count_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RXPKTGB
R-0h
Table 43-178 Rx_Packets_Count_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RXPKTGBR0hRx Packets Count Good Bad
This field indicates the number of good and bad packets received.

43.7.3.86 Rx_Octet_Count_Good_Bad Register (Offset = 784h) [Reset = 0h]

Rx_Octet_Count_Good_Bad is shown in Figure 43-125 and described in Table 43-179.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ther_qos, exclusive of preamble, in good and bad packets.

Figure 43-125 Rx_Octet_Count_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RXOCTGB
R-0h
Table 43-179 Rx_Octet_Count_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RXOCTGBR0hRx Octet Count Good Bad
This field indicates the number of bytes received, exclusive of preamble, in good and bad packets.

43.7.3.87 Rx_Octet_Count_Good Register (Offset = 788h) [Reset = 0h]

Rx_Octet_Count_Good is shown in Figure 43-126 and described in Table 43-180.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos, exclusive of preamble, only in good packets.

Figure 43-126 Rx_Octet_Count_Good Register
313029282726252423222120191817161514131211109876543210
RXOCTG
R-0h
Table 43-180 Rx_Octet_Count_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXOCTGR0hRx Octet Count Good
This field indicates the number of bytes received, exclusive of preamble, only in good packets.

43.7.3.88 Rx_Broadcast_Packets_Good Register (Offset = 78Ch) [Reset = 0h]

Rx_Broadcast_Packets_Good is shown in Figure 43-127 and described in Table 43-181.

Return to the Summary Table.

This register provides the number of good broadcast packets received by DWC_ether_qos.

Figure 43-127 Rx_Broadcast_Packets_Good Register
313029282726252423222120191817161514131211109876543210
RXBCASTG
R-0h
Table 43-181 Rx_Broadcast_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXBCASTGR0hRx Broadcast Packets Good
This field indicates the number of good broadcast packets received.

43.7.3.89 Rx_Multicast_Packets_Good Register (Offset = 790h) [Reset = 0h]

Rx_Multicast_Packets_Good is shown in Figure 43-128 and described in Table 43-182.

Return to the Summary Table.

This register provides the number of good multicast packets received by DWC_ether_qos.

Figure 43-128 Rx_Multicast_Packets_Good Register
313029282726252423222120191817161514131211109876543210
RXMCASTG
R-0h
Table 43-182 Rx_Multicast_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXMCASTGR0hRx Multicast Packets Good
This field indicates the number of good multicast packets received.

43.7.3.90 Rx_CRC_Error_Packets Register (Offset = 794h) [Reset = 0h]

Rx_CRC_Error_Packets is shown in Figure 43-129 and described in Table 43-183.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with CRC error.

Figure 43-129 Rx_CRC_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXCRCERR
R-0h
Table 43-183 Rx_CRC_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXCRCERRR0hRx CRC Error Packets
This field indicates the number of packets received with CRC error.

43.7.3.91 Rx_Alignment_Error_Packets Register (Offset = 798h) [Reset = 0h]

Rx_Alignment_Error_Packets is shown in Figure 43-130 and described in Table 43-184.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error. It is valid only in 10/100 mode.

Figure 43-130 Rx_Alignment_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXALGNERR
R-0h
Table 43-184 Rx_Alignment_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXALGNERRR0hRx Alignment Error Packets
This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode.

43.7.3.92 Rx_Runt_Error_Packets Register (Offset = 79Ch) [Reset = 0h]

Rx_Runt_Error_Packets is shown in Figure 43-131 and described in Table 43-185.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error.

Figure 43-131 Rx_Runt_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXRUNTERR
R-0h
Table 43-185 Rx_Runt_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXRUNTERRR0hRx Runt Error Packets
This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error.

43.7.3.93 Rx_Jabber_Error_Packets Register (Offset = 7A0h) [Reset = 0h]

Rx_Jabber_Error_Packets is shown in Figure 43-132 and described in Table 43-186.

Return to the Summary Table.

This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled, packets of length greater than 9,018 bytes (9,022 bytes for VLAN tagged) are considered as giant packets.

Figure 43-132 Rx_Jabber_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXJABERR
R-0h
Table 43-186 Rx_Jabber_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXJABERRR0hRx Jabber Error Packets
This field indicates the number of giant packets received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled, packets of length greater than 9,018 bytes (9,022 bytes for VLAN tagged) are considered as giant packets.

43.7.3.94 Rx_Undersize_Packets_Good Register (Offset = 7A4h) [Reset = 0h]

Rx_Undersize_Packets_Good is shown in Figure 43-133 and described in Table 43-187.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes, without any errors.

Figure 43-133 Rx_Undersize_Packets_Good Register
313029282726252423222120191817161514131211109876543210
RXUNDERSZG
R-0h
Table 43-187 Rx_Undersize_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXUNDERSZGR0hRx Undersize Packets Good
This field indicates the number of packets received with length less than 64 bytes, without any errors.

43.7.3.95 Rx_Oversize_Packets_Good Register (Offset = 7A8h) [Reset = 0h]

Rx_Oversize_Packets_Good is shown in Figure 43-134 and described in Table 43-188.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos without errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged packets
2000 bytes if enabled in the S2KP bit of the MAC_Configuration register).

Figure 43-134 Rx_Oversize_Packets_Good Register
313029282726252423222120191817161514131211109876543210
RXOVERSZG
R-0h
Table 43-188 Rx_Oversize_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXOVERSZGR0hRx Oversize Packets Good
This field indicates the number of packets received without errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged packets
2000 bytes if enabled in the S2KP bit of the MAC_Configuration register).

43.7.3.96 Rx_64Octets_Packets_Good_Bad Register (Offset = 7ACh) [Reset = 0h]

Rx_64Octets_Packets_Good_Bad is shown in Figure 43-135 and described in Table 43-189.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes, exclusive of the preamble.

Figure 43-135 Rx_64Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RX64OCTGB
R-0h
Table 43-189 Rx_64Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RX64OCTGBR0hRx 64 Octets Packets Good Bad
This field indicates the number of good and bad packets received with length 64 bytes, exclusive of the preamble.

43.7.3.97 Rx_65To127Octets_Packets_Good_Bad Register (Offset = 7B0h) [Reset = 0h]

Rx_65To127Octets_Packets_Good_Bad is shown in Figure 43-136 and described in Table 43-190.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.

Figure 43-136 Rx_65To127Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RX65_127OCTGB
R-0h
Table 43-190 Rx_65To127Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RX65_127OCTGBR0hRx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.

43.7.3.98 Rx_128To255Octets_Packets_Good_Bad Register (Offset = 7B4h) [Reset = 0h]

Rx_128To255Octets_Packets_Good_Bad is shown in Figure 43-137 and described in Table 43-191.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes, exclusive of the preamble.

Figure 43-137 Rx_128To255Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RX128_255OCTGB
R-0h
Table 43-191 Rx_128To255Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RX128_255OCTGBR0hRx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the preamble.

43.7.3.99 Rx_256To511Octets_Packets_Good_Bad Register (Offset = 7B8h) [Reset = 0h]

Rx_256To511Octets_Packets_Good_Bad is shown in Figure 43-138 and described in Table 43-192.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes, exclusive of the preamble.

Figure 43-138 Rx_256To511Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RX256_511OCTGB
R-0h
Table 43-192 Rx_256To511Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RX256_511OCTGBR0hRx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the preamble.

43.7.3.100 Rx_512To1023Octets_Packets_Good_Bad Register (Offset = 7BCh) [Reset = 0h]

Rx_512To1023Octets_Packets_Good_Bad is shown in Figure 43-139 and described in Table 43-193.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes, exclusive of the preamble.

Figure 43-139 Rx_512To1023Octets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RX512_1023OCTGB
R-0h
Table 43-193 Rx_512To1023Octets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RX512_1023OCTGBR0hRX 512-1023 Octets Packets Good Bad
This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the preamble.

43.7.3.101 Rx_1024ToMaxOctets_Packets_Good_Bad Register (Offset = 7C0h) [Reset = 0h]

Rx_1024ToMaxOctets_Packets_Good_Bad is shown in Figure 43-140 and described in Table 43-194.

Return to the Summary Table.

This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes, exclusive of the preamble.

Figure 43-140 Rx_1024ToMaxOctets_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RX1024_MAXOCTGB
R-0h
Table 43-194 Rx_1024ToMaxOctets_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RX1024_MAXOCTGBR0hRx 1024-Max Octets Good Bad
This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the preamble.

43.7.3.102 Rx_Unicast_Packets_Good Register (Offset = 7C4h) [Reset = 0h]

Rx_Unicast_Packets_Good is shown in Figure 43-141 and described in Table 43-195.

Return to the Summary Table.

This register provides the number of good unicast packets received by DWC_ether_qos.

Figure 43-141 Rx_Unicast_Packets_Good Register
313029282726252423222120191817161514131211109876543210
RXUCASTG
R-0h
Table 43-195 Rx_Unicast_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXUCASTGR0hRx Unicast Packets Good
This field indicates the number of good unicast packets received.

43.7.3.103 Rx_Length_Error_Packets Register (Offset = 7C8h) [Reset = 0h]

Rx_Length_Error_Packets is shown in Figure 43-142 and described in Table 43-196.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size), for all packets with valid length field.

Figure 43-142 Rx_Length_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXLENERR
R-0h
Table 43-196 Rx_Length_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXLENERRR0hRx Length Error Packets
This field indicates the number of packets received with length error (Length Type field not equal to packet size), for all packets with valid length field.

43.7.3.104 Rx_Out_Of_Range_Type_Packets Register (Offset = 7CCh) [Reset = 0h]

Rx_Out_Of_Range_Type_Packets is shown in Figure 43-143 and described in Table 43-197.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).

Figure 43-143 Rx_Out_Of_Range_Type_Packets Register
313029282726252423222120191817161514131211109876543210
RXOUTOFRNG
R-0h
Table 43-197 Rx_Out_Of_Range_Type_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXOUTOFRNGR0hRx Out of Range Type Packet
This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).

43.7.3.105 Rx_Pause_Packets Register (Offset = 7D0h) [Reset = 0h]

Rx_Pause_Packets is shown in Figure 43-144 and described in Table 43-198.

Return to the Summary Table.

This register provides the number of good and valid Pause packets received by DWC_ether_qos.

Figure 43-144 Rx_Pause_Packets Register
313029282726252423222120191817161514131211109876543210
RXPAUSEPKT
R-0h
Table 43-198 Rx_Pause_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXPAUSEPKTR0hRx Pause Packets
This field indicates the number of good and valid Pause packets received.

43.7.3.106 Rx_FIFO_Overflow_Packets Register (Offset = 7D4h) [Reset = 0h]

Rx_FIFO_Overflow_Packets is shown in Figure 43-145 and described in Table 43-199.

Return to the Summary Table.

This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos.

Figure 43-145 Rx_FIFO_Overflow_Packets Register
313029282726252423222120191817161514131211109876543210
RXFIFOOVFL
R-0h
Table 43-199 Rx_FIFO_Overflow_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXFIFOOVFLR0hRx FIFO Overflow Packets
This field indicates the number of missed received packets because of FIFO overflow.

43.7.3.107 Rx_VLAN_Packets_Good_Bad Register (Offset = 7D8h) [Reset = 0h]

Rx_VLAN_Packets_Good_Bad is shown in Figure 43-146 and described in Table 43-200.

Return to the Summary Table.

This register provides the number of good and bad VLAN packets received by DWC_ether_qos.

Figure 43-146 Rx_VLAN_Packets_Good_Bad Register
313029282726252423222120191817161514131211109876543210
RXVLANPKTGB
R-0h
Table 43-200 Rx_VLAN_Packets_Good_Bad Register Field Descriptions
BitFieldTypeResetDescription
31-0RXVLANPKTGBR0hRx VLAN Packets Good Bad
This field indicates the number of good and bad VLAN packets received.

43.7.3.108 Rx_Watchdog_Error_Packets Register (Offset = 7DCh) [Reset = 0h]

Rx_Watchdog_Error_Packets is shown in Figure 43-147 and described in Table 43-201.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when JE and WD bits are reset in MAC_Configuration register), 10,240 bytes (when JE bit is set and WD bit is reset in MAC_Configuration register), 16,384 bytes (when WD bit is set in MAC_Configuration register) or the value programmed in the MAC_Watchdog_Timeout register).

Figure 43-147 Rx_Watchdog_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXWDGERR
R-0h
Table 43-201 Rx_Watchdog_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXWDGERRR0hRx Watchdog Error Packets
This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when JE and WD bits are reset in MAC_Configuration register), 10,240 bytes (when JE bit is set and WD bit is reset in MAC_Configuration register), 16,384 bytes (when WD bit is set in MAC_Configuration register) or the value programmed in the MAC_Watchdog_Timeout register).

43.7.3.109 Rx_Receive_Error_Packets Register (Offset = 7E0h) [Reset = 0h]

Rx_Receive_Error_Packets is shown in Figure 43-148 and described in Table 43-202.

Return to the Summary Table.

This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface.

Figure 43-148 Rx_Receive_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXRCVERR
R-0h
Table 43-202 Rx_Receive_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXRCVERRR0hRx Receive Error Packets
This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface.

43.7.3.110 Rx_Control_Packets_Good Register (Offset = 7E4h) [Reset = 0h]

Rx_Control_Packets_Good is shown in Figure 43-149 and described in Table 43-203.

Return to the Summary Table.

This register provides the number of good control packets received by DWC_ether_qos.

Figure 43-149 Rx_Control_Packets_Good Register
313029282726252423222120191817161514131211109876543210
RXCTRLG
R-0h
Table 43-203 Rx_Control_Packets_Good Register Field Descriptions
BitFieldTypeResetDescription
31-0RXCTRLGR0hRx Control Packets Good
This field indicates the number of good control packets received.

43.7.3.111 Tx_LPI_USEC_Cntr Register (Offset = 7ECh) [Reset = 0h]

Tx_LPI_USEC_Cntr is shown in Figure 43-150 and described in Table 43-204.

Return to the Summary Table.

This register provides the number of microseconds Tx LPI is asserted by DWC_ether_qos.

Figure 43-150 Tx_LPI_USEC_Cntr Register
313029282726252423222120191817161514131211109876543210
TXLPIUSC
R-0h
Table 43-204 Tx_LPI_USEC_Cntr Register Field Descriptions
BitFieldTypeResetDescription
31-0TXLPIUSCR0hTx LPI Microseconds Counter
This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond.

43.7.3.112 Tx_LPI_Tran_Cntr Register (Offset = 7F0h) [Reset = 0h]

Tx_LPI_Tran_Cntr is shown in Figure 43-151 and described in Table 43-205.

Return to the Summary Table.

This register provides the number of times DWC_ether_qos has entered Tx LPI.

Figure 43-151 Tx_LPI_Tran_Cntr Register
313029282726252423222120191817161514131211109876543210
TXLPITRC
R-0h
Table 43-205 Tx_LPI_Tran_Cntr Register Field Descriptions
BitFieldTypeResetDescription
31-0TXLPITRCR0hTx LPI Transition counter
This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register), the counter will increment.

43.7.3.113 Rx_LPI_USEC_Cntr Register (Offset = 7F4h) [Reset = 0h]

Rx_LPI_USEC_Cntr is shown in Figure 43-152 and described in Table 43-206.

Return to the Summary Table.

This register provides the number of microseconds Rx LPI is sampled by DWC_ether_qos.

Figure 43-152 Rx_LPI_USEC_Cntr Register
313029282726252423222120191817161514131211109876543210
RXLPIUSC
R-0h
Table 43-206 Rx_LPI_USEC_Cntr Register Field Descriptions
BitFieldTypeResetDescription
31-0RXLPIUSCR0hRx LPI Microseconds Counter
This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit, the Timer value can have an error of +/- 1 microsecond.

43.7.3.114 Rx_LPI_Tran_Cntr Register (Offset = 7F8h) [Reset = 0h]

Rx_LPI_Tran_Cntr is shown in Figure 43-153 and described in Table 43-207.

Return to the Summary Table.

This register provides the number of times DWC_ether_qos has entered Rx LPI.

Figure 43-153 Rx_LPI_Tran_Cntr Register
313029282726252423222120191817161514131211109876543210
RXLPITRC
R-0h
Table 43-207 Rx_LPI_Tran_Cntr Register Field Descriptions
BitFieldTypeResetDescription
31-0RXLPITRCR0hRx LPI Transition counter
This field indicates the number of times Rx LPI Entry has occurred.

43.7.3.115 MMC_IPC_Rx_Interrupt_Mask Register (Offset = 800h) [Reset = 0h]

MMC_IPC_Rx_Interrupt_Mask is shown in Figure 43-154 and described in Table 43-208.

Return to the Summary Table.

This register maintains the mask for the interrupt generated from the receive IPC statistic counters.
The MMC Receive Checksum Off load Interrupt Mask register maintains the masks for the interrupts generated when the receive IPC (Checksum Off load) statistic counters reach half their maximum value, and when they reach their maximum values. This register is 32 bits wide.

Figure 43-154 MMC_IPC_Rx_Interrupt_Mask Register
3130292827262524
RESERVEDRXICMPEROIMRXICMPGOIMRXTCPEROIMRXTCPGOIMRXUDPEROIMRXUDPGOIM
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RXIPV6NOPAYOIMRXIPV6HEROIMRXIPV6GOIMRXIPV4UDSBLOIMRXIPV4FRAGOIMRXIPV4NOPAYOIMRXIPV4HEROIMRXIPV4GOIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRXICMPERPIMRXICMPGPIMRXTCPERPIMRXTCPGPIMRXUDPERPIMRXUDPGPIM
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RXIPV6NOPAYPIMRXIPV6HERPIMRXIPV6GPIMRXIPV4UDSBLPIMRXIPV4FRAGPIMRXIPV4NOPAYPIMRXIPV4HERPIMRXIPV4GPIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-208 MMC_IPC_Rx_Interrupt_Mask Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved.
29RXICMPEROIMR/W0hMMC Receive ICMP Error Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled : 0x1
28RXICMPGOIMR/W0hMMC Receive ICMP Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled : 0x1
27RXTCPEROIMR/W0hMMC Receive TCP Error Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive TCP Error Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive TCP Error Octet Counter Interrupt Mask is enabled : 0x1
26RXTCPGOIMR/W0hMMC Receive TCP Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive TCP Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive TCP Good Octet Counter Interrupt Mask is enabled : 0x1
25RXUDPEROIMR/W0hMMC Receive UDP Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive UDP Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive UDP Good Octet Counter Interrupt Mask is enabled : 0x1
24RXUDPGOIMR/W0hMMC Receive IPV6 No Payload Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled : 0x1
23RXIPV6NOPAYOIMR/W0hMMC Receive IPV6 Header Error Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled : 0x1
22RXIPV6HEROIMR/W0hMMC Receive IPV6 Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled : 0x1
21RXIPV6GOIMR/W0hMMC Receive IPV6 Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled : 0x1
20RXIPV4UDSBLOIMR/W0hMMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled : 0x1
19RXIPV4FRAGOIMR/W0hMMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled : 0x1
18RXIPV4NOPAYOIMR/W0hMMC Receive IPV4 No Payload Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled : 0x1
17RXIPV4HEROIMR/W0hMMC Receive IPV4 Header Error Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled : 0x1
16RXIPV4GOIMR/W0hMMC Receive IPV4 Good Octet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled : 0x1
15-14RESERVEDR0hReserved.
13RXICMPERPIMR/W0hMMC Receive ICMP Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled : 0x1
12RXICMPGPIMR/W0hMMC Receive ICMP Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled : 0x1
11RXTCPERPIMR/W0hMMC Receive TCP Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive TCP Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive TCP Error Packet Counter Interrupt Mask is enabled : 0x1
10RXTCPGPIMR/W0hMMC Receive TCP Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive TCP Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive TCP Good Packet Counter Interrupt Mask is enabled : 0x1
9RXUDPERPIMR/W0hMMC Receive UDP Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive UDP Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive UDP Error Packet Counter Interrupt Mask is enabled : 0x1
8RXUDPGPIMR/W0hMMC Receive UDP Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive UDP Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive UDP Good Packet Counter Interrupt Mask is enabled : 0x1
7RXIPV6NOPAYPIMR/W0hMMC Receive IPV6 No Payload Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled : 0x1
6RXIPV6HERPIMR/W0hMMC Receive IPV6 Header Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled : 0x1
5RXIPV6GPIMR/W0hMMC Receive IPV6 Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled : 0x1
4RXIPV4UDSBLPIMR/W0hMMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled : 0x1
3RXIPV4FRAGPIMR/W0hMMC Receive IPV4 Fragmented Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled : 0x1
2RXIPV4NOPAYPIMR/W0hMMC Receive IPV4 No Payload Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled : 0x1
1RXIPV4HERPIMR/W0hMMC Receive IPV4 Header Error Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled : 0x1
0RXIPV4GPIMR/W0hMMC Receive IPV4 Good Packet Counter Interrupt Mask
Setting this bit masks the interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.

0h = MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled : 0x0
1h = MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled : 0x1

43.7.3.116 MMC_IPC_Rx_Interrupt Register (Offset = 808h) [Reset = 0h]

MMC_IPC_Rx_Interrupt is shown in Figure 43-155 and described in Table 43-209.

Return to the Summary Table.

This register maintains the interrupt that the receive IPC statistic counters generate.
The MMC Receive Checksum Offload Interrupt register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones.
The MMC Receive Checksum Offload Interrupt register is 32 bit wide. When the MMC IPC counter that caused the interrupt is read, its corresponding interrupt bit is cleared. The counter's least-significant byte lane (Bits[7:0]) must be read to clear the interrupt bit.

Figure 43-155 MMC_IPC_Rx_Interrupt Register
3130292827262524
RESERVEDRXICMPEROISRXICMPGOISRXTCPEROISRXTCPGOISRXUDPEROISRXUDPGOIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RXIPV6NOPAYOISRXIPV6HEROISRXIPV6GOISRXIPV4UDSBLOISRXIPV4FRAGOISRXIPV4NOPAYOISRXIPV4HEROISRXIPV4GOIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRXICMPERPISRXICMPGPISRXTCPERPISRXTCPGPISRXUDPERPISRXUDPGPIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RXIPV6NOPAYPISRXIPV6HERPISRXIPV6GPISRXIPV4UDSBLPISRXIPV4FRAGPISRXIPV4NOPAYPISRXIPV4HERPISRXIPV4GPIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-209 MMC_IPC_Rx_Interrupt Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved.
29RXICMPEROISR0hMMC Receive ICMP Error Octet Counter Interrupt Status
This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive ICMP Error Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive ICMP Error Octet Counter Interrupt Status detected : 0x1
28RXICMPGOISR0hMMC Receive ICMP Good Octet Counter Interrupt Status
This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive ICMP Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive ICMP Good Octet Counter Interrupt Status detected : 0x1
27RXTCPEROISR0hMMC Receive TCP Error Octet Counter Interrupt Status
This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive TCP Error Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive TCP Error Octet Counter Interrupt Status detected : 0x1
26RXTCPGOISR0hMMC Receive TCP Good Octet Counter Interrupt Status
This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive TCP Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive TCP Good Octet Counter Interrupt Status detected : 0x1
25RXUDPEROISR0hMMC Receive UDP Error Octet Counter Interrupt Status
This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive UDP Error Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive UDP Error Octet Counter Interrupt Status detected : 0x1
24RXUDPGOISR0hMMC Receive UDP Good Octet Counter Interrupt Status
This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive UDP Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive UDP Good Octet Counter Interrupt Status detected : 0x1
23RXIPV6NOPAYOISR0hMMC Receive IPV6 No Payload Octet Counter Interrupt Status
This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected : 0x1
22RXIPV6HEROISR0hMMC Receive IPV6 Header Error Octet Counter Interrupt Status
This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected : 0x1
21RXIPV6GOISR0hMMC Receive IPV6 Good Octet Counter Interrupt Status
This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV6 Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV6 Good Octet Counter Interrupt Status detected : 0x1
20RXIPV4UDSBLOISR0hMMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt
Status
This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected : 0x1
19RXIPV4FRAGOISR0hMMC Receive IPV4 Fragmented Octet Counter Interrupt Status
This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected : 0x1
18RXIPV4NOPAYOISR0hMMC Receive IPV4 No Payload Octet Counter Interrupt Status
This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected : 0x1
17RXIPV4HEROISR0hMMC Receive IPV4 Header Error Octet Counter Interrupt Status
This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected : 0x1
16RXIPV4GOISR0hMMC Receive IPV4 Good Octet Counter Interrupt Status
This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 Good Octet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 Good Octet Counter Interrupt Status detected : 0x1
15-14RESERVEDR0hReserved.
13RXICMPERPISR0hMMC Receive ICMP Error Packet Counter Interrupt Status
This bit is set when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive ICMP Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive ICMP Error Packet Counter Interrupt Status detected : 0x1
12RXICMPGPISR0hMMC Receive ICMP Good Packet Counter Interrupt Status
This bit is set when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive ICMP Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive ICMP Good Packet Counter Interrupt Status detected : 0x1
11RXTCPERPISR0hMMC Receive TCP Error Packet Counter Interrupt Status
This bit is set when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive TCP Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive TCP Error Packet Counter Interrupt Status detected : 0x1
10RXTCPGPISR0hMMC Receive TCP Good Packet Counter Interrupt Status
This bit is set when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive TCP Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive TCP Good Packet Counter Interrupt Status detected : 0x1
9RXUDPERPISR0hMMC Receive UDP Error Packet Counter Interrupt Status
This bit is set when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive UDP Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive UDP Error Packet Counter Interrupt Status detected : 0x1
8RXUDPGPISR0hMC Receive UDP Good Packet Counter Interrupt Status
This bit is set when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive UDP Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive UDP Good Packet Counter Interrupt Status detected : 0x1
7RXIPV6NOPAYPISR0hMMC Receive IPV6 No Payload Packet Counter Interrupt Status
This bit is set when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected : 0x1
6RXIPV6HERPISR0hMMC Receive IPV6 Header Error Packet Counter Interrupt Status
This bit is set when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected : 0x1
5RXIPV6GPISR0hMMC Receive IPV6 Good Packet Counter Interrupt Status
This bit is set when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV6 Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV6 Good Packet Counter Interrupt Status detected : 0x1
4RXIPV4UDSBLPISR0hMMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status
This bit is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value.


0h = MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected : 0x1
3RXIPV4FRAGPISR0hMMC Receive IPV4 Fragmented Packet Counter Interrupt Status
This bit is set when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected : 0x1
2RXIPV4NOPAYPISR0hMMC Receive IPV4 No Payload Packet Counter Interrupt Status
This bit is set when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected : 0x1
1RXIPV4HERPISR0hMMC Receive IPV4 Header Error Packet Counter Interrupt Status
This bit is set when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected : 0x1
0RXIPV4GPISR0hMMC Receive IPV4 Good Packet Counter Interrupt Status
This bit is set when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

0h = MMC Receive IPV4 Good Packet Counter Interrupt Status not detected : 0x0
1h = MMC Receive IPV4 Good Packet Counter Interrupt Status detected : 0x1

43.7.3.117 RxIPv4_Good_Packets Register (Offset = 810h) [Reset = 0h]

RxIPv4_Good_Packets is shown in Figure 43-156 and described in Table 43-210.

Return to the Summary Table.

This register provides the number of good IPv4 datagrams received by DWC_ether_qos with the TCP, UDP, or ICMP payload.

Figure 43-156 RxIPv4_Good_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV4GDPKT
R-0h
Table 43-210 RxIPv4_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4GDPKTR0hRxIPv4 Good Packets
This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.

43.7.3.118 RxIPv4_Header_Error_Packets Register (Offset = 814h) [Reset = 0h]

RxIPv4_Header_Error_Packets is shown in Figure 43-157 and described in Table 43-211.

Return to the Summary Table.

RxIPv4 Header Error Packets
This register provides the number of IPv4 datagrams received by DWC_ether_qos with header (checksum, length, or version mismatch) errors.

Figure 43-157 RxIPv4_Header_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV4HDRERRPKT
R-0h
Table 43-211 RxIPv4_Header_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4HDRERRPKTR0hRxIPv4 Header Error Packets
This field indicates the number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors.

43.7.3.119 RxIPv4_No_Payload_Packets Register (Offset = 818h) [Reset = 0h]

RxIPv4_No_Payload_Packets is shown in Figure 43-158 and described in Table 43-212.

Return to the Summary Table.

This register provides the number of IPv4 datagram packets received by DWC_ether_qos that did not have a TCP, UDP, or ICMP payload.

Figure 43-158 RxIPv4_No_Payload_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV4NOPAYPKT
R-0h
Table 43-212 RxIPv4_No_Payload_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4NOPAYPKTR0hRxIPv4 Payload Packets
This field indicates the number of IPv4 datagram packets received that did not have a TCP, UDP, or ICMP payload.

43.7.3.120 RxIPv4_Fragmented_Packets Register (Offset = 81Ch) [Reset = 0h]

RxIPv4_Fragmented_Packets is shown in Figure 43-159 and described in Table 43-213.

Return to the Summary Table.

This register provides the number of good IPv4 datagrams received by DWC_ether_qos with fragmentation.

Figure 43-159 RxIPv4_Fragmented_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV4FRAGPKT
R-0h
Table 43-213 RxIPv4_Fragmented_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4FRAGPKTR0hRxIPv4 Fragmented Packets
This field indicates the number of good IPv4 datagrams received with fragmentation.

43.7.3.121 RxIPv4_UDP_Checksum_Disabled_Packets Register (Offset = 820h) [Reset = 0h]

RxIPv4_UDP_Checksum_Disabled_Packets is shown in Figure 43-160 and described in Table 43-214.

Return to the Summary Table.

This register provides the number of good IPv4 datagrams received by DWC_ether_qos that had a UDP payload with checksum disabled.

Figure 43-160 RxIPv4_UDP_Checksum_Disabled_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV4UDSBLPKT
R-0h
Table 43-214 RxIPv4_UDP_Checksum_Disabled_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4UDSBLPKTR0hRxIPv4 UDP Checksum Disabled Packets
This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled.

43.7.3.122 RxIPv6_Good_Packets Register (Offset = 824h) [Reset = 0h]

RxIPv6_Good_Packets is shown in Figure 43-161 and described in Table 43-215.

Return to the Summary Table.

This register provides the number of good IPv6 datagrams received by DWC_ether_qos with the TCP, UDP, or ICMP payload.

Figure 43-161 RxIPv6_Good_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV6GDPKT
R-0h
Table 43-215 RxIPv6_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV6GDPKTR0hRxIPv6 Good Packets
This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload.

43.7.3.123 RxIPv6_Header_Error_Packets Register (Offset = 828h) [Reset = 0h]

RxIPv6_Header_Error_Packets is shown in Figure 43-162 and described in Table 43-216.

Return to the Summary Table.

This register provides the number of IPv6 datagrams received by DWC_ether_qos with header (length or version mismatch) errors.

Figure 43-162 RxIPv6_Header_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV6HDRERRPKT
R-0h
Table 43-216 RxIPv6_Header_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV6HDRERRPKTR0hRxIPv6 Header Error Packets
This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors.

43.7.3.124 RxIPv6_No_Payload_Packets Register (Offset = 82Ch) [Reset = 0h]

RxIPv6_No_Payload_Packets is shown in Figure 43-163 and described in Table 43-217.

Return to the Summary Table.

This register provides the number of IPv6 datagram packets received by DWC_ether_qos that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers.

Figure 43-163 RxIPv6_No_Payload_Packets Register
313029282726252423222120191817161514131211109876543210
RXIPV6NOPAYPKT
R-0h
Table 43-217 RxIPv6_No_Payload_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV6NOPAYPKTR0hRxIPv6 Payload Packets
This field indicates the number of IPv6 datagram packets received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers.

43.7.3.125 RxUDP_Good_Packets Register (Offset = 830h) [Reset = 0h]

RxUDP_Good_Packets is shown in Figure 43-164 and described in Table 43-218.

Return to the Summary Table.

This register provides the number of good IP datagrams received by DWC_ether_qos with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented.

Figure 43-164 RxUDP_Good_Packets Register
313029282726252423222120191817161514131211109876543210
RXUDPGDPKT
R-0h
Table 43-218 RxUDP_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXUDPGDPKTR0hRxUDP Good Packets
This field indicates the number of good IP datagrams received with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented.

43.7.3.126 RxUDP_Error_Packets Register (Offset = 834h) [Reset = 0h]

RxUDP_Error_Packets is shown in Figure 43-165 and described in Table 43-219.

Return to the Summary Table.

This register provides the number of good IP datagrams received by DWC_ether_qos whose UDP payload has a checksum error.

Figure 43-165 RxUDP_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXUDPERRPKT
R-0h
Table 43-219 RxUDP_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXUDPERRPKTR0hRxUDP Error Packets
This field indicates the number of good IP datagrams received whose UDP payload has a checksum error.

43.7.3.127 RxTCP_Good_Packets Register (Offset = 838h) [Reset = 0h]

RxTCP_Good_Packets is shown in Figure 43-166 and described in Table 43-220.

Return to the Summary Table.

This register provides the number of good IP datagrams received by DWC_ether_qos with a good TCP payload.

Figure 43-166 RxTCP_Good_Packets Register
313029282726252423222120191817161514131211109876543210
RXTCPGDPKT
R-0h
Table 43-220 RxTCP_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXTCPGDPKTR0hRxTCP Good Packets
This field indicates the number of good IP datagrams received with a good TCP payload.

43.7.3.128 RxTCP_Error_Packets Register (Offset = 83Ch) [Reset = 0h]

RxTCP_Error_Packets is shown in Figure 43-167 and described in Table 43-221.

Return to the Summary Table.

This register provides the number of good IP datagrams received by DWC_ether_qos whose TCP payload has a checksum error.

Figure 43-167 RxTCP_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXTCPERRPKT
R-0h
Table 43-221 RxTCP_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXTCPERRPKTR0hRxTCP Error Packets
This field indicates the number of good IP datagrams received whose TCP payload has a checksum error.

43.7.3.129 RxICMP_Good_Packets Register (Offset = 840h) [Reset = 0h]

RxICMP_Good_Packets is shown in Figure 43-168 and described in Table 43-222.

Return to the Summary Table.

This register provides the number of good IP datagrams received by DWC_ether_qos with a good ICMP payload.

Figure 43-168 RxICMP_Good_Packets Register
313029282726252423222120191817161514131211109876543210
RXICMPGDPKT
R-0h
Table 43-222 RxICMP_Good_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXICMPGDPKTR0hRxICMP Good Packets
This field indicates the number of good IP datagrams received with a good ICMP payload.

43.7.3.130 RxICMP_Error_Packets Register (Offset = 844h) [Reset = 0h]

RxICMP_Error_Packets is shown in Figure 43-169 and described in Table 43-223.

Return to the Summary Table.

This register provides the number of good IP datagrams received by DWC_ether_qos whose ICMP payload has a checksum error.

Figure 43-169 RxICMP_Error_Packets Register
313029282726252423222120191817161514131211109876543210
RXICMPERRPKT
R-0h
Table 43-223 RxICMP_Error_Packets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXICMPERRPKTR0hRxICMP Error Packets
This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error.

43.7.3.131 RxIPv4_Good_Octets Register (Offset = 850h) [Reset = 0h]

RxIPv4_Good_Octets is shown in Figure 43-170 and described in Table 43-224.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-170 RxIPv4_Good_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV4GDOCT
R-0h
Table 43-224 RxIPv4_Good_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4GDOCTR0hRxIPv4 Good Octets
This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.132 RxIPv4_Header_Error_Octets Register (Offset = 854h) [Reset = 0h]

RxIPv4_Header_Error_Octets is shown in Figure 43-171 and described in Table 43-225.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-171 RxIPv4_Header_Error_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV4HDRERROCT
R-0h
Table 43-225 RxIPv4_Header_Error_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4HDRERROCTR0hRxIPv4 Header Error Octets
This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.133 RxIPv4_No_Payload_Octets Register (Offset = 858h) [Reset = 0h]

RxIPv4_No_Payload_Octets is shown in Figure 43-172 and described in Table 43-226.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-172 RxIPv4_No_Payload_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV4NOPAYOCT
R-0h
Table 43-226 RxIPv4_No_Payload_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4NOPAYOCTR0hRxIPv4 Payload Octets
This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.134 RxIPv4_Fragmented_Octets Register (Offset = 85Ch) [Reset = 0h]

RxIPv4_Fragmented_Octets is shown in Figure 43-173 and described in Table 43-227.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-173 RxIPv4_Fragmented_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV4FRAGOCT
R-0h
Table 43-227 RxIPv4_Fragmented_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4FRAGOCTR0hRxIPv4 Fragmented Octets
This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.135 RxIPv4_UDP_Checksum_Disable_Octets Register (Offset = 860h) [Reset = 0h]

RxIPv4_UDP_Checksum_Disable_Octets is shown in Figure 43-174 and described in Table 43-228.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-174 RxIPv4_UDP_Checksum_Disable_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV4UDSBLOCT
R-0h
Table 43-228 RxIPv4_UDP_Checksum_Disable_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV4UDSBLOCTR0hRxIPv4 UDP Checksum Disable Octets
This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.136 RxIPv6_Good_Octets Register (Offset = 864h) [Reset = 0h]

RxIPv6_Good_Octets is shown in Figure 43-175 and described in Table 43-229.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in good IPv6 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-175 RxIPv6_Good_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV6GDOCT
R-0h
Table 43-229 RxIPv6_Good_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV6GDOCTR0hRxIPv6 Good Octets
This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.137 RxIPv6_Header_Error_Octets Register (Offset = 868h) [Reset = 0h]

RxIPv6_Header_Error_Octets is shown in Figure 43-176 and described in Table 43-230.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams with header errors (length, version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-176 RxIPv6_Header_Error_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV6HDRERROCT
R-0h
Table 43-230 RxIPv6_Header_Error_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV6HDRERROCTR0hRxIPv6 Header Error Octets
This field indicates the number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.138 RxIPv6_No_Payload_Octets Register (Offset = 86Ch) [Reset = 0h]

RxIPv6_No_Payload_Octets is shown in Figure 43-177 and described in Table 43-231.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

Figure 43-177 RxIPv6_No_Payload_Octets Register
313029282726252423222120191817161514131211109876543210
RXIPV6NOPAYOCT
R-0h
Table 43-231 RxIPv6_No_Payload_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXIPV6NOPAYOCTR0hRxIPv6 Payload Octets
This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.

43.7.3.139 RxUDP_Good_Octets Register (Offset = 870h) [Reset = 0h]

RxUDP_Good_Octets is shown in Figure 43-178 and described in Table 43-232.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a good UDP segment. This counter does not count IP header bytes.

Figure 43-178 RxUDP_Good_Octets Register
313029282726252423222120191817161514131211109876543210
RXUDPGDOCT
R-0h
Table 43-232 RxUDP_Good_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXUDPGDOCTR0hRxUDP Good Octets
This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes.

43.7.3.140 RxUDP_Error_Octets Register (Offset = 874h) [Reset = 0h]

RxUDP_Error_Octets is shown in Figure 43-179 and described in Table 43-233.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a UDP segment that had checksum errors. This counter does not count IP header bytes.

Figure 43-179 RxUDP_Error_Octets Register
313029282726252423222120191817161514131211109876543210
RXUDPERROCT
R-0h
Table 43-233 RxUDP_Error_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXUDPERROCTR0hRxUDP Error Octets
This field indicates the number of bytes received in a UDP segment that had checksum errors. This counter does not count IP header bytes.

43.7.3.141 RxTCP_Good_Octets Register (Offset = 878h) [Reset = 0h]

RxTCP_Good_Octets is shown in Figure 43-180 and described in Table 43-234.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a good TCP segment. This counter does not count IP header bytes.

Figure 43-180 RxTCP_Good_Octets Register
313029282726252423222120191817161514131211109876543210
RXTCPGDOCT
R-0h
Table 43-234 RxTCP_Good_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXTCPGDOCTR0hRxTCP Good Octets
This field indicates the number of bytes received in a good TCP segment. This counter does not count IP header bytes.

43.7.3.142 RxTCP_Error_Octets Register (Offset = 87Ch) [Reset = 0h]

RxTCP_Error_Octets is shown in Figure 43-181 and described in Table 43-235.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a TCP segment that had checksum errors. This counter does not count IP header bytes.

Figure 43-181 RxTCP_Error_Octets Register
313029282726252423222120191817161514131211109876543210
RXTCPERROCT
R-0h
Table 43-235 RxTCP_Error_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXTCPERROCTR0hRxTCP Error Octets
This field indicates the number of bytes received in a TCP segment that had checksum errors. This counter does not count IP header bytes.

43.7.3.143 RxICMP_Good_Octets Register (Offset = 880h) [Reset = 0h]

RxICMP_Good_Octets is shown in Figure 43-182 and described in Table 43-236.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a good ICMP segment. This counter does not count IP header bytes.

Figure 43-182 RxICMP_Good_Octets Register
313029282726252423222120191817161514131211109876543210
RXICMPGDOCT
R-0h
Table 43-236 RxICMP_Good_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXICMPGDOCTR0hRxICMP Good Octets
This field indicates the number of bytes received in a good ICMP segment. This counter does not count IP header bytes.

43.7.3.144 RxICMP_Error_Octets Register (Offset = 884h) [Reset = 0h]

RxICMP_Error_Octets is shown in Figure 43-183 and described in Table 43-237.

Return to the Summary Table.

This register provides the number of bytes received by DWC_ether_qos in a ICMP segment that had checksum errors. This counter does not count IP header bytes.

Figure 43-183 RxICMP_Error_Octets Register
313029282726252423222120191817161514131211109876543210
RXICMPERROCT
R-0h
Table 43-237 RxICMP_Error_Octets Register Field Descriptions
BitFieldTypeResetDescription
31-0RXICMPERROCTR0hRxICMP Error Octets
This field indicates the number of bytes received in a ICMP segment that had checksum errors. This counter does not count IP header bytes.

43.7.3.145 MAC_L3_L4_Control0 Register (Offset = 900h) [Reset = 0h]

MAC_L3_L4_Control0 is shown in Figure 43-184 and described in Table 43-238.

Return to the Summary Table.

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.

Figure 43-184 MAC_L3_L4_Control0 Register
3130292827262524
RESERVEDDMCHEN0RESERVEDDMCHN0
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDL4DPIM0L4DPM0L4SPIM0L4SPM0RESERVEDL4PEN0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
L3HDBM0L3HSBM0
R/W-0hR/W-0h
76543210
L3HSBM0L3DAIM0L3DAM0L3SAIM0L3SAM0RESERVEDL3PEN0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-238 MAC_L3_L4_Control0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28DMCHEN0R/W0hDMA Channel Select Enable
When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. The DMA channel is indicated by the DMCHN bits. When this bit is reset, the DMA channel is not decided by this filter.
0h = DMA Channel Select is disabled : 0x0
1h = DMA Channel Select is enabled : 0x1
27-25RESERVEDR0hReserved.
24DMCHN0R/W0hDMA Channel Number
When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. The width of this field depends on the number of the DMA channels present in your configuration.
23-22RESERVEDR0hReserved.
21L4DPIM0R/W0hLayer 4 Destination Port Inverse Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4DPM0 bit is set high.
0h = Layer 4 Destination Port Inverse Match is disabled : 0x0
1h = Layer 4 Destination Port Inverse Match is enabled : 0x1
20L4DPM0R/W0hLayer 4 Destination Port Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching.
0h = Layer 4 Destination Port Match is disabled : 0x0
1h = Layer 4 Destination Port Match is enabled : 0x1
19L4SPIM0R/W0hLayer 4 Source Port Inverse Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4SPM0 bit is set high.
0h = Layer 4 Source Port Inverse Match is disabled : 0x0
1h = Layer 4 Source Port Inverse Match is enabled : 0x1
18L4SPM0R/W0hLayer 4 Source Port Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching.
0h = Layer 4 Source Port Match is disabled : 0x0
1h = Layer 4 Source Port Match is enabled : 0x1
17RESERVEDR0hReserved.
16L4PEN0R/W0hLayer 4 Protocol Enable
When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching.
The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set.
0h = Layer 4 Protocol is disabled : 0x0
1h = Layer 4 Protocol is enabled : 0x1
15-11L3HDBM0R/W0hLayer 3 IP DA Higher Bits Match
IPv4 Packets:
This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits:
- 0: No bits are masked.
- 1: LSb[0] is masked.
- 2: Two LSbs [1:0] are masked
- ..
- 127: All bits except MSb are masked.
This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set.
10-6L3HSBM0R/W0hLayer 3 IP SA Higher Bits Match
IPv4 Packets:
This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high.
5L3DAIM0R/W0hLayer 3 IP DA Inverse Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3DAM0 bit is set high.
0h = Layer 3 IP DA Inverse Match is disabled : 0x0
1h = Layer 3 IP DA Inverse Match is enabled : 0x1
4L3DAM0R/W0hLayer 3 IP DA Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering.
0h = Layer 3 IP DA Match is disabled : 0x0
1h = Layer 3 IP DA Match is enabled : 0x1
3L3SAIM0R/W0hLayer 3 IP SA Inverse Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3SAM0 bit is set.
0h = Layer 3 IP SA Inverse Match is disabled : 0x0
1h = Layer 3 IP SA Inverse Match is enabled : 0x1
2L3SAM0R/W0hLayer 3 IP SA Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering.
0h = Layer 3 IP SA Match is disabled : 0x0
1h = Layer 3 IP SA Match is enabled : 0x1
1RESERVEDR0hReserved.
0L3PEN0R/W0hLayer 3 Protocol Enable
When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets.
The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set.
0h = Layer 3 Protocol is disabled : 0x0
1h = Layer 3 Protocol is enabled : 0x1

43.7.3.146 MAC_Layer4_Address0 Register (Offset = 904h) [Reset = 0h]

MAC_Layer4_Address0 is shown in Figure 43-185 and described in Table 43-239.

Return to the Summary Table.

The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

Figure 43-185 MAC_Layer4_Address0 Register
313029282726252423222120191817161514131211109876543210
L4DP0L4SP0
R/W-0hR/W-0h
Table 43-239 MAC_Layer4_Address0 Register Field Descriptions
BitFieldTypeResetDescription
31-16L4DP0R/W0hLayer 4 Destination Port Number Field
When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4DPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets.
15-0L4SP0R/W0hLayer 4 Source Port Number Field
When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4SPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets.

43.7.3.147 MAC_Layer3_Addr0_Reg0 Register (Offset = 910h) [Reset = 0h]

MAC_Layer3_Addr0_Reg0 is shown in Figure 43-186 and described in Table 43-240.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Figure 43-186 MAC_Layer3_Addr0_Reg0 Register
313029282726252423222120191817161514131211109876543210
L3A00
R/W-0h
Table 43-240 MAC_Layer3_Addr0_Reg0 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A00R/W0hLayer 3 Address 0 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets.

43.7.3.148 MAC_Layer3_Addr1_Reg0 Register (Offset = 914h) [Reset = 0h]

MAC_Layer3_Addr1_Reg0 is shown in Figure 43-187 and described in Table 43-241.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

Figure 43-187 MAC_Layer3_Addr1_Reg0 Register
313029282726252423222120191817161514131211109876543210
L3A10
R/W-0h
Table 43-241 MAC_Layer3_Addr1_Reg0 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A10R/W0hLayer 3 Address 1 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets.

43.7.3.149 MAC_Layer3_Addr2_Reg0 Register (Offset = 918h) [Reset = 0h]

MAC_Layer3_Addr2_Reg0 is shown in Figure 43-188 and described in Table 43-242.

Return to the Summary Table.

The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.

Figure 43-188 MAC_Layer3_Addr2_Reg0 Register
313029282726252423222120191817161514131211109876543210
L3A20
R/W-0h
Table 43-242 MAC_Layer3_Addr2_Reg0 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A20R/W0hLayer 3 Address 2 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.150 MAC_Layer3_Addr3_Reg0 Register (Offset = 91Ch) [Reset = 0h]

MAC_Layer3_Addr3_Reg0 is shown in Figure 43-189 and described in Table 43-243.

Return to the Summary Table.

The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.

Figure 43-189 MAC_Layer3_Addr3_Reg0 Register
313029282726252423222120191817161514131211109876543210
L3A30
R/W-0h
Table 43-243 MAC_Layer3_Addr3_Reg0 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A30R/W0hLayer 3 Address 3 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.151 MAC_L3_L4_Control1 Register (Offset = 930h) [Reset = 0h]

MAC_L3_L4_Control1 is shown in Figure 43-190 and described in Table 43-244.

Return to the Summary Table.

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.

Figure 43-190 MAC_L3_L4_Control1 Register
3130292827262524
RESERVEDDMCHEN1RESERVEDDMCHN1
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDL4DPIM1L4DPM1L4SPIM1L4SPM1RESERVEDL4PEN1
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
L3HDBM1L3HSBM1
R/W-0hR/W-0h
76543210
L3HSBM1L3DAIM1L3DAM1L3SAIM1L3SAM1RESERVEDL3PEN1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-244 MAC_L3_L4_Control1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28DMCHEN1R/W0hDMA Channel Select Enable
When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. The DMA channel is indicated by the DMCHN bits. When this bit is reset, the DMA channel is not decided by this filter.
0h = DMA Channel Select is disabled : 0x0
1h = DMA Channel Select is enabled : 0x1
27-25RESERVEDR0hReserved.
24DMCHN1R/W0hDMA Channel Number
When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. The width of this field depends on the number of the DMA channels present in your configuration.
23-22RESERVEDR0hReserved.
21L4DPIM1R/W0hLayer 4 Destination Port Inverse Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4DPM0 bit is set high.
0h = Layer 4 Destination Port Inverse Match is disabled : 0x0
1h = Layer 4 Destination Port Inverse Match is enabled : 0x1
20L4DPM1R/W0hLayer 4 Destination Port Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching.
0h = Layer 4 Destination Port Match is disabled : 0x0
1h = Layer 4 Destination Port Match is enabled : 0x1
19L4SPIM1R/W0hLayer 4 Source Port Inverse Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4SPM0 bit is set high.
0h = Layer 4 Source Port Inverse Match is disabled : 0x0
1h = Layer 4 Source Port Inverse Match is enabled : 0x1
18L4SPM1R/W0hLayer 4 Source Port Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching.
0h = Layer 4 Source Port Match is disabled : 0x0
1h = Layer 4 Source Port Match is enabled : 0x1
17RESERVEDR0hReserved.
16L4PEN1R/W0hLayer 4 Protocol Enable
When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching.
The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set.
0h = Layer 4 Protocol is disabled : 0x0
1h = Layer 4 Protocol is enabled : 0x1
15-11L3HDBM1R/W0hLayer 3 IP DA Higher Bits Match
IPv4 Packets:
This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits:
- 0: No bits are masked.
- 1: LSb[0] is masked.
- 2: Two LSbs [1:0] are masked
- ..
- 127: All bits except MSb are masked.
This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set.
10-6L3HSBM1R/W0hLayer 3 IP SA Higher Bits Match
IPv4 Packets:
This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high.
5L3DAIM1R/W0hLayer 3 IP DA Inverse Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3DAM0 bit is set high.
0h = Layer 3 IP DA Inverse Match is disabled : 0x0
1h = Layer 3 IP DA Inverse Match is enabled : 0x1
4L3DAM1R/W0hLayer 3 IP DA Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering.
0h = Layer 3 IP DA Match is disabled : 0x0
1h = Layer 3 IP DA Match is enabled : 0x1
3L3SAIM1R/W0hLayer 3 IP SA Inverse Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3SAM0 bit is set.
0h = Layer 3 IP SA Inverse Match is disabled : 0x0
1h = Layer 3 IP SA Inverse Match is enabled : 0x1
2L3SAM1R/W0hLayer 3 IP SA Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering.
0h = Layer 3 IP SA Match is disabled : 0x0
1h = Layer 3 IP SA Match is enabled : 0x1
1RESERVEDR0hReserved.
0L3PEN1R/W0hLayer 3 Protocol Enable
When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets.
The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set.
0h = Layer 3 Protocol is disabled : 0x0
1h = Layer 3 Protocol is enabled : 0x1

43.7.3.152 MAC_Layer4_Address1 Register (Offset = 934h) [Reset = 0h]

MAC_Layer4_Address1 is shown in Figure 43-191 and described in Table 43-245.

Return to the Summary Table.

The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

Figure 43-191 MAC_Layer4_Address1 Register
313029282726252423222120191817161514131211109876543210
L4DP1L4SP1
R/W-0hR/W-0h
Table 43-245 MAC_Layer4_Address1 Register Field Descriptions
BitFieldTypeResetDescription
31-16L4DP1R/W0hLayer 4 Destination Port Number Field
When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4DPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets.
15-0L4SP1R/W0hLayer 4 Source Port Number Field
When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4SPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets.

43.7.3.153 MAC_Layer3_Addr0_Reg1 Register (Offset = 940h) [Reset = 0h]

MAC_Layer3_Addr0_Reg1 is shown in Figure 43-192 and described in Table 43-246.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Figure 43-192 MAC_Layer3_Addr0_Reg1 Register
313029282726252423222120191817161514131211109876543210
L3A01
R/W-0h
Table 43-246 MAC_Layer3_Addr0_Reg1 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A01R/W0hLayer 3 Address 0 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets.

43.7.3.154 MAC_Layer3_Addr1_Reg1 Register (Offset = 944h) [Reset = 0h]

MAC_Layer3_Addr1_Reg1 is shown in Figure 43-193 and described in Table 43-247.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

Figure 43-193 MAC_Layer3_Addr1_Reg1 Register
313029282726252423222120191817161514131211109876543210
L3A11
R/W-0h
Table 43-247 MAC_Layer3_Addr1_Reg1 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A11R/W0hLayer 3 Address 1 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets.

43.7.3.155 MAC_Layer3_Addr2_Reg1 Register (Offset = 948h) [Reset = 0h]

MAC_Layer3_Addr2_Reg1 is shown in Figure 43-194 and described in Table 43-248.

Return to the Summary Table.

The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.

Figure 43-194 MAC_Layer3_Addr2_Reg1 Register
313029282726252423222120191817161514131211109876543210
L3A21
R/W-0h
Table 43-248 MAC_Layer3_Addr2_Reg1 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A21R/W0hLayer 3 Address 2 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.156 MAC_Layer3_Addr3_Reg1 Register (Offset = 94Ch) [Reset = 0h]

MAC_Layer3_Addr3_Reg1 is shown in Figure 43-195 and described in Table 43-249.

Return to the Summary Table.

The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.

Figure 43-195 MAC_Layer3_Addr3_Reg1 Register
313029282726252423222120191817161514131211109876543210
L3A31
R/W-0h
Table 43-249 MAC_Layer3_Addr3_Reg1 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A31R/W0hLayer 3 Address 3 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.157 MAC_L3_L4_Control2 Register (Offset = 960h) [Reset = 0h]

MAC_L3_L4_Control2 is shown in Figure 43-196 and described in Table 43-250.

Return to the Summary Table.

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.

Figure 43-196 MAC_L3_L4_Control2 Register
3130292827262524
RESERVEDDMCHEN2RESERVEDDMCHN2
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDL4DPIM2L4DPM2L4SPIM2L4SPM2RESERVEDL4PEN2
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
L3HDBM2L3HSBM2
R/W-0hR/W-0h
76543210
L3HSBM2L3DAIM2L3DAM2L3SAIM2L3SAM2RESERVEDL3PEN2
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-250 MAC_L3_L4_Control2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28DMCHEN2R/W0hDMA Channel Select Enable
When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. The DMA channel is indicated by the DMCHN bits. When this bit is reset, the DMA channel is not decided by this filter.
0h = DMA Channel Select is disabled : 0x0
1h = DMA Channel Select is enabled : 0x1
27-25RESERVEDR0hReserved.
24DMCHN2R/W0hDMA Channel Number
When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. The width of this field depends on the number of the DMA channels present in your configuration.
23-22RESERVEDR0hReserved.
21L4DPIM2R/W0hLayer 4 Destination Port Inverse Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4DPM0 bit is set high.
0h = Layer 4 Destination Port Inverse Match is disabled : 0x0
1h = Layer 4 Destination Port Inverse Match is enabled : 0x1
20L4DPM2R/W0hLayer 4 Destination Port Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching.
0h = Layer 4 Destination Port Match is disabled : 0x0
1h = Layer 4 Destination Port Match is enabled : 0x1
19L4SPIM2R/W0hLayer 4 Source Port Inverse Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4SPM0 bit is set high.
0h = Layer 4 Source Port Inverse Match is disabled : 0x0
1h = Layer 4 Source Port Inverse Match is enabled : 0x1
18L4SPM2R/W0hLayer 4 Source Port Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching.
0h = Layer 4 Source Port Match is disabled : 0x0
1h = Layer 4 Source Port Match is enabled : 0x1
17RESERVEDR0hReserved.
16L4PEN2R/W0hLayer 4 Protocol Enable
When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching.
The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set.
0h = Layer 4 Protocol is disabled : 0x0
1h = Layer 4 Protocol is enabled : 0x1
15-11L3HDBM2R/W0hLayer 3 IP DA Higher Bits Match
IPv4 Packets:
This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits:
- 0: No bits are masked.
- 1: LSb[0] is masked.
- 2: Two LSbs [1:0] are masked
- ..
- 127: All bits except MSb are masked.
This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set.
10-6L3HSBM2R/W0hLayer 3 IP SA Higher Bits Match
IPv4 Packets:
This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high.
5L3DAIM2R/W0hLayer 3 IP DA Inverse Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3DAM0 bit is set high.
0h = Layer 3 IP DA Inverse Match is disabled : 0x0
1h = Layer 3 IP DA Inverse Match is enabled : 0x1
4L3DAM2R/W0hLayer 3 IP DA Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering.
0h = Layer 3 IP DA Match is disabled : 0x0
1h = Layer 3 IP DA Match is enabled : 0x1
3L3SAIM2R/W0hLayer 3 IP SA Inverse Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3SAM0 bit is set.
0h = Layer 3 IP SA Inverse Match is disabled : 0x0
1h = Layer 3 IP SA Inverse Match is enabled : 0x1
2L3SAM2R/W0hLayer 3 IP SA Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering.
0h = Layer 3 IP SA Match is disabled : 0x0
1h = Layer 3 IP SA Match is enabled : 0x1
1RESERVEDR0hReserved.
0L3PEN2R/W0hLayer 3 Protocol Enable
When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets.
The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set.
0h = Layer 3 Protocol is disabled : 0x0
1h = Layer 3 Protocol is enabled : 0x1

43.7.3.158 MAC_Layer4_Address2 Register (Offset = 964h) [Reset = 0h]

MAC_Layer4_Address2 is shown in Figure 43-197 and described in Table 43-251.

Return to the Summary Table.

The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

Figure 43-197 MAC_Layer4_Address2 Register
313029282726252423222120191817161514131211109876543210
L4DP2L4SP2
R/W-0hR/W-0h
Table 43-251 MAC_Layer4_Address2 Register Field Descriptions
BitFieldTypeResetDescription
31-16L4DP2R/W0hLayer 4 Destination Port Number Field
When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4DPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets.
15-0L4SP2R/W0hLayer 4 Source Port Number Field
When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4SPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets.

43.7.3.159 MAC_Layer3_Addr0_Reg2 Register (Offset = 970h) [Reset = 0h]

MAC_Layer3_Addr0_Reg2 is shown in Figure 43-198 and described in Table 43-252.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Figure 43-198 MAC_Layer3_Addr0_Reg2 Register
313029282726252423222120191817161514131211109876543210
L3A02
R/W-0h
Table 43-252 MAC_Layer3_Addr0_Reg2 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A02R/W0hLayer 3 Address 0 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets.

43.7.3.160 MAC_Layer3_Addr1_Reg2 Register (Offset = 974h) [Reset = 0h]

MAC_Layer3_Addr1_Reg2 is shown in Figure 43-199 and described in Table 43-253.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

Figure 43-199 MAC_Layer3_Addr1_Reg2 Register
313029282726252423222120191817161514131211109876543210
L3A12
R/W-0h
Table 43-253 MAC_Layer3_Addr1_Reg2 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A12R/W0hLayer 3 Address 1 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets.

43.7.3.161 MAC_Layer3_Addr2_Reg2 Register (Offset = 978h) [Reset = 0h]

MAC_Layer3_Addr2_Reg2 is shown in Figure 43-200 and described in Table 43-254.

Return to the Summary Table.

The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.

Figure 43-200 MAC_Layer3_Addr2_Reg2 Register
313029282726252423222120191817161514131211109876543210
L3A22
R/W-0h
Table 43-254 MAC_Layer3_Addr2_Reg2 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A22R/W0hLayer 3 Address 2 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.162 MAC_Layer3_Addr3_Reg2 Register (Offset = 97Ch) [Reset = 0h]

MAC_Layer3_Addr3_Reg2 is shown in Figure 43-201 and described in Table 43-255.

Return to the Summary Table.

The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.

Figure 43-201 MAC_Layer3_Addr3_Reg2 Register
313029282726252423222120191817161514131211109876543210
L3A32
R/W-0h
Table 43-255 MAC_Layer3_Addr3_Reg2 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A32R/W0hLayer 3 Address 3 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.163 MAC_L3_L4_Control3 Register (Offset = 990h) [Reset = 0h]

MAC_L3_L4_Control3 is shown in Figure 43-202 and described in Table 43-256.

Return to the Summary Table.

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.

Figure 43-202 MAC_L3_L4_Control3 Register
3130292827262524
RESERVEDDMCHEN3RESERVEDDMCHN3
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDL4DPIM3L4DPM3L4SPIM3L4SPM3RESERVEDL4PEN3
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
L3HDBM3L3HSBM3
R/W-0hR/W-0h
76543210
L3HSBM3L3DAIM3L3DAM3L3SAIM3L3SAM3RESERVEDL3PEN3
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-256 MAC_L3_L4_Control3 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28DMCHEN3R/W0hDMA Channel Select Enable
When set, this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. The DMA channel is indicated by the DMCHN bits. When this bit is reset, the DMA channel is not decided by this filter.
0h = DMA Channel Select is disabled : 0x0
1h = DMA Channel Select is enabled : 0x1
27-25RESERVEDR0hReserved.
24DMCHN3R/W0hDMA Channel Number
When DMCHEN is set high, this field selects the DMA Channel number to which the packet passed by this filter is routed. The width of this field depends on the number of the DMA channels present in your configuration.
23-22RESERVEDR0hReserved.
21L4DPIM3R/W0hLayer 4 Destination Port Inverse Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Destination Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4DPM0 bit is set high.
0h = Layer 4 Destination Port Inverse Match is disabled : 0x0
1h = Layer 4 Destination Port Inverse Match is enabled : 0x1
20L4DPM3R/W0hLayer 4 Destination Port Match Enable
When this bit is set, the Layer 4 Destination Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Destination Port number field for matching.
0h = Layer 4 Destination Port Match is disabled : 0x0
1h = Layer 4 Destination Port Match is enabled : 0x1
19L4SPIM3R/W0hLayer 4 Source Port Inverse Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset, the Layer 4 Source Port number field is enabled for perfect matching.
This bit is valid and applicable only when the L4SPM0 bit is set high.
0h = Layer 4 Source Port Inverse Match is disabled : 0x0
1h = Layer 4 Source Port Inverse Match is enabled : 0x1
18L4SPM3R/W0hLayer 4 Source Port Match Enable
When this bit is set, the Layer 4 Source Port number field is enabled for matching. When this bit is reset, the MAC ignores the Layer 4 Source Port number field for matching.
0h = Layer 4 Source Port Match is disabled : 0x0
1h = Layer 4 Source Port Match is enabled : 0x1
17RESERVEDR0hReserved.
16L4PEN3R/W0hLayer 4 Protocol Enable
When this bit is set, the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset, the Source and Destination Port number fields of TCP packets are used for matching.
The Layer 4 matching is done only when the L4SPM0 or L4DPM0 bit is set.
0h = Layer 4 Protocol is disabled : 0x0
1h = Layer 4 Protocol is enabled : 0x1
15-11L3HDBM3R/W0hLayer 3 IP DA Higher Bits Match
IPv4 Packets:
This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
Bits[12:11] of this field correspond to Bits[6:5] of L3HSBM0 which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 packets. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits:
- 0: No bits are masked.
- 1: LSb[0] is masked.
- 2: Two LSbs [1:0] are masked
- ..
- 127: All bits except MSb are masked.
This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set.
10-6L3HSBM3R/W0hLayer 3 IP SA Higher Bits Match
IPv4 Packets:
This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field:
- 0: No bits are masked.
- 1: LSb[0] is masked
- 2: Two LSbs [1:0] are masked
- ..
- 31: All bits except MSb are masked.
IPv6 Packets:
This field contains Bits[4:0] of L3HSBM0. These bits indicate the number of higher bits of IP Source or Destination Address matched in the IPv6 packets. This field is valid and applicable only when the L3DAM0 or L3SAM0 bit is set high.
5L3DAIM3R/W0hLayer 3 IP DA Inverse Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset, the Layer 3 IP Destination Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3DAM0 bit is set high.
0h = Layer 3 IP DA Inverse Match is disabled : 0x0
1h = Layer 3 IP DA Inverse Match is enabled : 0x1
4L3DAM3R/W0hLayer 3 IP DA Match Enable
When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Destination Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3SAM0 bit because either IPv6 DA or SA can be checked for filtering.
0h = Layer 3 IP DA Match is disabled : 0x0
1h = Layer 3 IP DA Match is enabled : 0x1
3L3SAIM3R/W0hLayer 3 IP SA Inverse Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset, the Layer 3 IP Source Address field is enabled for perfect matching.
This bit is valid and applicable only when the L3SAM0 bit is set.
0h = Layer 3 IP SA Inverse Match is disabled : 0x0
1h = Layer 3 IP SA Inverse Match is enabled : 0x1
2L3SAM3R/W0hLayer 3 IP SA Match Enable
When this bit is set, the Layer 3 IP Source Address field is enabled for matching. When this bit is reset, the MAC ignores the Layer 3 IP Source Address field for matching.
Note: When the L3PEN0 bit is set, you should set either this bit or the L3DAM0 bit because either IPv6 SA or DA can be checked for filtering.
0h = Layer 3 IP SA Match is disabled : 0x0
1h = Layer 3 IP SA Match is enabled : 0x1
1RESERVEDR0hReserved.
0L3PEN3R/W0hLayer 3 Protocol Enable
When this bit is set, the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset, the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets.
The Layer 3 matching is done only when the L3SAM0 or L3DAM0 bit is set.
0h = Layer 3 Protocol is disabled : 0x0
1h = Layer 3 Protocol is enabled : 0x1

43.7.3.164 MAC_Layer4_Address3 Register (Offset = 994h) [Reset = 0h]

MAC_Layer4_Address3 is shown in Figure 43-203 and described in Table 43-257.

Return to the Summary Table.

The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core.
You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

Figure 43-203 MAC_Layer4_Address3 Register
313029282726252423222120191817161514131211109876543210
L4DP3L4SP3
R/W-0hR/W-0h
Table 43-257 MAC_Layer4_Address3 Register Field Descriptions
BitFieldTypeResetDescription
31-16L4DP3R/W0hLayer 4 Destination Port Number Field
When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4DPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 packets.
15-0L4SP3R/W0hLayer 4 Source Port Number Field
When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets.
When the L4PEN0 and L4SPM0 bits are set in MAC_L3_L4_Control0 register, this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 packets.

43.7.3.165 MAC_Layer3_Addr0_Reg3 Register (Offset = 9A0h) [Reset = 0h]

MAC_Layer3_Addr0_Reg3 is shown in Figure 43-204 and described in Table 43-258.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Figure 43-204 MAC_Layer3_Addr0_Reg3 Register
313029282726252423222120191817161514131211109876543210
L3A03
R/W-0h
Table 43-258 MAC_Layer3_Addr0_Reg3 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A03R/W0hLayer 3 Address 0 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[31:0] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Source Address field in the IPv4 packets.

43.7.3.166 MAC_Layer3_Addr1_Reg3 Register (Offset = 9A4h) [Reset = 0h]

MAC_Layer3_Addr1_Reg3 is shown in Figure 43-205 and described in Table 43-259.

Return to the Summary Table.

For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

Figure 43-205 MAC_Layer3_Addr1_Reg3 Register
313029282726252423222120191817161514131211109876543210
L3A13
R/W-0h
Table 43-259 MAC_Layer3_Addr1_Reg3 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A13R/W0hLayer 3 Address 1 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[63:32] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset and the L3SAM0 bit is set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with the IP Destination Address field in the IPv4 packets.

43.7.3.167 MAC_Layer3_Addr2_Reg3 Register (Offset = 9A8h) [Reset = 0h]

MAC_Layer3_Addr2_Reg3 is shown in Figure 43-206 and described in Table 43-260.

Return to the Summary Table.

The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.

Figure 43-206 MAC_Layer3_Addr2_Reg3 Register
313029282726252423222120191817161514131211109876543210
L3A23
R/W-0h
Table 43-260 MAC_Layer3_Addr2_Reg3 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A23R/W0hLayer 3 Address 2 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[95:64] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.168 MAC_Layer3_Addr3_Reg3 Register (Offset = 9ACh) [Reset = 0h]

MAC_Layer3_Addr3_Reg3 is shown in Figure 43-207 and described in Table 43-261.

Return to the Summary Table.

The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.

Figure 43-207 MAC_Layer3_Addr3_Reg3 Register
313029282726252423222120191817161514131211109876543210
L3A33
R/W-0h
Table 43-261 MAC_Layer3_Addr3_Reg3 Register Field Descriptions
BitFieldTypeResetDescription
31-0L3A33R/W0hLayer 3 Address 3 Field
When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets.
When the L3PEN0 and L3DAM0 bits are set in the MAC_L3_L4_Control0 register, this field contains the value to be matched with Bits[127:96] of the IP Destination Address field in the IPv6 packets.
When the L3PEN0 bit is reset in the MAC_L3_L4_Control0 register, this field is not used.

43.7.3.169 MAC_Timestamp_Control Register (Offset = B00h) [Reset = 2000h]

MAC_Timestamp_Control is shown in Figure 43-208 and described in Table 43-262.

Return to the Summary Table.

This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver.

Figure 43-208 MAC_Timestamp_Control Register
3130292827262524
RESERVEDAV8021ASMENRESERVEDTXTSSTSM
R-0hR/W-0hR-0hR/W-0h
2322212019181716
RESERVEDESTICSCTSENMACADDRSNAPTYPSEL
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TSMSTRENATSEVNTENATSIPV4ENATSIPV6ENATSIPENATSVER2ENATSCTRLSSRTSENALL
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTSADDREGRESERVEDTSUPDTTSINITTSCFUPDTTSENA
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-262 MAC_Timestamp_Control Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28AV8021ASMENR/W0hAV 802.1AS Mode Enable
When this bit is set, the MAC processes only untagged PTP over Ethernet packets for providing PTP status and capturing timestamp snapshots, that is, IEEE 802.1AS mode of operation.
When PTP offload feature is enabled, for the purpose of PTP offload, the transport specific field in the PTP header is generated and checked based on the value of this bit.
0h = AV 802.1AS Mode is disabled : 0x0
1h = AV 802.1AS Mode is enabled : 0x1
27-25RESERVEDR0hReserved.
24TXTSSTSMR/W0hTransmit Timestamp Status Mode
When this bit is set, the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the MAC_Tx_Timestamp_Status_Nanoseconds register.
When this bit is reset, the MAC ignores the timestamp status of current packet if the timestamp status of previous packet is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the MAC_Tx_Timestamp_Status_Nanoseconds register.
0h = Transmit Timestamp Status Mode is disabled : 0x0
1h = Transmit Timestamp Status Mode is enabled : 0x1
23-21RESERVEDR0hReserved.
20ESTIR/W0hExternal System Time Input
When this bit is set, the MAC uses the external 64-bit reference System Time input for the following:
- To take the timestamp provided as status
- To insert the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is enabled.
When this bit is reset, the MAC uses the internal reference System Time.
0h = External System Time Input is disabled : 0x0
1h = External System Time Input is enabled : 0x1
19CSCR/W0hEnable checksum correction during OST for PTP over UDP/IPv4 packets
When this bit is set, the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct, for changes made to origin timestamp and/or correction field as part of one step timestamp operation. The application shall form the packet with these two dummy bytes.
When reset, no updates are done to keep the UDP checksum correct. The application shall form the packet with UDP checksum set to 0.
0h = checksum correction during OST for PTP over UDP/IPv4 packets is disabled : 0x0
1h = checksum correction during OST for PTP over UDP/IPv4 packets is enabled : 0x1
18TSENMACADDRR/W0hEnable MAC Address for PTP Packet Filtering
When this bit is set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet.
When this bit is set, received PTP packets with DA containing a special multicast or unicast address that matches the one programmed in MAC address registers are considered for processing as indicated below, when PTP is directly sent over Ethernet.
For normal time stamping operation, MAC address registers 0 to 31 is considered for unicast destination address matching.
For PTP offload, only MAC address register 0 is considered for unicast destination address matching.
0h = MAC Address for PTP Packet Filtering is disabled : 0x0
1h = MAC Address for PTP Packet Filtering is enabled : 0x1
17-16SNAPTYPSELR/W0hSelect PTP packets for Taking Snapshots
These bits, along with Bits 15 and 14, decide the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Timestamp Snapshot Dependency on Register Bits Table.
15TSMSTRENAR/W0hEnable Snapshot for Messages Relevant to Master
When this bit is set, the snapshot is taken only for the messages that are relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node.
0h = Snapshot for Messages Relevant to Master is disabled : 0x0
1h = Snapshot for Messages Relevant to Master is enabled : 0x1
14TSEVNTENAR/W0hEnable Timestamp Snapshot for Event Messages
When this bit is set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When this bit is reset, the snapshot is taken for all messages except Announce, Management, and Signaling. For more information about the timestamp snapshots, see Timestamp Snapshot Dependency on Register Bits Table.
0h = Timestamp Snapshot for Event Messages is disabled : 0x0
1h = Timestamp Snapshot for Event Messages is enabled : 0x1
13TSIPV4ENAR/W1hEnable Processing of PTP Packets Sent over IPv4-UDP
When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset, the MAC ignores the PTP transported over IPv4-UDP packets. This bit is set by default.
0h = Processing of PTP Packets Sent over IPv4-UDP is disabled : 0x0
1h = Processing of PTP Packets Sent over IPv4-UDP is enabled : 0x1
12TSIPV6ENAR/W0hEnable Processing of PTP Packets Sent over IPv6-UDP
When this bit is set, the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear, the MAC ignores the PTP transported over IPv6-UDP packets.
0h = Processing of PTP Packets Sent over IPv6-UDP is disabled : 0x0
1h = Processing of PTP Packets Sent over IPv6-UDP is enabled : 0x1
11TSIPENAR/W0hEnable Processing of PTP over Ethernet Packets
When this bit is set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset, the MAC ignores the PTP over Ethernet packets.
0h = Processing of PTP over Ethernet Packets is disabled : 0x0
1h = Processing of PTP over Ethernet Packets is enabled : 0x1
10TSVER2ENAR/W0hEnable PTP Packet Processing for Version 2 Format
When this bit is set, the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset, the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588 formats are described in 'PTP Processing and Control'.
0h = PTP Packet Processing for Version 2 Format is disabled : 0x0
1h = PTP Packet Processing for Version 2 Format is enabled : 0x1
9TSCTRLSSRR/W0hTimestamp Digital or Binary Rollover Control
When this bit is set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment must be programmed correctly depending on the PTP reference clock frequency and the value of this bit.
0h = Timestamp Digital or Binary Rollover Control is disabled : 0x0
1h = Timestamp Digital or Binary Rollover Control is enabled : 0x1
8TSENALLR/W0hEnable Timestamp for All Packets
When this bit is set, the timestamp snapshot is enabled for all packets received by the MAC.
0h = Timestamp for All Packets disabled : 0x0
1h = Timestamp for All Packets enabled : 0x1
7-6RESERVEDR0hReserved.
5TSADDREGR/W0hUpdate Addend Register
When this bit is set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Addend Register is not updated : 0x0
1h = Addend Register is updated : 0x1
4RESERVEDR0hReserved.
3TSUPDTR/W0hUpdate Timestamp
When this bit is set, the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update.
This bit should be zero before updating it. This bit is reset when the update is complete in hardware. The Timestamp Higher Word register (if enabled during core configuration) is not updated.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Timestamp is not updated : 0x0
1h = Timestamp is updated : 0x1
2TSINITR/W0hInitialize Timestamp
When this bit is set, the system time is initialized (overwritten) with the value specified in the MAC Register 80 (System Time Seconds Update Register) and MAC Register 81 (System Time Nanoseconds Update Register).
This bit should be zero before it is updated. This bit is reset when the initialization is complete. The Timestamp Higher Word register (if enabled during core configuration) can only be initialized.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Timestamp is not initialized : 0x0
1h = Timestamp is initialized : 0x1
1TSCFUPDTR/W0hFine or Coarse Timestamp Update
When this bit is set, the Fine method is used to update system timestamp. When this bit is reset, Coarse method is used to update the system timestamp.
0h = Coarse method is used to update system timestamp : 0x0
1h = Fine method is used to update system timestamp : 0x1
0TSENAR/W0hEnable Timestamp
When this bit is set, the timestamp is added for Transmit and Receive packets. When disabled, timestamp is not added for transmit and receive packets and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode.
On the Receive side, the MAC processes the 1588 packets only if this bit is set.
0h = Timestamp is disabled : 0x0
1h = Timestamp is enabled : 0x1

43.7.3.170 MAC_Sub_Second_Increment Register (Offset = B04h) [Reset = 0h]

MAC_Sub_Second_Increment is shown in Figure 43-209 and described in Table 43-263.

Return to the Summary Table.

This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock.

Figure 43-209 MAC_Sub_Second_Increment Register
313029282726252423222120191817161514131211109876543210
RESERVEDSSINCSNSINCRESERVED
R-0hR/W-0hR/W-0hR-0h
Table 43-263 MAC_Sub_Second_Increment Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23-16SSINCR/W0hSub-second Increment Value
The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when the PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in MAC_Timestamp_Control]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465 ns. In this case, you should program a value of 43 (0x2B) which is derived by 20 ns/0.465.
15-8SNSINCR/W0hSub-nanosecond Increment Value
This field contains the sub-nanosecond increment value, represented in
nanoseconds multiplied by 28.
This value is accumulated with the sub-nanoseconds field of the subsecond
register.
For example, when TSCTRLSSR field in the MAC_Timestamp_Control
register is set. and if the required increment is 5.3ns, then SSINC should
be 0x05 and SNSINC should be 0x4C.
7-0RESERVEDR0hReserved.

43.7.3.171 MAC_System_Time_Seconds Register (Offset = B08h) [Reset = 0h]

MAC_System_Time_Seconds is shown in Figure 43-210 and described in Table 43-264.

Return to the Summary Table.

The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from clk_ptp_ref_i to CSR clock).

Figure 43-210 MAC_System_Time_Seconds Register
313029282726252423222120191817161514131211109876543210
TSS
R-0h
Table 43-264 MAC_System_Time_Seconds Register Field Descriptions
BitFieldTypeResetDescription
31-0TSSR0hTimestamp Second
The value in this field indicates the current value in seconds of the System Time maintained by the MAC.

43.7.3.172 MAC_System_Time_Nanoseconds Register (Offset = B0Ch) [Reset = 0h]

MAC_System_Time_Nanoseconds is shown in Figure 43-211 and described in Table 43-265.

Return to the Summary Table.

The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC.

Figure 43-211 MAC_System_Time_Nanoseconds Register
3130292827262524
RESERVEDTSSS
R-0hR-0h
2322212019181716
TSSS
R-0h
15141312111098
TSSS
R-0h
76543210
TSSS
R-0h
Table 43-265 MAC_System_Time_Nanoseconds Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30-0TSSSR0hTimestamp Sub Seconds
The value in this field has the sub-second representation of time, with an accuracy of 0.46 ns. When Bit 9 is set in MAC_Timestamp_Control, each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to zero.

43.7.3.173 MAC_System_Time_Seconds_Update Register (Offset = B10h) [Reset = 0h]

MAC_System_Time_Seconds_Update is shown in Figure 43-212 and described in Table 43-266.

Return to the Summary Table.

The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in EMAC_REGS/EQOS_MAC/MAC_Timestamp_Control.

Figure 43-212 MAC_System_Time_Seconds_Update Register
313029282726252423222120191817161514131211109876543210
TSS
R/W-0h
Table 43-266 MAC_System_Time_Seconds_Update Register Field Descriptions
BitFieldTypeResetDescription
31-0TSSR/W0hTimestamp Seconds
The value in this field is the seconds part of the update.
When ADDSUB is reset, this field must be programmed with the seconds part of the update value.
When ADDSUB is set, this field must be programmed with the complement of the seconds part of the update value.
For example, if 2.000000001 seconds need to be subtracted from the system time, the TSS field in the MAC_Timestamp_Seconds_Update register must be 0xFFFF_FFFE (that is, 232 - 2).

43.7.3.174 MAC_System_Time_Nanoseconds_Update Register (Offset = B14h) [Reset = 0h]

MAC_System_Time_Nanoseconds_Update is shown in Figure 43-213 and described in Table 43-267.

Return to the Summary Table.

MAC System Time Nanoseconds Update register.

Figure 43-213 MAC_System_Time_Nanoseconds_Update Register
3130292827262524
ADDSUBTSSS
R/W-0hR/W-0h
2322212019181716
TSSS
R/W-0h
15141312111098
TSSS
R/W-0h
76543210
TSSS
R/W-0h
Table 43-267 MAC_System_Time_Nanoseconds_Update Register Field Descriptions
BitFieldTypeResetDescription
31ADDSUBR/W0hAdd or Subtract Time
When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register.
0h = Add time : 0x0
1h = Subtract time : 0x1
30-0TSSSR/W0hTimestamp Sub Seconds
The value in this field is the sub-seconds part of the update.
When ADDSUB is reset, this field must be programmed with the sub-seconds part of the update value, with an accuracy based on the TSCTRLSSR bit of the MAC_Timestamp_Control register.
When ADDSUB is set, this field must be programmed with the complement of the sub-seconds part of the update value as described below.
When TSCTRLSSR bit in MAC_Timestamp_Control is set, the programmed value must be 10^9 - <sub-second value>. When TSCTRLSSR bit in MAC_Timestamp_Control is reset, the programmed value must be 231 - <sub-second_value>.
When the TSCTRLSSR bit is reset in the MAC_Timestamp_Control register, each bit represents an accuracy of 0.46 ns. When the TSCTRLSSR bit is set in the MAC_Timestamp_Control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.
For example, if 2.000000001 seconds need to be subtracted from the system time, then the TSSS field in the MAC_Timestamp_Nanoseconds_Update register must be 0x7FFF_FFFF (that is, 231 - 1), when TSCTRLSSR bit in MAC_Timestamp_Control is reset and 0x3B9A_C9FF (that is, 10^9 - 1), when TSCTRLSSR bit in MAC_Timestamp_Control is set.

43.7.3.175 MAC_Timestamp_Addend Register (Offset = B18h) [Reset = 0h]

MAC_Timestamp_Addend is shown in Figure 43-214 and described in Table 43-268.

Return to the Summary Table.

Timestamp Addend register. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register). The content of this register is added to a 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time is updated whenever the accumulator overflows.

Figure 43-214 MAC_Timestamp_Addend Register
313029282726252423222120191817161514131211109876543210
TSAR
R/W-0h
Table 43-268 MAC_Timestamp_Addend Register Field Descriptions
BitFieldTypeResetDescription
31-0TSARR/W0hTimestamp Addend Register
This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization.

43.7.3.176 MAC_System_Time_Higher_Word_Seconds Register (Offset = B1Ch) [Reset = 0h]

MAC_System_Time_Higher_Word_Seconds is shown in Figure 43-215 and described in Table 43-269.

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System Time - Higher Word Seconds register.

Figure 43-215 MAC_System_Time_Higher_Word_Seconds Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSHWR
R-0hR/W-0h
Table 43-269 MAC_System_Time_Higher_Word_Seconds Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-0TSHWRR/W0hTimestamp Higher Word Register
This field contains the most-significant 16-bits of timestamp seconds value. This register is optional. You can add this register by selecting the Add IEEE 1588 Higher Word Register option. This register is directly written to initialize the value and it is incremented when there is an overflow from 32-bits of the System Time Seconds register.
Access restriction applies. Updated based on the event. Setting 1 sets. Setting 0 clears.

43.7.3.177 MAC_Timestamp_Status Register (Offset = B20h) [Reset = 0h]

MAC_Timestamp_Status is shown in Figure 43-216 and described in Table 43-270.

Return to the Summary Table.

Timestamp Status register. All bits except Bits[27:25] gets cleared when the application reads this register.

Figure 43-216 MAC_Timestamp_Status Register
3130292827262524
RESERVEDATSNSATSSTM
R-0hR-0hR-0h
2322212019181716
RESERVEDATSSTN
R-0hR-0h
15141312111098
TXTSSISRESERVEDTSTRGTERR3TSTARGT3
R-0hR-0hR-0hR-0h
76543210
TSTRGTERR2TSTARGT2TSTRGTERR1TSTARGT1TSTRGTERR0AUXTSTRIGTSTARGT0TSSOVF
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-270 MAC_Timestamp_Status Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved.
29-25ATSNSR0hNumber of Auxiliary Timestamp Snapshots
This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected.
24ATSSTMR0hAuxiliary Timestamp Snapshot Trigger Missed
This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected.
0h = Auxiliary Timestamp Snapshot Trigger Missed status not detected : 0x0
1h = Auxiliary Timestamp Snapshot Trigger Missed status detected : 0x1
23-20RESERVEDR0hReserved.
19-16ATSSTNR0hAuxiliary Timestamp Snapshot Trigger Identifier
These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list:
- Bit 16: Auxiliary trigger 0
- Bit 17: Auxiliary trigger 1
- Bit 18: Auxiliary trigger 2
- Bit 19: Auxiliary trigger 3
The software can read this register to find the triggers that are set when the timestamp is taken.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
15TXTSSISR0hTx Timestamp Status Interrupt Status
In non-EQOS_CORE configurations when drop transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and MAC_Tx_Timestamp_Status_Seconds registers.
When PTP offload feature is enabled, this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and MAC_Tx_Timestamp_Status_Seconds registers, for PTO generated Delay Request and Pdelay request packets.
This bit is cleared when the MAC_Tx_Timestamp_Status_Seconds register is read (or write to MAC_Tx_Timestamp_Status_Seconds register when RCWE bit of MAC_CSR_SW_Ctrl register is set).
0h = Tx Timestamp Status Interrupt status not detected : 0x0
1h = Tx Timestamp Status Interrupt status detected : 0x1
14-10RESERVEDR0hReserved.
9TSTRGTERR3R0hTimestamp Target Time Error
This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Error status not detected : 0x0
1h = Timestamp Target Time Error status detected : 0x1
8TSTARGT3R0hTimestamp Target Time Reached for Target Time PPS3
When this bit is set, it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Reached for Target Time PPS3 status not detected : 0x0
1h = Timestamp Target Time Reached for Target Time PPS3 status detected : 0x1
7TSTRGTERR2R0hTimestamp Target Time Error
This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Error status not detected : 0x0
1h = Timestamp Target Time Error status detected : 0x1
6TSTARGT2R0hTimestamp Target Time Reached for Target Time PPS2
When set, this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Reached for Target Time PPS2 status not detected : 0x0
1h = Timestamp Target Time Reached for Target Time PPS2 status detected : 0x1
5TSTRGTERR1R0hTimestamp Target Time Error
This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Error status not detected : 0x0
1h = Timestamp Target Time Error status detected : 0x1
4TSTARGT1R0hTimestamp Target Time Reached for Target Time PPS1
When set, this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Reached for Target Time PPS1 status not detected : 0x0
1h = Timestamp Target Time Reached for Target Time PPS1 status detected : 0x1
3TSTRGTERR0R0hTimestamp Target Time Error
This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds
registers elapses. This bit is cleared when the application reads this bit.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Error status not detected : 0x0
1h = Timestamp Target Time Error status detected : 0x1
2AUXTSTRIGR0hAuxiliary Timestamp Trigger Snapshot
This bit is set high when the auxiliary snapshot is written to the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Auxiliary Timestamp Trigger Snapshot status not detected : 0x0
1h = Auxiliary Timestamp Trigger Snapshot status detected : 0x1
1TSTARGT0R0hTimestamp Target Time Reached
When set, this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Target Time Reached status not detected : 0x0
1h = Timestamp Target Time Reached status detected : 0x1
0TSSOVFR0hTimestamp Seconds Overflow
When this bit is set, it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
Access restriction applies. Clears on read (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event.
0h = Timestamp Seconds Overflow status not detected : 0x0
1h = Timestamp Seconds Overflow status detected : 0x1

43.7.3.178 MAC_Tx_Timestamp_Status_Nanoseconds Register (Offset = B30h) [Reset = 0h]

MAC_Tx_Timestamp_Status_Nanoseconds is shown in Figure 43-217 and described in Table 43-271.

Return to the Summary Table.

This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled.
The MAC_Tx_Timestamp_Status_Nanoseconds register, along with MAC_Tx_Timestamp_Status_Seconds, gives the 64-bit timestamp captured for the PTP packet successfully transmitted by the MAC. This value is considered to be read by the application when the last byte of MAC_Tx_Timestamp_Status_Nanoseconds is read. In the little-endian mode, this means when bits[31:24] are read
in big-endian mode, bits[7:0] are read.
If the application does not read these registers and timestamp of another packet is captured, then either the current timestamp is lost (overwritten) or the new timestamp is lost (dropped), depending on the setting of the TXTSSTSM bit of the MAC_Timestamp_Control register. The status bit TXTSC bit [15] in MAC_Timestamp_Status register is set whenever the MAC transmitter captures the timestamp.

Figure 43-217 MAC_Tx_Timestamp_Status_Nanoseconds Register
3130292827262524
TXTSSMISTXTSSLO
R-0hR-0h
2322212019181716
TXTSSLO
R-0h
15141312111098
TXTSSLO
R-0h
76543210
TXTSSLO
R-0h
Table 43-271 MAC_Tx_Timestamp_Status_Nanoseconds Register Field Descriptions
BitFieldTypeResetDescription
31TXTSSMISR0hTransmit Timestamp Status Missed
When this bit is set, it indicates one of the following:
- The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset
- The timestamp of the previous packet is overwritten with timestamp of the current packet if TXTSSTSM bit of the MAC_Timestamp_Control register is set.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Transmit Timestamp Status Missed status not detected : 0x0
1h = Transmit Timestamp Status Missed status detected : 0x1
30-0TXTSSLOR0hTransmit Timestamp Status Low
This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp.

43.7.3.179 MAC_Tx_Timestamp_Status_Seconds Register (Offset = B34h) [Reset = 0h]

MAC_Tx_Timestamp_Status_Seconds is shown in Figure 43-218 and described in Table 43-272.

Return to the Summary Table.

The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted.

Figure 43-218 MAC_Tx_Timestamp_Status_Seconds Register
313029282726252423222120191817161514131211109876543210
TXTSSHI
R-0h
Table 43-272 MAC_Tx_Timestamp_Status_Seconds Register Field Descriptions
BitFieldTypeResetDescription
31-0TXTSSHIR0hTransmit Timestamp Status High
This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp.

43.7.3.180 MAC_Auxiliary_Control Register (Offset = B40h) [Reset = 0h]

MAC_Auxiliary_Control is shown in Figure 43-219 and described in Table 43-273.

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The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot.

Figure 43-219 MAC_Auxiliary_Control Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDATSEN1ATSEN0RESERVEDATSFC
R-0hR-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-273 MAC_Auxiliary_Control Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved.
7RESERVEDR0hReserved.
6RESERVEDR0hReserved.
5ATSEN1R/W0hAuxiliary Snapshot 1 Enable
This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set, the auxiliary snapshot of the event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored.
0h = Auxiliary Snapshot $i is disabled : 0x0
1h = Auxiliary Snapshot $i is enabled : 0x1
4ATSEN0R/W0hAuxiliary Snapshot 0 Enable
This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set, the auxiliary snapshot of the event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored.
0h = Auxiliary Snapshot $i is disabled : 0x0
1h = Auxiliary Snapshot $i is enabled : 0x1
3-1RESERVEDR0hReserved.
0ATSFCR/W0hAuxiliary Snapshot FIFO Clear
When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, the auxiliary snapshots are stored in the FIFO.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Auxiliary Snapshot FIFO Clear is disabled : 0x0
1h = Auxiliary Snapshot FIFO Clear is enabled : 0x1

43.7.3.181 MAC_Auxiliary_Timestamp_Nanoseconds Register (Offset = B48h) [Reset = 0h]

MAC_Auxiliary_Timestamp_Nanoseconds is shown in Figure 43-220 and described in Table 43-274.

Return to the Summary Table.

The Auxiliary Timestamp Nanoseconds register, along with MAC_Auxiliary_Timestamp_Seconds, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4, 8, or 16 as selected while configuring the core.
You can store multiple snapshots in this FIFO. Bits[29:25] in MAC_Timestamp_Status indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read.

Figure 43-220 MAC_Auxiliary_Timestamp_Nanoseconds Register
3130292827262524
RESERVEDAUXTSLO
R-0hR-0h
2322212019181716
AUXTSLO
R-0h
15141312111098
AUXTSLO
R-0h
76543210
AUXTSLO
R-0h
Table 43-274 MAC_Auxiliary_Timestamp_Nanoseconds Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30-0AUXTSLOR0hAuxiliary Timestamp
Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp.

43.7.3.182 MAC_Auxiliary_Timestamp_Seconds Register (Offset = B4Ch) [Reset = 0h]

MAC_Auxiliary_Timestamp_Seconds is shown in Figure 43-221 and described in Table 43-275.

Return to the Summary Table.

The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register.

Figure 43-221 MAC_Auxiliary_Timestamp_Seconds Register
313029282726252423222120191817161514131211109876543210
AUXTSHI
R-0h
Table 43-275 MAC_Auxiliary_Timestamp_Seconds Register Field Descriptions
BitFieldTypeResetDescription
31-0AUXTSHIR0hAuxiliary Timestamp
Contains the lower 32 bits of the Seconds field of the auxiliary timestamp.

43.7.3.183 MAC_Timestamp_Ingress_Asym_Corr Register (Offset = B50h) [Reset = 0h]

MAC_Timestamp_Ingress_Asym_Corr is shown in Figure 43-222 and described in Table 43-276.

Return to the Summary Table.

The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages.

Figure 43-222 MAC_Timestamp_Ingress_Asym_Corr Register
313029282726252423222120191817161514131211109876543210
OSTIAC
R/W-0h
Table 43-276 MAC_Timestamp_Ingress_Asym_Corr Register Field Descriptions
BitFieldTypeResetDescription
31-0OSTIACR/W0hOne-Step Timestamp Ingress Asymmetry Correction
This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 216. For example, 2.5 ns is represented as 0x00028000.
The value can also be negative, which is represented in 2's complement form with bit 31 representing the sign bit.

43.7.3.184 MAC_Timestamp_Egress_Asym_Corr Register (Offset = B54h) [Reset = 0h]

MAC_Timestamp_Egress_Asym_Corr is shown in Figure 43-223 and described in Table 43-277.

Return to the Summary Table.

The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages.

Figure 43-223 MAC_Timestamp_Egress_Asym_Corr Register
313029282726252423222120191817161514131211109876543210
OSTEAC
R/W-0h
Table 43-277 MAC_Timestamp_Egress_Asym_Corr Register Field Descriptions
BitFieldTypeResetDescription
31-0OSTEACR/W0hOne-Step Timestamp Egress Asymmetry Correction
This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied by 216.
For example, if the required correction is +2.5 ns, the programmed value must be 0xFFFD_8000, which is the 2's complement of 0x0002_8000(2.5 * 216). Similarly, if the required correction is -3.3 ns, the programmed value is 0x0003_4CCC (3.3 * 216).

43.7.3.185 MAC_Timestamp_Ingress_Corr_Nanosecond Register (Offset = B58h) [Reset = 0h]

MAC_Timestamp_Ingress_Corr_Nanosecond is shown in Figure 43-224 and described in Table 43-278.

Return to the Summary Table.

This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path.

Figure 43-224 MAC_Timestamp_Ingress_Corr_Nanosecond Register
313029282726252423222120191817161514131211109876543210
TSIC
R/W-0h
Table 43-278 MAC_Timestamp_Ingress_Corr_Nanosecond Register Field Descriptions
BitFieldTypeResetDescription
31-0TSICR/W0hTimestamp Ingress Correction
This field contains the ingress path correction value as defined by the Ingress Correction expression.

43.7.3.186 MAC_Timestamp_Egress_Corr_Nanosecond Register (Offset = B5Ch) [Reset = 0h]

MAC_Timestamp_Egress_Corr_Nanosecond is shown in Figure 43-225 and described in Table 43-279.

Return to the Summary Table.

This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path.

Figure 43-225 MAC_Timestamp_Egress_Corr_Nanosecond Register
313029282726252423222120191817161514131211109876543210
TSEC
R/W-0h
Table 43-279 MAC_Timestamp_Egress_Corr_Nanosecond Register Field Descriptions
BitFieldTypeResetDescription
31-0TSECR/W0hTimestamp Egress Correction
This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression.

43.7.3.187 MAC_Timestamp_Ingress_Corr_Subnanosec Register (Offset = B60h) [Reset = 0h]

MAC_Timestamp_Ingress_Corr_Subnanosec is shown in Figure 43-226 and described in Table 43-280.

Return to the Summary Table.

This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value, for ingress direction.

Figure 43-226 MAC_Timestamp_Ingress_Corr_Subnanosec Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSICSNSRESERVED
R-0hR/W-0hR-0h
Table 43-280 MAC_Timestamp_Ingress_Corr_Subnanosec Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-8TSICSNSR/W0hTimestamp Ingress Correction, sub-nanoseconds
This field contains the sub-nanoseconds part of the ingress path correction value as defined by the "Ingress Correction" expression.
7-0RESERVEDR0hReserved.

43.7.3.188 MAC_Timestamp_Egress_Corr_Subnanosec Register (Offset = B64h) [Reset = 0h]

MAC_Timestamp_Egress_Corr_Subnanosec is shown in Figure 43-227 and described in Table 43-281.

Return to the Summary Table.

This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value, for egress direction.

Figure 43-227 MAC_Timestamp_Egress_Corr_Subnanosec Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSECSNSRESERVED
R-0hR/W-0hR-0h
Table 43-281 MAC_Timestamp_Egress_Corr_Subnanosec Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-8TSECSNSR/W0hTimestamp Egress Correction, sub-nanoseconds
This field contains the sub-nanoseconds part of the egress path correction value as defined by the "Egress Correction" expression.
7-0RESERVEDR0hReserved.

43.7.3.189 MAC_PPS_Control Register (Offset = B70h) [Reset = 0h]

MAC_PPS_Control is shown in Figure 43-228 and described in Table 43-282.

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PPS Control register.
Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected.

Figure 43-228 MAC_PPS_Control Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
15141312111098
RESERVEDTRGTMODSEL1RESERVEDPPSCMD1
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDTRGTMODSEL0PPSEN0PPSCTRL_PPSCMD
R-0hR/W-0hR/W-0hR/W-0h
Table 43-282 MAC_PPS_Control Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30-29RESERVEDR0hReserved.
28-27RESERVEDR0hReserved.
26-24RESERVEDR0hReserved.
23RESERVEDR0hReserved.
22-21RESERVEDR0hReserved.
20-19RESERVEDR0hReserved.
18-16RESERVEDR0hReserved.
15RESERVEDR0hReserved.
14-13TRGTMODSEL1R/W0hTarget Time Register Mode for PPS1 Output
This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal.
0h = Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding ptp_pps_o output port : 0x0
1h = Reserved : 0x1
2h = Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation : 0x2
3h = Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted : 0x3
12-11RESERVEDR0hReserved.
10-8PPSCMD1R/W0hFlexible PPS1 Output Control
This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to the PPSCMD0 field.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
7RESERVEDR0hReserved.
6-5TRGTMODSEL0R/W0hTarget Time Register Mode for PPS0 Output
This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal:
0h = Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding ptp_pps_o output port : 0x0
1h = Reserved : 0x1
2h = Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation : 0x2
3h = Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted : 0x3
4PPSEN0R/W0hFlexible PPS Output Mode Enable
When this bit is set, Bits[3:0] function as PPSCMD. When this bit is reset, Bits[3:0] function as PPSCTRL (Fixed PPS mode).
0h = Flexible PPS Output Mode is disabled : 0x0
1h = Flexible PPS Output Mode is enabled : 0x1
3-0PPSCTRL_PPSCMDR/W0hPPS Output Frequency Control
This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies:
- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz.
- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz.
- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz.
- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz.
- ..
- 1111: The binary rollover is 32.768 KHz and the digital rollover is 16.384 KHz.
Note:
In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies.
In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example:
- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms
- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of
One clock of 50 percent duty cycle and 537 ms period
Second clock of 463 ms period (268 ms low and 195 ms high)
- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of
Three clocks of 50 percent duty cycle and 268 ms period
Fourth clock of 195 ms period (134 ms low and 61 ms high)
This behavior is because of the non-linear toggling of bits in the digital rollover mode in the MAC_System_Time_Nanoseconds register.
or
Flexible PPS Output (ptp_pps_o[0]) Control
Programming these bits with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The software should ensure that these bits are programmed only when they are 'all-zero'. The following list describes the values of PPSCMD0:
- 0000: No Command
- 0001: START Single Pulse
This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS0 Width Register.
- 0010: START Pulse Train
This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS0 Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by the 'Stop Pulse train at time' or 'Stop Pulse Train immediately' commands.
- 0011: Cancel START
This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time.
- 0100: STOP Pulse train at time
This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses.
- 0101: STOP Pulse Train immediately
This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010).
- 0110: Cancel STOP Pulse train
This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command.
- 0111-1111: Reserved
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

43.7.3.190 MAC_PPS0_Target_Time_Seconds Register (Offset = B80h) [Reset = 0h]

MAC_PPS0_Target_Time_Seconds is shown in Figure 43-229 and described in Table 43-283.

Return to the Summary Table.

The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers.

Figure 43-229 MAC_PPS0_Target_Time_Seconds Register
313029282726252423222120191817161514131211109876543210
TSTRH0
R/W-0h
Table 43-283 MAC_PPS0_Target_Time_Seconds Register Field Descriptions
BitFieldTypeResetDescription
31-0TSTRH0R/W0hPPS Target Time Seconds Register
This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on Target Time mode selected for the corresponding PPS output in the MAC_PPS_Control register.

43.7.3.191 MAC_PPS0_Target_Time_Nanoseconds Register (Offset = B84h) [Reset = 0h]

MAC_PPS0_Target_Time_Nanoseconds is shown in Figure 43-230 and described in Table 43-284.

Return to the Summary Table.

PPS0 Target Time Nanoseconds register.

Figure 43-230 MAC_PPS0_Target_Time_Nanoseconds Register
3130292827262524
TRGTBUSY0TTSL0
R/W-0hR/W-0h
2322212019181716
TTSL0
R/W-0h
15141312111098
TTSL0
R/W-0h
76543210
TTSL0
R/W-0h
Table 43-284 MAC_PPS0_Target_Time_Nanoseconds Register Field Descriptions
BitFieldTypeResetDescription
31TRGTBUSY0R/W0hPPS Target Time Register Busy
The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain.
The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted.
0h = PPS Target Time Register Busy status is not detected : 0x0
1h = PPS Target Time Register Busy is detected : 0x1
30-0TTSL0R/W0hTarget Time Low for PPS Register
This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGTMODSEL0 field (Bits [6:5]) in MAC_PPS_Control.
When the TSCTRLSSR bit is reset in the MAC_Timestamp_Control register, this value should be (time in ns / 0.465). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value.
When the TSCTRLSSR bit is set in the MAC_Timestamp_Control register, this value should not exceed 0x3B9A_C9FF. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

43.7.3.192 MAC_PPS0_Interval Register (Offset = B88h) [Reset = 0h]

MAC_PPS0_Interval is shown in Figure 43-231 and described in Table 43-285.

Return to the Summary Table.

The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).

Figure 43-231 MAC_PPS0_Interval Register
313029282726252423222120191817161514131211109876543210
PPSINT0
R/W-0h
Table 43-285 MAC_PPS0_Interval Register Field Descriptions
BitFieldTypeResetDescription
31-0PPSINT0R/W0hPPS Output Signal Interval
These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value.
You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS0 signal output is 100 ns (that is, 5 units of sub-second increment value), you should program value 4 (5-1) in this register.

43.7.3.193 MAC_PPS0_Width Register (Offset = B8Ch) [Reset = 0h]

MAC_PPS0_Width is shown in Figure 43-232 and described in Table 43-286.

Return to the Summary Table.

The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0]).

Figure 43-232 MAC_PPS0_Width Register
313029282726252423222120191817161514131211109876543210
PPSWIDTH0
R/W-0h
Table 43-286 MAC_PPS0_Width Register Field Descriptions
BitFieldTypeResetDescription
31-0PPSWIDTH0R/W0hPPS Output Signal Width
These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value.
You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20 ns), and width between the rising and corresponding falling edges of PPS0 signal output is 80 ns (that is, four units of sub-second increment value), you should program value 3 (4-1) in this register.
Note: The value programmed in this register must be lesser than the value programmed in MAC_PPS0_Interval.

43.7.3.194 MAC_PPS1_Target_Time_Seconds Register (Offset = B90h) [Reset = 0h]

MAC_PPS1_Target_Time_Seconds is shown in Figure 43-233 and described in Table 43-287.

Return to the Summary Table.

The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers.

Figure 43-233 MAC_PPS1_Target_Time_Seconds Register
313029282726252423222120191817161514131211109876543210
TSTRH1
R/W-0h
Table 43-287 MAC_PPS1_Target_Time_Seconds Register Field Descriptions
BitFieldTypeResetDescription
31-0TSTRH1R/W0hPPS Target Time Seconds Register
This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on Target Time mode selected for the corresponding PPS output in the MAC_PPS_Control register.

43.7.3.195 MAC_PPS1_Target_Time_Nanoseconds Register (Offset = B94h) [Reset = 0h]

MAC_PPS1_Target_Time_Nanoseconds is shown in Figure 43-234 and described in Table 43-288.

Return to the Summary Table.

PPS0 Target Time Nanoseconds register.

Figure 43-234 MAC_PPS1_Target_Time_Nanoseconds Register
3130292827262524
TRGTBUSY1TTSL1
R/W-0hR/W-0h
2322212019181716
TTSL1
R/W-0h
15141312111098
TTSL1
R/W-0h
76543210
TTSL1
R/W-0h
Table 43-288 MAC_PPS1_Target_Time_Nanoseconds Register Field Descriptions
BitFieldTypeResetDescription
31TRGTBUSY1R/W0hPPS Target Time Register Busy
The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain.
The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted.
0h = PPS Target Time Register Busy status is not detected : 0x0
1h = PPS Target Time Register Busy is detected : 0x1
30-0TTSL1R/W0hTarget Time Low for PPS Register
This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGTMODSEL0 field (Bits [6:5]) in MAC_PPS_Control.
When the TSCTRLSSR bit is reset in the MAC_Timestamp_Control register, this value should be (time in ns / 0.465). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value.
When the TSCTRLSSR bit is set in the MAC_Timestamp_Control register, this value should not exceed 0x3B9A_C9FF. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

43.7.3.196 MAC_PPS1_Interval Register (Offset = B98h) [Reset = 0h]

MAC_PPS1_Interval is shown in Figure 43-235 and described in Table 43-289.

Return to the Summary Table.

The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).

Figure 43-235 MAC_PPS1_Interval Register
313029282726252423222120191817161514131211109876543210
PPSINT1
R/W-0h
Table 43-289 MAC_PPS1_Interval Register Field Descriptions
BitFieldTypeResetDescription
31-0PPSINT1R/W0hPPS Output Signal Interval
These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value.
You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20 ns), and desired interval between the rising edges of PPS0 signal output is 100 ns (that is, 5 units of sub-second increment value), you should program value 4 (5-1) in this register.

43.7.3.197 MAC_PPS1_Width Register (Offset = B9Ch) [Reset = 0h]

MAC_PPS1_Width is shown in Figure 43-236 and described in Table 43-290.

Return to the Summary Table.

The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0]).

Figure 43-236 MAC_PPS1_Width Register
313029282726252423222120191817161514131211109876543210
PPSWIDTH1
R/W-0h
Table 43-290 MAC_PPS1_Width Register Field Descriptions
BitFieldTypeResetDescription
31-0PPSWIDTH1R/W0hPPS Output Signal Width
These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value.
You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20 ns), and width between the rising and corresponding falling edges of PPS0 signal output is 80 ns (that is, four units of sub-second increment value), you should program value 3 (4-1) in this register.
Note: The value programmed in this register must be lesser than the value programmed in MAC_PPS0_Interval.

43.7.3.198 MAC_PTO_Control Register (Offset = BC0h) [Reset = 0h]

MAC_PTO_Control is shown in Figure 43-237 and described in Table 43-291.

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This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Figure 43-237 MAC_PTO_Control Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
DN
R/W-0h
76543210
PDRDISDRRDISAPDREQTRIGASYNCTRIGRESERVEDAPDREQENASYNCENPTOEN
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-291 MAC_PTO_Control Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-8DNR/W0hDomain Number
This field indicates the domain Number in which the PTP node is operating.

7PDRDISR/W0hDisable Peer Delay Response response generation
When this bit is set, the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet, as required by the programmed mode.
Note: Setting this bit to 1 affects the normal PTP Offload operation and the time synchronization. So, this bit must be set only if there is problem with Pdelay_Resp generation in Hardware and/or Pdelay_Resp generation is handled by Software.

0h = Peer Delay Response response generation is enabled : 0x0
1h = Peer Delay Response response generation is disabled : 0x1
6DRRDISR/W0hDisable PTO Delay Request/Response response generation
When this bit is set, the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively, as required by the programmed mode.


0h = PTO Delay Request/Response response generation is enabled : 0x0
1h = PTO Delay Request/Response response generation is disabled : 0x1
5APDREQTRIGR/W0hAutomatic PTP Pdelay_Req message Trigger
When this bit is set, one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this operation.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

0h = Automatic PTP Pdelay_Req message Trigger is disabled : 0x0
1h = Automatic PTP Pdelay_Req message Trigger is enabled : 0x1
4ASYNCTRIGR/W0hAutomatic PTP SYNC message Trigger
When this bit is set, one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

0h = Automatic PTP SYNC message Trigger is disabled : 0x0
1h = Automatic PTP SYNC message Trigger is enabled : 0x1
3RESERVEDR0hReserved.
2APDREQENR/W0hAutomatic PTP Pdelay_Req message Enable
When this bit is set, PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Peer-to-Peer Transparent mode.


0h = Automatic PTP Pdelay_Req message is disabled : 0x0
1h = Automatic PTP Pdelay_Req message is enabled : 0x1
1ASYNCENR/W0hAutomatic PTP SYNC message Enable
When this bit is set, PTP SYNC message is generated periodically based on interval programmed or trigger from application, when the MAC is programmed to be in Clock Master mode.


0h = Automatic PTP SYNC message is disabled : 0x0
1h = Automatic PTP SYNC message is enabled : 0x1
0PTOENR/W0hPTP Offload Enable
When this bit is set, the PTP Offload feature is enabled.


0h = PTP Offload feature is disabled : 0x0
1h = PTP Offload feature is enabled : 0x1

43.7.3.199 MAC_Source_Port_Identity0 Register (Offset = BC4h) [Reset = 0h]

MAC_Source_Port_Identity0 is shown in Figure 43-238 and described in Table 43-292.

Return to the Summary Table.

This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Figure 43-238 MAC_Source_Port_Identity0 Register
313029282726252423222120191817161514131211109876543210
SPI0
R/W-0h
Table 43-292 MAC_Source_Port_Identity0 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPI0R/W0hSource Port Identity 0
This field indicates bits [31:0] of sourcePortIdentity of PTP node.

43.7.3.200 MAC_Source_Port_Identity1 Register (Offset = BC8h) [Reset = 0h]

MAC_Source_Port_Identity1 is shown in Figure 43-239 and described in Table 43-293.

Return to the Summary Table.

This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Figure 43-239 MAC_Source_Port_Identity1 Register
313029282726252423222120191817161514131211109876543210
SPI1
R/W-0h
Table 43-293 MAC_Source_Port_Identity1 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPI1R/W0hSource Port Identity 1
This field indicates bits [63:32] of sourcePortIdentity of PTP node.

43.7.3.201 MAC_Source_Port_Identity2 Register (Offset = BCCh) [Reset = 0h]

MAC_Source_Port_Identity2 is shown in Figure 43-240 and described in Table 43-294.

Return to the Summary Table.

This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Figure 43-240 MAC_Source_Port_Identity2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSPI2
R-0hR/W-0h
Table 43-294 MAC_Source_Port_Identity2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15-0SPI2R/W0hSource Port Identity 2
This field indicates bits [79:64] of sourcePortIdentity of PTP node.

43.7.3.202 MAC_Log_Message_Interval Register (Offset = BD0h) [Reset = 0h]

MAC_Log_Message_Interval is shown in Figure 43-241 and described in Table 43-295.

Return to the Summary Table.


This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Figure 43-241 MAC_Log_Message_Interval Register
31302928272625242322212019181716
LMPDRIRESERVED
R/W-0hR-0h
1514131211109876543210
RESERVEDDRSYNCRLSI
R-0hR/W-0hR/W-0h
Table 43-295 MAC_Log_Message_Interval Register Field Descriptions
BitFieldTypeResetDescription
31-24LMPDRIR/W0hLog Min Pdelay_Req Interval
This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF.
23-11RESERVEDR0hReserved.
10-8DRSYNCRR/W0h
Delay_Req to SYNC Ratio
In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
- 0: DelayReq generated for every received SYNC
- 1: DelayReq generated every alternate reception of SYNC
- 2: for every 4 SYNC messages
- 3: for every 8 SYNC messages
- 4: for every 16 SYNC messages
- 5: for every 32 SYNC messages
- 6-7: Reserved
The master sends this information (logMinDelayReqInterval) in the DelayResp PTP messages to the slave. The DWC_ether_qos Receiver processes this value from the received DelayResp messages and updates this field accordingly. In the Slave mode, the host must not write/update this register unless it has to override the received value. In Master mode, the sum of this field and logSyncInterval (LSI) field is provided in the logMinDelayReqInterval field of the generated multicast Delay_Resp PTP message.
Access restriction applies. Updated based on the event. Setting 1 sets. Setting 0 clears.
0h = DelayReq generated for every received SYNC : 0x0
1h = DelayReq generated every alternate reception of SYNC : 0x1
2h = for every 4 SYNC messages : 0x2
3h = for every 8 SYNC messages : 0x3
4h = for every 16 SYNC messages : 0x4
5h = for every 32 SYNC messages : 0x5
6h = Reserved : 0x6
7-0LSIR/W0h
Log Sync Interval
This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example, if the required value is -1, the value programmed must be 0xFF.

43.7.3.203 MTL_Operation_Mode Register (Offset = C00h) [Reset = 0h]

MTL_Operation_Mode is shown in Figure 43-242 and described in Table 43-296.

Return to the Summary Table.

The Operation Mode register establishes the Transmit and Receive operating modes and commands.

Figure 43-242 MTL_Operation_Mode Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCNTCLRCNTPRST
R-0hR/W-0hR/W-0h
76543210
RESERVEDSCHALGRESERVEDRAADTXSTSRESERVED
R-0hR/W-0hR-0hR/W-0hR/W-0hR-0h
Table 43-296 MTL_Operation_Mode Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved.
9CNTCLRR/W0hCounters Reset
When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.
If this bit is set along with CNT_PRESET bit, CNT_PRESET has precedence.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Counters are not reset : 0x0
1h = All counters are reset : 0x1
8CNTPRSTR/W0hCounters Preset
When this bit is set,
- MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
- Missed Packet and Overflow Packet counters in MTL_RxQ[0-7]_Missed_Packet_Overflow_Cnt register is initialized/preset to 12'h7F0.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Counters Preset is disabled : 0x0
1h = Counters Preset is enabled : 0x1
7RESERVEDR0hReserved.
6-5SCHALGR/W0hTx Scheduling Algorithm
This field indicates the algorithm for Tx scheduling:
0h = WRR algorithm : 0x0
1h = WFQ algorithm when DCB feature is selected.Otherwise, Reserved : 0x1
2h = DWRR algorithm when DCB feature is selected.Otherwise, Reserved : 0x2
3h = Strict priority algorithm : 0x3
4-3RESERVEDR0hReserved.
2RAAR/W0hReceive Arbitration Algorithm
This field is used to select the arbitration algorithm for the Rx side.
- 0: Strict priority (SP)
Queue 0 has the lowest priority and the last queue has the highest priority.
- 1: Weighted Strict Priority (WSP)

0h = Strict priority (SP) : 0x0
1h = Weighted Strict Priority (WSP) : 0x1
1DTXSTSR/W0hDrop Transmit Status
When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset, the Tx packet status received from the MAC is forwarded to the application.
0h = Drop Transmit Status is disabled : 0x0
1h = Drop Transmit Status is enabled : 0x1
0RESERVEDR0hReserved.

43.7.3.204 MTL_DBG_CTL Register (Offset = C08h) [Reset = 0h]

MTL_DBG_CTL is shown in Figure 43-243 and described in Table 43-297.

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The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access.

Figure 43-243 MTL_DBG_CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
STSIEPKTIEFIFOSELFIFOWRENFIFORDENRSTSELRSTALL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDPKTSTATERESERVEDBYTEENDBGMODFDBGEN
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-297 MTL_DBG_CTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15STSIER/W0hTransmit Status Available Interrupt Status Enable
When this bit is set, an interrupt is generated when Transmit status is available in slave mode.
0h = Transmit Packet Available Interrupt Status is disabled : 0x0
1h = Transmit Packet Available Interrupt Status is enabled : 0x1
14PKTIER/W0hReceive Packet Available Interrupt Status Enable
When this bit is set, an interrupt is generated when EOP of received packet is written to the Rx FIFO.
0h = Receive Packet Available Interrupt Status is disabled : 0x0
1h = Receive Packet Available Interrupt Status is enabled : 0x1
13-12FIFOSELR/W0hFIFO Selected for Access
This field indicates the FIFO selected for debug access:
0h = Tx FIFO : 0x0
1h = Tx Status FIFO (only read access when SLVMOD is set) : 0x1
2h = TSO FIFO (cannot be accessed when SLVMOD is set) : 0x2
3h = Rx FIFO : 0x3
11FIFOWRENR/W0hFIFO Write Enable
When this bit is set, it enables the Write operation on selected FIFO when FIFO Debug Access is enabled.
This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.
Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.
0h = FIFO Write is disabled : 0x0
1h = FIFO Write is enabled : 0x1
10FIFORDENR/W0hFIFO Read Enable
When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.
Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.
0h = FIFO Read is disabled : 0x0
1h = FIFO Read is enabled : 0x1
9RSTSELR/W0hReset Pointers of Selected FIFO
When this bit is set, the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled.
This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.
Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.
0h = Reset Pointers of Selected FIFO is disabled : 0x0
1h = Reset Pointers of Selected FIFO is enabled : 0x1
8RSTALLR/W0hReset All Pointers
When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0.
Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets.
0h = Reset All Pointers is disabled : 0x0
1h = Reset All Pointers is enabled : 0x1
7RESERVEDR0hReserved.
6-5PKTSTATER/W0hEncoded Packet State
This field is used to write the control information to the Tx FIFO or Rx FIFO.
Tx FIFO:
- 00: Packet Data
- 01: Control Word
- 10: SOP Data
- 11: EOP Data
Rx FIFO:
- 00: Packet Data
- 01: Normal Status
- 10: Last Status
- 11: EOP
0h = Packet Data : 0x0
1h = Control Word/Normal Status : 0x1
2h = SOP Data/Last Status : 0x2
3h = EOP Data/EOP : 0x3
4RESERVEDR0hReserved.
3-2BYTEENR/W0hByte Enables
This field indicates the number of data bytes valid in the data register during Write operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected.
0h = Byte 0 valid : 0x0
1h = Byte 0 and Byte 1 are valid : 0x1
2h = Byte 0, Byte 1, and Byte 2 are valid : 0x2
3h = All four bytes are valid : 0x3
1DBGMODR/W0hDebug Mode Access to FIFO
When this bit is set, it indicates that the current access to the FIFO is read, write, and debug access. In this mode, the following access types are allowed:
- Read and Write access to Tx FIFO, TSO FIFO, and Rx FIFO
- Read access is allowed to Tx Status FIFO.
When this bit is reset, it indicates that the current access to the FIFO is slave access bypassing the DMA. In this mode, the following access are allowed:
- Write access to the Tx FIFO
- Read access to the Rx FIFO and Tx Status FIFO

0h = Debug Mode Access to FIFO is disabled : 0x0
1h = Debug Mode Access to FIFO is enabled : 0x1
0FDBGENR/W0hFIFO Debug Access Enable
When this bit is set, it indicates that the debug mode access to the FIFO is enabled. When this bit is reset, it indicates that the FIFO can be accessed only through a master interface.
0h = FIFO Debug Access is disabled : 0x0
1h = FIFO Debug Access is enabled : 0x1

43.7.3.205 MTL_DBG_STS Register (Offset = C0Ch) [Reset = 18h]

MTL_DBG_STS is shown in Figure 43-244 and described in Table 43-298.

Return to the Summary Table.

The FIFO Debug Status register contains the status of FIFO debug access.

Figure 43-244 MTL_DBG_STS Register
3130292827262524
LOCR
R-0h
2322212019181716
LOCR
R-0h
15141312111098
LOCRRESERVEDSTSIPKTI
R-0hR-0hR/W-0hR/W-0h
76543210
RESERVEDBYTEENPKTSTATEFIFOBUSY
R-0hR-3hR-0hR-0h
Table 43-298 MTL_DBG_STS Register Field Descriptions
BitFieldTypeResetDescription
31-15LOCRR0hRemaining Locations in the FIFO
Slave Access Mode:
This field indicates the space available in selected FIFO.
Debug Access Mode:
This field contains the Write or Read pointer value of the selected FIFO during Write or Read operation, respectively.
Reset: In single Tx Queue configurations, (DWC_EQOS_TXFIFO_SIZE/(DWC_EQOS_DATAWIDTH/8)), Otherwise 0000H
14-10RESERVEDR0hReserved.
9STSIR/W0hTransmit Status Available Interrupt Status
When set, this bit indicates that the Slave mode Tx packet is transmitted, and the status is available in Tx Status FIFO. This bit is reset when 1 is written to this bit.
0h = Transmit Status Available Interrupt Status not detected : 0x0
1h = Transmit Status Available Interrupt Status detected : 0x1
8PKTIR/W0hReceive Packet Available Interrupt Status
When set, this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO. This bit is reset when 1 is written to this bit.
0h = Receive Packet Available Interrupt Status not detected : 0x0
1h = Receive Packet Available Interrupt Status detected : 0x1
7-5RESERVEDR0hReserved.
4-3BYTEENR3hByte Enables
This field indicates the number of data bytes valid in the data register during Read operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected.
0h = Byte 0 valid : 0x0
1h = Byte 0 and Byte 1 are valid : 0x1
2h = Byte 0, Byte 1, and Byte 2 are valid : 0x2
3h = All four bytes are valid : 0x3
2-1PKTSTATER0hEncoded Packet State
This field is used to get the control or status information of the selected FIFO.
Tx FIFO:
- 00: Packet Data
- 01: Control Word
- 10: SOP Data
- 11: EOP Data
Rx FIFO:
- 00: Packet Data
- 01: Normal Status
- 10: Last Status
- 11: EOP
This field is applicable only for Tx FIFO and Rx FIFO during Read operation.
0h = Packet Data : 0x0
1h = Control Word/Normal Status : 0x1
2h = SOP Data/Last Status : 0x2
3h = EOP Data/EOP : 0x3
0FIFOBUSYR0hFIFO Busy
When set, this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid:
- All other fields of this register
- All fields of the MTL_FIFO_Debug_Data register
0h = FIFO Busy not detected : 0x0
1h = FIFO Busy detected : 0x1

43.7.3.206 MTL_FIFO_Debug_Data Register (Offset = C10h) [Reset = 0h]

MTL_FIFO_Debug_Data is shown in Figure 43-245 and described in Table 43-299.

Return to the Summary Table.

The FIFO Debug Data register contains the data to be written to or read from the FIFOs.

Figure 43-245 MTL_FIFO_Debug_Data Register
313029282726252423222120191817161514131211109876543210
FDBGDATA
R/W-0h
Table 43-299 MTL_FIFO_Debug_Data Register Field Descriptions
BitFieldTypeResetDescription
31-0FDBGDATAR/W0hFIFO Debug Data
During debug or slave access write operation, this field contains the data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO. During debug or slave access read operation, this field contains the data read from the Tx FIFO, Rx FIFO, TSO FIFO, or Tx Status FIFO.

43.7.3.207 MTL_Interrupt_Status Register (Offset = C20h) [Reset = 0h]

MTL_Interrupt_Status is shown in Figure 43-246 and described in Table 43-300.

Return to the Summary Table.

The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.

Figure 43-246 MTL_Interrupt_Status Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDDBGISRESERVED
R-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDQ1ISQ0IS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-300 MTL_Interrupt_Status Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved.
18RESERVEDR0hReserved.
17DBGISR0hDebug Interrupt status
This bit indicates an interrupt event during the slave access. To reset this bit, the application must read the FIFO Debug Access Status register to get the exact cause of the interrupt and clear its source.
0h = Debug Interrupt status not detected : 0x0
1h = Debug Interrupt status detected : 0x1
16RESERVEDR0hReserved.
15-8RESERVEDR0hReserved.
7RESERVEDR0hReserved.
6RESERVEDR0hReserved.
5RESERVEDR0hReserved.
4RESERVEDR0hReserved.
3RESERVEDR0hReserved.
2RESERVEDR0hReserved.
1Q1ISR0hQueue 1 Interrupt status
This bit indicates that there is an interrupt from Queue 1. To reset this bit, the application must read the MTL_Q1_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source.
0h = Queue 1 Interrupt status not detected : 0x0
1h = Queue 1 Interrupt status detected : 0x1
0Q0ISR0hQueue 0 Interrupt status
This bit indicates that there is an interrupt from Queue 0. To reset this bit, the application must read Queue 0 Interrupt Control and Status register to get the exact cause of the interrupt and clear its source.
0h = Queue 0 Interrupt status not detected : 0x0
1h = Queue 0 Interrupt status detected : 0x1

43.7.3.208 MTL_RxQ_DMA_Map0 Register (Offset = C30h) [Reset = 0h]

MTL_RxQ_DMA_Map0 is shown in Figure 43-247 and described in Table 43-301.

Return to the Summary Table.

The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations.

Figure 43-247 MTL_RxQ_DMA_Map0 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
15141312111098
RESERVEDQ1DDMACHRESERVEDQ1MDMACH
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDQ0DDMACHRESERVEDQ0MDMACH
R-0hR/W-0hR-0hR/W-0h
Table 43-301 MTL_RxQ_DMA_Map0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28RESERVEDR0hReserved.
27-25RESERVEDR0hReserved.
24RESERVEDR0hReserved.
23-21RESERVEDR0hReserved.
20RESERVEDR0hReserved.
19-17RESERVEDR0hReserved.
16RESERVEDR0hReserved.
15-13RESERVEDR0hReserved.
12Q1DDMACHR/W0hQueue 1 Enabled for DA-based DMA Channel Selection
When set, this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.
When reset, this bit indicates that the packets received in Queue 1 are routed to the DMA Channel programmed in the Q1MDMACH field (Bits[10:8]).
0h = Queue 1 disabled for DA-based DMA Channel Selection : 0x0
1h = Queue 1 enabled for DA-based DMA Channel Selection : 0x1
11-9RESERVEDR0hReserved.
8Q1MDMACHR/W0hQueue 1 Mapped to DMA Channel
This field controls the routing of the received packet in Queue 1 to the DMA channel:
- 000: DMA Channel 0
- 001: DMA Channel 1
- 010: DMA Channel 2
- 011: DMA Channel 3
- 100: DMA Channel 4
- 101: DMA Channel 5
- 110: DMA Channel 6
- 111: DMA Channel 7
This field is valid when the Q1DDMACH field is reset.
The width of this field depends on the number of RX DMA channels and not all the values may be valid in some configurations. For example, if the number of RX DMA channels selected is 2, only 000 and 001 are valid, the other bits are reserved.
7-5RESERVEDR0hReserved.
4Q0DDMACHR/W0hQueue 0 Enabled for DA-based DMA Channel Selection
When set, this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the Ethernet DA address.
When reset, this bit indicates that the packets received in Queue 0 are routed to the DMA Channel programmed in the Q0MDMACH field.
0h = Queue 0 disabled for DA-based DMA Channel Selection : 0x0
1h = Queue 0 enabled for DA-based DMA Channel Selection : 0x1
3-1RESERVEDR0hReserved.
0Q0MDMACHR/W0hQueue 0 Mapped to DMA Channel
This field controls the routing of the packet received in Queue 0 to the DMA channel:
- 000: DMA Channel 0
- 001: DMA Channel 1
- 010: DMA Channel 2
- 011: DMA Channel 3
- 100: DMA Channel 4
- 101: DMA Channel 5
- 110: DMA Channel 6
- 111: DMA Channel 7
This field is valid when the Q0DDMACH field is reset.
The width of this field depends on the number of RX DMA channels and not all the values may be valid in some configurations. For example, if the number of RX DMA channels selected is 2, only 000 and 001 are valid, the other bits are reserved.

43.7.3.209 MTL_TxQ0_Operation_Mode Register (Offset = D00h) [Reset = 0h]

MTL_TxQ0_Operation_Mode is shown in Figure 43-248 and described in Table 43-302.

Return to the Summary Table.

The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands.

Figure 43-248 MTL_TxQ0_Operation_Mode Register
31302928272625242322212019181716
RESERVEDTQS
R-0hR/W-0h
1514131211109876543210
RESERVEDTTCTXQENTSFFTQ
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-302 MTL_TxQ0_Operation_Mode Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved.
19-16TQSR/W0hTransmit Queue Size
This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one, the reset value is 0x0 and indicates size of 256 bytes.
When the number of Tx Queues is one, the field is read-only and the configured TX FIFO size in blocks of 256 bytes is reflected in the reset value.
The width of this field depends on the Tx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits:
LOG2(2048/256) = LOG2(8) = 3 bits
15-7RESERVEDR0hReserved.
6-4TTCR/W0hTransmit Threshold Control
These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset.
0h = 32 : 0x0
1h = 64 : 0x1
2h = 96 : 0x2
3h = 128 : 0x3
4h = 192 : 0x4
5h = 256 : 0x5
6h = 384 : 0x6
7h = 512 : 0x7
3-2TXQENR/W0hTransmit Queue Enable
This field is used to enable/disable the transmit queue 0.
- 2'b00: Not enabled
- 2'b01: Reserved
- 2'b10: Enabled
- 2'b11: Reserved
This field is Read Only in Single Queue configurations and Read Write in Multiple Queue configurations.
Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field.
0h = Not enabled : 0x0
1h = Enable in AV mode(Reserved in non-AV) : 0x1
2h = Enabled : 0x2
3h = Reserved : 0x3
1TSFR/W0hTransmit Store and Forward
When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped.
0h = Transmit Store and Forward is disabled : 0x0
1h = Transmit Store and Forward is enabled : 0x1
0FTQR/W0hFlush Transmit Queue
When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the MTL_TxQ1_Operation_Mode register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission.
Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (clk_tx_i) should be active.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Flush Transmit Queue is disabled : 0x0
1h = Flush Transmit Queue is enabled : 0x1

43.7.3.210 MTL_TxQ0_Underflow Register (Offset = D04h) [Reset = 0h]

MTL_TxQ0_Underflow is shown in Figure 43-249 and described in Table 43-303.

Return to the Summary Table.

The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush

Figure 43-249 MTL_TxQ0_Underflow Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUFCNTOVFUFFRMCNT
R-0hR-0hR-0h
76543210
UFFRMCNT
R-0h
Table 43-303 MTL_TxQ0_Underflow Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved.
11UFCNTOVFR0hOverflow Bit for Underflow Packet Counter
This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Overflow not detected for Underflow Packet Counter : 0x0
1h = Overflow detected for Underflow Packet Counter : 0x1
10-0UFFRMCNTR0hUnderflow Packet Counter
This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read with mci_be_i[0] at 1'b1.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

43.7.3.211 MTL_TxQ0_Debug Register (Offset = D08h) [Reset = 0h]

MTL_TxQ0_Debug is shown in Figure 43-250 and described in Table 43-304.

Return to the Summary Table.

The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue.

Figure 43-250 MTL_TxQ0_Debug Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSTXSTSFRESERVEDPTXQ
R-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTXSTSFSTSTXQSTSTWCSTSTRCSTSTXQPAUSED
R-0hR-0hR-0hR-0hR-0hR-0h
Table 43-304 MTL_TxQ0_Debug Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved.
22-20STXSTSFR0hNumber of Status Words in Tx Status FIFO of Queue
This field indicates the current number of status in the Tx Status FIFO of this queue.
When the DTXSTS bit of MTL_Operation_Mode register is set to 1, this field does not reflect the number of status words in Tx Status FIFO.
19RESERVEDR0hReserved.
18-16PTXQR0hNumber of Packets in the Transmit Queue
This field indicates the current number of packets in the Tx Queue.
When the DTXSTS bit of MTL_Operation_Mode register is set to 1, this field does not reflect the number of packets in the Transmit queue.
15-6RESERVEDR0hReserved.
5TXSTSFSTSR0hMTL Tx Status FIFO Full Status
When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission.
0h = MTL Tx Status FIFO Full status is not detected : 0x0
1h = MTL Tx Status FIFO Full status is detected : 0x1
4TXQSTSR0hMTL Tx Queue Not Empty Status
When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission.
0h = MTL Tx Queue Not Empty status is not detected : 0x0
1h = MTL Tx Queue Not Empty status is detected : 0x1
3TWCSTSR0hMTL Tx Queue Write Controller Status
When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue.
0h = MTL Tx Queue Write Controller status is not detected : 0x0
1h = MTL Tx Queue Write Controller status is detected : 0x1
2-1TRCSTSR0hMTL Tx Queue Read Controller Status
This field indicates the state of the Tx Queue Read Controller:
0h = Idle state : 0x0
1h = Read state (transferring data to the MAC transmitter) : 0x1
2h = Waiting for pending Tx Status from the MAC transmitter : 0x2
3h = Flushing the Tx queue because of the Packet Abort request from the MAC : 0x3
0TXQPAUSEDR0hTransmit Queue in Pause
When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following:
- Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled
- Reception of 802.3x Pause packet when PFC is disabled
0h = Transmit Queue in Pause status is not detected : 0x0
1h = Transmit Queue in Pause status is detected : 0x1

43.7.3.212 MTL_TxQ0_ETS_Status Register (Offset = D14h) [Reset = 0h]

MTL_TxQ0_ETS_Status is shown in Figure 43-251 and described in Table 43-305.

Return to the Summary Table.

The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0.

Figure 43-251 MTL_TxQ0_ETS_Status Register
313029282726252423222120191817161514131211109876543210
RESERVEDABS
R-0hR-0h
Table 43-305 MTL_TxQ0_ETS_Status Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23-0ABSR0hAverage Bits per Slot
This field contains the average transmitted bits per slot.
When the DCB operation is enabled for Queue 0, this field is computed over every 10 million bit times slot (4 ms in 2500 Mbps
10 ms in 1000 Mbps
100 ms in 100 Mbps). The maximum value is 0x989680.

43.7.3.213 MTL_TxQ0_Quantum_Weight Register (Offset = D18h) [Reset = 0h]

MTL_TxQ0_Quantum_Weight is shown in Figure 43-252 and described in Table 43-306.

Return to the Summary Table.

The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR), weights for the Weighted Round Robin (WRR), and Weighted Fair Queuing (WFQ) for Queue 0.

Figure 43-252 MTL_TxQ0_Quantum_Weight Register
313029282726252423222120191817161514131211109876543210
RESERVEDISCQW
R-0hR/W-0h
Table 43-306 MTL_TxQ0_Quantum_Weight Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved.
20-0ISCQWR/W0hQuantum or Weights
When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic, this field contains the quantum value in bytes to be added to credit during every queue scanning cycle. The maximum value is 0x1312D0 bytes.
When DCB operation is enabled with WFQ algorithm for Queue 0 traffic, this field contains the weight for this queue. The maximum value is 0x3FFF where weight of 0 indicates 100% bandwidth. Bits[20:14] must be written to zero. The higher the programmed weights lesser the bandwidth allocated for the particular Transmit Queue. This is because the weights are used to compute the packet finish time (weights*packet_size). Lesser the finish time, higher the probability of the packet getting scheduled first and using more bandwidth.
When DCB operation or generic queuing operation is enabled with WRR algorithm for Queue 0 traffic, this field contains the weight for this queue. The maximum value is 0x64.
Bits [20:7] must be written to zero.

43.7.3.214 MTL_Q0_Interrupt_Control_Status Register (Offset = D2Ch) [Reset = 0h]

MTL_Q0_Interrupt_Control_Status is shown in Figure 43-253 and described in Table 43-307.

Return to the Summary Table.

This register contains the interrupt enable and status bits for the queue 0 interrupts.

Figure 43-253 MTL_Q0_Interrupt_Control_Status Register
3130292827262524
RESERVEDRXOIE
R-0hR/W-0h
2322212019181716
RESERVEDRXOVFIS
R-0hR/W-0h
15141312111098
RESERVEDABPSIETXUIE
R-0hR/W-0hR/W-0h
76543210
RESERVEDABPSISTXUNFIS
R-0hR/W-0hR/W-0h
Table 43-307 MTL_Q0_Interrupt_Control_Status Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved.
24RXOIER/W0hReceive Queue Overflow Interrupt Enable
When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled.
0h = Receive Queue Overflow Interrupt is disabled : 0x0
1h = Receive Queue Overflow Interrupt is enabled : 0x1
23-17RESERVEDR0hReserved.
16RXOVFISR/W0hReceive Queue Overflow Interrupt Status
This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Queue Overflow Interrupt Status not detected : 0x0
1h = Receive Queue Overflow Interrupt Status detected : 0x1
15-10RESERVEDR0hReserved.
9ABPSIER/W0hAverage Bits Per Slot Interrupt Enable
When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
When this bit is cleared, the interrupt is not asserted for such an event.
0h = Average Bits Per Slot Interrupt is disabled : 0x0
1h = Average Bits Per Slot Interrupt is enabled : 0x1
8TXUIER/W0hTransmit Queue Underflow Interrupt Enable
When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled.
0h = Transmit Queue Underflow Interrupt Status is disabled : 0x0
1h = Transmit Queue Underflow Interrupt Status is enabled : 0x1
7-2RESERVEDR0hReserved.
1ABPSISR/W0hAverage Bits Per Slot Interrupt Status
When set, this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Average Bits Per Slot Interrupt Status not detected : 0x0
1h = Average Bits Per Slot Interrupt Status detected : 0x1
0TXUNFISR/W0hTransmit Queue Underflow Interrupt Status
This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Queue Underflow Interrupt Status not detected : 0x0
1h = Transmit Queue Underflow Interrupt Status detected : 0x1

43.7.3.215 MTL_RxQ0_Operation_Mode Register (Offset = D30h) [Reset = 0h]

MTL_RxQ0_Operation_Mode is shown in Figure 43-254 and described in Table 43-308.

Return to the Summary Table.

The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command.
The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release

Figure 43-254 MTL_RxQ0_Operation_Mode Register
3130292827262524
RESERVED
R-0h
2322212019181716
RQSRESERVEDRFD
R/W-0hR-0hR/W-0h
15141312111098
RFDRESERVEDRFA
R/W-0hR-0hR/W-0h
76543210
EHFCDIS_TCP_EFRSFFEPFUPRESERVEDRTC
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-308 MTL_RxQ0_Operation_Mode Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23-20RQSR/W0hReceive Queue Size
This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one, the reset value is 0x0 and indicates size of 256 bytes.
When the number of Rx Queues is one, the field is read-only and the configured RX FIFO size in blocks of 256 bytes is reflected in the reset value.
The width of this field depends on the Rx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits:
LOG2(2048/256) = LOG2(8) = 3 bits
19-17RESERVEDR0hReserved.
16-14RFDR/W0hThreshold for Deactivating Flow Control (in half-duplex and full-duplex modes)
These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation:
- 0: Full minus 1 KB, that is, FULL 1 KB
- 1: Full minus 1.5 KB, that is, FULL 1.5 KB
- 2: Full minus 2 KB, that is, FULL 2 KB
- 3: Full minus 2.5 KB, that is, FULL 2.5 KB
- ...
- 6: Full minus 4 KB, that is, FULL 4 KB
- 7: Full minus 4.5 KB, that is, FULL 4.5 KB



The de-assertion is effective only after flow control is asserted.
Note: The value must be programmed in such a way to make sure that the threshold is a positive number.
When the EHFC is set high, these values are applicable only when the Rx queue size determined by the RQS field of this register, is equal to or greater than 4 KB.
For a given queue size, the values ranges between 0 and the encoding for FULL minus (QSIZE - 0.5 KB) and all other values are illegal. Here the term FULL and QSIZE refers to the queue size determined by the RQS field of this register.
The width of this field depends on RX FIFO size selected during the configuration. Remaining bits are reserved and read only.
13-11RESERVEDR0hReserved.
10-8RFAR/W0hThreshold for Activating Flow Control (in half-duplex and full-duplex
These bits control the threshold (fill-level of Rx queue) at which the flow control is activated:
For more information on encoding for this field, see RFD.
7EHFCR/W0hEnable Hardware Flow Control
When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. When reset, the flow control operation is disabled.
0h = Hardware Flow Control is disabled : 0x0
1h = Hardware Flow Control is enabled : 0x1
6DIS_TCP_EFR/W0hDisable Dropping of TCP/IP Checksum Error Packets
When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC.
When this bit is reset, all error packets are dropped if the FEP bit is reset.
0h = Dropping of TCP/IP Checksum Error Packets is enabled : 0x0
1h = Dropping of TCP/IP Checksum Error Packets is disabled : 0x1
5RSFR/W0hReceive Queue Store and Forward
When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register.
0h = Receive Queue Store and Forward is disabled : 0x0
1h = Receive Queue Store and Forward is enabled : 0x1
4FEPR/W0hForward Error Packets
When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped.
When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA.
0h = Forward Error Packets is disabled : 0x0
1h = Forward Error Packets is enabled : 0x1
3FUPR/W0hForward Undersized Good Packets
When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01.
0h = Forward Undersized Good Packets is disabled : 0x0
1h = Forward Undersized Good Packets is enabled : 0x1
2RESERVEDR0hReserved.
1-0RTCR/W0hReceive Queue Threshold Control
These bits control the threshold level of the MTL Rx queue (in bytes):
The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred.
This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1.
0h = 64 : 0x0
1h = 32 : 0x1
2h = 96 : 0x2
3h = 128 : 0x3

43.7.3.216 MTL_RxQ0_Missed_Packet_Overflow_Cnt Register (Offset = D34h) [Reset = 0h]

MTL_RxQ0_Missed_Packet_Overflow_Cnt is shown in Figure 43-255 and described in Table 43-309.

Return to the Summary Table.

The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow.

Figure 43-255 MTL_RxQ0_Missed_Packet_Overflow_Cnt Register
3130292827262524
RESERVEDMISCNTOVFMISPKTCNT
R-0hR-0hR-0h
2322212019181716
MISPKTCNT
R-0h
15141312111098
RESERVEDOVFCNTOVFOVFPKTCNT
R-0hR-0hR-0h
76543210
OVFPKTCNT
R-0h
Table 43-309 MTL_RxQ0_Missed_Packet_Overflow_Cnt Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27MISCNTOVFR0hMissed Packet Counter Overflow Bit
When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Missed Packet Counter overflow not detected : 0x0
1h = Missed Packet Counter overflow detected : 0x1
26-16MISPKTCNTR0hMissed Packet Counter
This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1.
This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
15-12RESERVEDR0hReserved.
11OVFCNTOVFR0hOverflow Counter Overflow Bit
When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Overflow Counter overflow not detected : 0x0
1h = Overflow Counter overflow detected : 0x1
10-0OVFPKTCNTR0hOverflow Packet Counter
This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This counter is reset when this register is read with mci_be_i[0] at 1'b1.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

43.7.3.217 MTL_RxQ0_Debug Register (Offset = D38h) [Reset = 0h]

MTL_RxQ0_Debug is shown in Figure 43-256 and described in Table 43-310.

Return to the Summary Table.

The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue.

Figure 43-256 MTL_RxQ0_Debug Register
3130292827262524
RESERVEDPRXQ
R-0hR-0h
2322212019181716
PRXQ
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRXQSTSRESERVEDRRCSTSRWCSTS
R-0hR-0hR-0hR-0hR-0h
Table 43-310 MTL_RxQ0_Debug Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved.
29-16PRXQR0hNumber of Packets in Receive Queue
This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size.
15-6RESERVEDR0hReserved.
5-4RXQSTSR0hMTL Rx Queue Fill-Level Status
This field gives the status of the fill-level of the Rx Queue:
0h = Rx Queue empty : 0x0
1h = Rx Queue fill-level below flow-control deactivate threshold : 0x1
2h = Rx Queue fill-level above flow-control activate threshold : 0x2
3h = Rx Queue full : 0x3
3RESERVEDR0hReserved.
2-1RRCSTSR0hMTL Rx Queue Read Controller State
This field gives the state of the Rx queue Read controller:
0h = Idle state : 0x0
1h = Reading packet data : 0x1
2h = Reading packet status (or timestamp) : 0x2
3h = Flushing the packet data and status : 0x3
0RWCSTSR0hMTL Rx Queue Write Controller Active Status
When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
0h = MTL Rx Queue Write Controller Active Status not detected : 0x0
1h = MTL Rx Queue Write Controller Active Status detected : 0x1

43.7.3.218 MTL_RxQ0_Control Register (Offset = D3Ch) [Reset = 0h]

MTL_RxQ0_Control is shown in Figure 43-257 and described in Table 43-311.

Return to the Summary Table.

The Queue Receive Control register controls the receive arbitration and passing of received packets to the application.

Figure 43-257 MTL_RxQ0_Control Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRXQ_FRM_ARBITRXQ_WEGT
R-0hR/W-0hR/W-0h
Table 43-311 MTL_RxQ0_Control Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved.
3RXQ_FRM_ARBITR/W0hReceive Queue Packet Arbitration
When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue.
When this bit is reset, the DWC_ether_qos drives the packet data to the ARI interface such that the following amount of data of currently-selected queue is transmitted before switching to other queue:
- PBL amount of data (indicated by ari_qN_pbl_i[])
or
- Complete data of a packet
The status and the timestamp are not a part of the PBL data. Therefore, the DWC_ether_qos drives the complete status (including timestamp status) during first PBL request for the packet (in store-and-forward mode) or the last PBL request for the packet (in Threshold mode).

0h = Receive Queue Packet Arbitration is disabled : 0x0
1h = Receive Queue Packet Arbitration is enabled : 0x1
2-0RXQ_WEGTR/W0hReceive Queue Weight
This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle.

43.7.3.219 MTL_TxQ1_Operation_Mode Register (Offset = D40h) [Reset = 0h]

MTL_TxQ1_Operation_Mode is shown in Figure 43-258 and described in Table 43-312.

Return to the Summary Table.

The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands.

Figure 43-258 MTL_TxQ1_Operation_Mode Register
31302928272625242322212019181716
RESERVEDTQS
R-0hR/W-0h
1514131211109876543210
RESERVEDTTCTXQENTSFFTQ
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 43-312 MTL_TxQ1_Operation_Mode Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved.
19-16TQSR/W0hTransmit Queue Size
This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one, the reset value is 0x0 and indicates size of 256 bytes.
When the number of Tx Queues is one, the field is read-only and the configured TX FIFO size in blocks of 256 bytes is reflected in the reset value.
The width of this field depends on the Tx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits:
LOG2(2048/256) = LOG2(8) = 3 bits
15-7RESERVEDR0hReserved.
6-4TTCR/W0hTransmit Threshold Control
These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset.
0h = 32 : 0x0
1h = 64 : 0x1
2h = 96 : 0x2
3h = 128 : 0x3
4h = 192 : 0x4
5h = 256 : 0x5
6h = 384 : 0x6
7h = 512 : 0x7
3-2TXQENR/W0hTransmit Queue Enable
This field is used to enable/disable the transmit queue 0.
- 2'b00: Not enabled
- 2'b01: Reserved
- 2'b10: Enabled
- 2'b11: Reserved
Note: In multiple Tx queues configuration, all the queues are disabled by default. Enable the Tx queue by programming this field.
0h = Not enabled : 0x0
1h = Enable in AV mode(Reserved in non-AV) : 0x1
2h = Enabled : 0x2
3h = Reserved : 0x3
1TSFR/W0hTransmit Store and Forward
When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when the transmission is stopped.
0h = Transmit Store and Forward is disabled : 0x0
1h = Transmit Store and Forward is enabled : 0x1
0FTQR/W0hFlush Transmit Queue
When this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you should not write to the MTL_TxQ1_Operation_Mode register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission.
Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (clk_tx_i) should be active.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Flush Transmit Queue is disabled : 0x0
1h = Flush Transmit Queue is enabled : 0x1

43.7.3.220 MTL_TxQ1_Underflow Register (Offset = D44h) [Reset = 0h]

MTL_TxQ1_Underflow is shown in Figure 43-259 and described in Table 43-313.

Return to the Summary Table.

The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush

Figure 43-259 MTL_TxQ1_Underflow Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDUFCNTOVFUFFRMCNT
R-0hR-0hR-0h
76543210
UFFRMCNT
R-0h
Table 43-313 MTL_TxQ1_Underflow Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved.
11UFCNTOVFR0hOverflow Bit for Underflow Packet Counter
This bit is set every time the Tx queue Underflow Packet Counter field overflows, that is, it has crossed the maximum count. In such a scenario, the overflow packet counter is reset to all-zeros and this bit indicates that the rollover happened.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Overflow not detected for Underflow Packet Counter : 0x0
1h = Overflow detected for Underflow Packet Counter : 0x1
10-0UFFRMCNTR0hUnderflow Packet Counter
This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when this register is read with mci_be_i[0] at 1'b1.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

43.7.3.221 MTL_TxQ1_Debug Register (Offset = D48h) [Reset = 0h]

MTL_TxQ1_Debug is shown in Figure 43-260 and described in Table 43-314.

Return to the Summary Table.

The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue.

Figure 43-260 MTL_TxQ1_Debug Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSTXSTSFRESERVEDPTXQ
R-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTXSTSFSTSTXQSTSTWCSTSTRCSTSTXQPAUSED
R-0hR-0hR-0hR-0hR-0hR-0h
Table 43-314 MTL_TxQ1_Debug Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved.
22-20STXSTSFR0hNumber of Status Words in Tx Status FIFO of Queue
This field indicates the current number of status in the Tx Status FIFO of this queue.
When the DTXSTS bit of MTL_Operation_Mode register is set to 1, this field does not reflect the number of status words in Tx Status FIFO.
19RESERVEDR0hReserved.
18-16PTXQR0hNumber of Packets in the Transmit Queue
This field indicates the current number of packets in the Tx Queue.
When the DTXSTS bit of MTL_Operation_Mode register is set to 1, this field does not reflect the number of packets in the Transmit queue.
15-6RESERVEDR0hReserved.
5TXSTSFSTSR0hMTL Tx Status FIFO Full Status
When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission.
0h = MTL Tx Status FIFO Full status is not detected : 0x0
1h = MTL Tx Status FIFO Full status is detected : 0x1
4TXQSTSR0hMTL Tx Queue Not Empty Status
When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission.
0h = MTL Tx Queue Not Empty status is not detected : 0x0
1h = MTL Tx Queue Not Empty status is detected : 0x1
3TWCSTSR0hMTL Tx Queue Write Controller Status
When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue.
0h = MTL Tx Queue Write Controller status is not detected : 0x0
1h = MTL Tx Queue Write Controller status is detected : 0x1
2-1TRCSTSR0hMTL Tx Queue Read Controller Status
This field indicates the state of the Tx Queue Read Controller:
0h = Idle state : 0x0
1h = Read state (transferring data to the MAC transmitter) : 0x1
2h = Waiting for pending Tx Status from the MAC transmitter : 0x2
3h = Flushing the Tx queue because of the Packet Abort request from the MAC : 0x3
0TXQPAUSEDR0hTransmit Queue in Pause
When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following:
- Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled
- Reception of 802.3x Pause packet when PFC is disabled
0h = Transmit Queue in Pause status is not detected : 0x0
1h = Transmit Queue in Pause status is detected : 0x1

43.7.3.222 MTL_TxQ1_ETS_Status Register (Offset = D54h) [Reset = 0h]

MTL_TxQ1_ETS_Status is shown in Figure 43-261 and described in Table 43-315.

Return to the Summary Table.

The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1.

Figure 43-261 MTL_TxQ1_ETS_Status Register
313029282726252423222120191817161514131211109876543210
RESERVEDABS
R-0hR-0h
Table 43-315 MTL_TxQ1_ETS_Status Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23-0ABSR0hAverage Bits per Slot
This field contains the average transmitted bits per slot.
If AV operation is enabled, this field is computed over number of slots, programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. When Enable Slot Interval feature is selected, the maximum value of this field is 0x6_4000 in 100 Mbps, 0x3E_8000 in 1000 Mbps and 9C_4000 in 2500 Mbps mode respectively. Otherwise, the maximum value of this field is 0x30D4 in 100 Mbs, 0x1E848 in 1000 Mbps and 0x4C4B4 in 2500 Mbps respectively.
When the DCB operation is enabled for Queue, this field is computed over every 10 million bit times slot (4 ms in 2500 Mbps
10 ms in 1000 Mbps
100 ms in 100 Mbps). The maximum value is 0x989680.

43.7.3.223 MTL_TxQ1_Quantum_Weight Register (Offset = D58h) [Reset = 0h]

MTL_TxQ1_Quantum_Weight is shown in Figure 43-262 and described in Table 43-316.

Return to the Summary Table.

The Queue 1 idleSlopeCredit, Quantum or Weights register provides the average traffic transmitted in Queue 1.

Figure 43-262 MTL_TxQ1_Quantum_Weight Register
313029282726252423222120191817161514131211109876543210
RESERVEDISCQW
R-0hR/W-0h
Table 43-316 MTL_TxQ1_Quantum_Weight Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved.
20-0ISCQWR/W0hidleSlopeCredit, Quantum or Weights
- idleSlopeCredit
When AV feature is enabled, this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns for 100 Mbps
8 ns for 1000 Mbps
3.2 ns for 2500 Mbps) when the credit is increasing. The software should program this field with computed credit in bits per cycle scaled by 1,024. The maximum value is portTransmitRate, that is, 0x2000 in 1000/2500 Mbps mode and 0x1000 in 100 Mbps mode. Bits[20:14] must be written to zero.
- Quantum
When the DCB operation is enabled with DWRR algorithm for Queue 1 traffic, this field contains the quantum value in bytes to be added to credit during every queue scanning cycle. The maximum value is 0x1312D0 bytes.
- Weights
When DCB operation is enabled with WFQ algorithm for Queue 1 traffic, this field contains the weight for this queue. The maximum value is 0x3FFF where weight of 0 indicates 100% bandwidth. Bits[20:14] must be written to zero.
When DCB operation or generic queuing operation is enabled with WRR algorithm for Queue 1 traffic, this field contains the weight for this queue. The maximum value is 0x64.
Bits [20:7] must be written to zero.
- Note 1: In multiple Queue configuration this field in respective per queue register must be programmed to some non-zero value when multiple queues are enabled or single queue other than Q0 is enabled. This field need not be programmed when only Q0 is enabled. In general, when WRR algorithm is selected a non-zero value must be programmed on both Receive and Transmit. In Receive, the register is MTL_Operation_Mode register.
- Note 2: For WFQ algorithm, higher the programmed weights lesser the bandwidth allocated for that Transmit Queue. The finish time is not a function of particular packet alone but it is as per the formula: (previous_finish_time of particular Transmit Queue + (weights*packet_size))
- Note 3: The weights programmed do not correspond to the number of packets but the fraction of bandwidth or time allocated for particular queue w.r.t. total BW or time.

43.7.3.224 MTL_Q1_Interrupt_Control_Status Register (Offset = D6Ch) [Reset = 0h]

MTL_Q1_Interrupt_Control_Status is shown in Figure 43-263 and described in Table 43-317.

Return to the Summary Table.

This register contains the interrupt enable and status bits for the queue 1 interrupts.

Figure 43-263 MTL_Q1_Interrupt_Control_Status Register
3130292827262524
RESERVEDRXOIE
R-0hR/W-0h
2322212019181716
RESERVEDRXOVFIS
R-0hR/W-0h
15141312111098
RESERVEDABPSIETXUIE
R-0hR/W-0hR/W-0h
76543210
RESERVEDABPSISTXUNFIS
R-0hR/W-0hR/W-0h
Table 43-317 MTL_Q1_Interrupt_Control_Status Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved.
24RXOIER/W0hReceive Queue Overflow Interrupt Enable
When this bit is set, the Receive Queue Overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled.
0h = Receive Queue Overflow Interrupt is disabled : 0x0
1h = Receive Queue Overflow Interrupt is enabled : 0x1
23-17RESERVEDR0hReserved.
16RXOVFISR/W0hReceive Queue Overflow Interrupt Status
This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Queue Overflow Interrupt Status not detected : 0x0
1h = Receive Queue Overflow Interrupt Status detected : 0x1
15-10RESERVEDR0hReserved.
9ABPSIER/W0hAverage Bits Per Slot Interrupt Enable
When this bit is set, the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
When this bit is cleared, the interrupt is not asserted for such an event.
0h = Average Bits Per Slot Interrupt is disabled : 0x0
1h = Average Bits Per Slot Interrupt is enabled : 0x1
8TXUIER/W0hTransmit Queue Underflow Interrupt Enable
When this bit is set, the Transmit Queue Underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled.
0h = Transmit Queue Underflow Interrupt Status is disabled : 0x0
1h = Transmit Queue Underflow Interrupt Status is enabled : 0x1
7-2RESERVEDR0hReserved.
1ABPSISR/W0hAverage Bits Per Slot Interrupt Status
When set, this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Average Bits Per Slot Interrupt Status not detected : 0x0
1h = Average Bits Per Slot Interrupt Status detected : 0x1
0TXUNFISR/W0hTransmit Queue Underflow Interrupt Status
This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Queue Underflow Interrupt Status not detected : 0x0
1h = Transmit Queue Underflow Interrupt Status detected : 0x1

43.7.3.225 MTL_RxQ1_Operation_Mode Register (Offset = D70h) [Reset = 0h]

MTL_RxQ1_Operation_Mode is shown in Figure 43-264 and described in Table 43-318.

Return to the Summary Table.

The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command.
The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release

Figure 43-264 MTL_RxQ1_Operation_Mode Register
3130292827262524
RESERVED
R-0h
2322212019181716
RQSRESERVEDRFD
R/W-0hR-0hR/W-0h
15141312111098
RFDRESERVEDRFA
R/W-0hR-0hR/W-0h
76543210
EHFCDIS_TCP_EFRSFFEPFUPRESERVEDRTC
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 43-318 MTL_RxQ1_Operation_Mode Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved.
23-20RQSR/W0hReceive Queue Size
This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one, the reset value is 0x0 and indicates size of 256 bytes.
When the number of Rx Queues is one, the field is read-only and the configured RX FIFO size in blocks of 256 bytes is reflected in the reset value.
The width of this field depends on the Rx memory size selected in your configuration. For example, if the memory size is 2048, the width of this field is 3 bits:
LOG2(2048/256) = LOG2(8) = 3 bits
19-17RESERVEDR0hReserved.
16-14RFDR/W0hThreshold for Deactivating Flow Control (in half-duplex and full-duplex modes)
These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation:
- 0: Full minus 1 KB, that is, FULL 1 KB
- 1: Full minus 1.5 KB, that is, FULL 1.5 KB
- 2: Full minus 2 KB, that is, FULL 2 KB
- 3: Full minus 2.5 KB, that is, FULL 2.5 KB
- ...
- 6: Full minus 4 KB, that is, FULL 4 KB
- 7: Full minus 4.5 KB, that is, FULL 4.5 KB



The de-assertion is effective only after flow control is asserted.
Note: The value must be programmed in such a way to make sure that the threshold is a positive number.
When the EHFC is set high, these values are applicable only when the Rx queue size determined by the RQS field of this register, is equal to or greater than 4 KB.
For a given queue size, the values ranges between 0 and the encoding for FULL minus (QSIZE - 0.5 KB) and all other values are illegal. Here the term FULL and QSIZE refers to the queue size determined by the RQS field of this register.
The width of this field depends on RX FIFO size selected during the configuration. Remaining bits are reserved and read only.
13-11RESERVEDR0hReserved.
10-8RFAR/W0hThreshold for Activating Flow Control (in half-duplex and full-duplex
These bits control the threshold (fill-level of Rx queue) at which the flow control is activated:
For more information on encoding for this field, see RFD.
7EHFCR/W0hEnable Hardware Flow Control
When this bit is set, the flow control signal operation, based on the fill-level of Rx queue, is enabled. When reset, the flow control operation is disabled.
0h = Hardware Flow Control is disabled : 0x0
1h = Hardware Flow Control is enabled : 0x1
6DIS_TCP_EFR/W0hDisable Dropping of TCP/IP Checksum Error Packets
When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC.
When this bit is reset, all error packets are dropped if the FEP bit is reset.
0h = Dropping of TCP/IP Checksum Error Packets is enabled : 0x0
1h = Dropping of TCP/IP Checksum Error Packets is disabled : 0x1
5RSFR/W0hReceive Queue Store and Forward
When this bit is set, the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register.
0h = Receive Queue Store and Forward is disabled : 0x0
1h = Receive Queue Store and Forward is enabled : 0x1
4FEPR/W0hForward Error Packets
When this bit is reset, the Rx queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped.
When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA.
0h = Forward Error Packets is disabled : 0x0
1h = Forward Error Packets is enabled : 0x1
3FUPR/W0hForward Undersized Good Packets
When this bit is set, the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01.
0h = Forward Undersized Good Packets is disabled : 0x0
1h = Forward Undersized Good Packets is enabled : 0x1
2RESERVEDR0hReserved.
1-0RTCR/W0hReceive Queue Threshold Control
These bits control the threshold level of the MTL Rx queue (in bytes):
The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred.
This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1.
0h = 64 : 0x0
1h = 32 : 0x1
2h = 96 : 0x2
3h = 128 : 0x3

43.7.3.226 MTL_RxQ1_Missed_Packet_Overflow_Cnt Register (Offset = D74h) [Reset = 0h]

MTL_RxQ1_Missed_Packet_Overflow_Cnt is shown in Figure 43-265 and described in Table 43-319.

Return to the Summary Table.

The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow.

Figure 43-265 MTL_RxQ1_Missed_Packet_Overflow_Cnt Register
3130292827262524
RESERVEDMISCNTOVFMISPKTCNT
R-0hR-0hR-0h
2322212019181716
MISPKTCNT
R-0h
15141312111098
RESERVEDOVFCNTOVFOVFPKTCNT
R-0hR-0hR-0h
76543210
OVFPKTCNT
R-0h
Table 43-319 MTL_RxQ1_Missed_Packet_Overflow_Cnt Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27MISCNTOVFR0hMissed Packet Counter Overflow Bit
When set, this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Missed Packet Counter overflow not detected : 0x0
1h = Missed Packet Counter overflow detected : 0x1
26-16MISPKTCNTR0hMissed Packet Counter
This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1.
This counter is incremented by 1 when the DMA discards the packet because of buffer unavailability.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
15-12RESERVEDR0hReserved.
11OVFCNTOVFR0hOverflow Counter Overflow Bit
When set, this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
0h = Overflow Counter overflow not detected : 0x0
1h = Overflow Counter overflow detected : 0x1
10-0OVFPKTCNTR0hOverflow Packet Counter
This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This counter is reset when this register is read with mci_be_i[0] at 1'b1.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

43.7.3.227 MTL_RxQ1_Debug Register (Offset = D78h) [Reset = 0h]

MTL_RxQ1_Debug is shown in Figure 43-266 and described in Table 43-320.

Return to the Summary Table.

The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue.

Figure 43-266 MTL_RxQ1_Debug Register
3130292827262524
RESERVEDPRXQ
R-0hR-0h
2322212019181716
PRXQ
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRXQSTSRESERVEDRRCSTSRWCSTS
R-0hR-0hR-0hR-0hR-0h
Table 43-320 MTL_RxQ1_Debug Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved.
29-16PRXQR0hNumber of Packets in Receive Queue
This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size.
15-6RESERVEDR0hReserved.
5-4RXQSTSR0hMTL Rx Queue Fill-Level Status
This field gives the status of the fill-level of the Rx Queue:
0h = Rx Queue empty : 0x0
1h = Rx Queue fill-level below flow-control deactivate threshold : 0x1
2h = Rx Queue fill-level above flow-control activate threshold : 0x2
3h = Rx Queue full : 0x3
3RESERVEDR0hReserved.
2-1RRCSTSR0hMTL Rx Queue Read Controller State
This field gives the state of the Rx queue Read controller:
0h = Idle state : 0x0
1h = Reading packet data : 0x1
2h = Reading packet status (or timestamp) : 0x2
3h = Flushing the packet data and status : 0x3
0RWCSTSR0hMTL Rx Queue Write Controller Active Status
When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
0h = MTL Rx Queue Write Controller Active Status not detected : 0x0
1h = MTL Rx Queue Write Controller Active Status detected : 0x1

43.7.3.228 MTL_RxQ1_Control Register (Offset = D7Ch) [Reset = 0h]

MTL_RxQ1_Control is shown in Figure 43-267 and described in Table 43-321.

Return to the Summary Table.

The Queue Receive Control register controls the receive arbitration and passing of received packets to the application.

Figure 43-267 MTL_RxQ1_Control Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRXQ_FRM_ARBITRXQ_WEGT
R-0hR/W-0hR/W-0h
Table 43-321 MTL_RxQ1_Control Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved.
3RXQ_FRM_ARBITR/W0hReceive Queue Packet Arbitration
When this bit is set, the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue.
When this bit is reset, the DWC_ether_qos drives the packet data to the ARI interface such that the following amount of data of currently-selected queue is transmitted before switching to other queue:
- PBL amount of data (indicated by ari_qN_pbl_i[])
or
- Complete data of a packet
The status and the timestamp are not a part of the PBL data. Therefore, the DWC_ether_qos drives the complete status (including timestamp status) during first PBL request for the packet (in store-and-forward mode) or the last PBL request for the packet (in Threshold mode).

0h = Receive Queue Packet Arbitration is disabled : 0x0
1h = Receive Queue Packet Arbitration is enabled : 0x1
2-0RXQ_WEGTR/W0hReceive Queue Weight
This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle.

43.7.3.229 DMA_Mode Register (Offset = 1000h) [Reset = 0h]

DMA_Mode is shown in Figure 43-268 and described in Table 43-322.

Return to the Summary Table.

The Bus Mode register establishes the bus operating modes for the DMA.

Figure 43-268 DMA_Mode Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDINTM
R-0hR/W-0h
15141312111098
RESERVEDPRTXPRRESERVEDRESERVED
R-0hR/W-0hR/W-0hR-0hR-0h
76543210
RESERVEDTAADASWR
R-0hR/W-0hR/W-0hR/W-0h
Table 43-322 DMA_Mode Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved.
17-16INTMR/W0hInterrupt Mode
This field defines the interrupt mode of DWC_ether_qos.
The behavior of the following outputs changes depending on the following settings:
- sbd_perch_tx_intr_o[] (Transmit Per Channel Interrupt)
- sbd_perch_rx_intr_o[] (Receive Per Channel Interrupt)
- sbd_intr_o (Common Interrupt)
It also changes the behavior of the RI/TI bits in the DMA_CH0_Status.
- 00: sbd_perch_* are pulse signals for each completion events. sbd_intr_o is also asserted and cleared only when software clears the corresponding RI/TI status bits
- 01: sbd_perch_* are level signals asserted on corresponding event and de-asserted when the software clears the corresponding RI/TI status bits. The sbd_intr_o is not asserted for these packet transfer completion events.
- 10: sbd_perch_* are level signals asserted on corresponding event and de-asserted when the software clears the corresponding RI/TI status bits. However, the signal is asserted again if the same event occurred again before it was cleared. The sbd_intr_o is not asserted for these packet transfer completion events.
- 11: Reserved
For more details please refer Table "DWC_ether_qos Transfer Complete Interrupt Behavior".
0h = See above description : 0x0
1h = See above description : 0x1
2h = See above description : 0x2
3h = Reserved : 0x3
15RESERVEDR0hReserved.
14-12PRR/W0hPriority Ratio
These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set.
0h = The priority ratio is 1:1 : 0x0
1h = The priority ratio is 2:1 : 0x1
2h = The priority ratio is 3:1 : 0x2
3h = The priority ratio is 4:1 : 0x3
4h = The priority ratio is 5:1 : 0x4
5h = The priority ratio is 6:1 : 0x5
6h = The priority ratio is 7:1 : 0x6
7h = The priority ratio is 8:1 : 0x7
11TXPRR/W0hTransmit Priority
When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus.
0h = Transmit Priority is disabled : 0x0
1h = Transmit Priority is enabled : 0x1
10-9RESERVEDR0hReserved.
8RESERVEDR0hReserved.
7-5RESERVEDR0hReserved.
4-2TAAR/W0hTransmit Arbitration Algorithm
This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected.
0h = Fixed priority(Channel 0 has the lowest priority and the last channel has the highest priority) : 0x0
1h = Weighted Strict Priority (WSP) : 0x1
2h = Weighted Round-Robin (WRR) : 0x2
3h = Reserved (for 3'b011 to 3'b111) : 0x3
1DAR/W0hDMA Tx or Rx Arbitration Scheme
This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels:
- 0: Weighted Round-Robin with Rx:Tx or Tx:Rx
The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit.
- 1: Fixed Priority
The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path.
0h = Weighted Round-Robin with Rx:Tx or Tx:Rx : 0x0
1h = Fixed Priority : 0x1
0SWRR/W0hSoftware Reset
When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all DWC_ether_qos clock domains. Before reprogramming any DWC_ether_qos register, a value of zero should be read in this bit.
This bit must be read at least 4 CSR clock cycles after it is written to 1.
Note: The reset operation is complete only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock.
Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.
0h = Software Reset is disabled : 0x0
1h = Software Reset is enabled : 0x1

43.7.3.230 DMA_SysBus_Mode Register (Offset = 1004h) [Reset = 0h]

DMA_SysBus_Mode is shown in Figure 43-269 and described in Table 43-323.

Return to the Summary Table.

The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests.

Figure 43-269 DMA_SysBus_Mode Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDRESERVED
R-0hR-0h
15141312111098
RBMBRESERVEDAALRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR-0hR/W-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDFB
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 43-323 DMA_SysBus_Mode Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved.
30RESERVEDR0hReserved.
29-26RESERVEDR0hReserved.
25-24RESERVEDR0hReserved.
23-18RESERVEDR0hReserved.
17-16RESERVEDR0hReserved.
15RBR/W0hRebuild INCRx Burst
When this bit is set high and the AHB master gets SPLIT, RETRY, or Early Burst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst.
0h = Rebuild INCRx Burst is disabled : 0x0
1h = Rebuild INCRx Burst is enabled : 0x1
14MBR/W0hMixed Burst
When this bit is set high and the FB bit is low, the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more. For burst length of 16 or less, the AHB master performs fixed burst transfers (INCRx and SINGLE).
0h = Mixed Burst is disabled : 0x0
1h = Mixed Burst is enabled : 0x1
13RESERVEDR0hReserved.
12AALR/W0hAddress-Aligned Beats
When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels.
0h = Address-Aligned Beats is disabled : 0x0
1h = Address-Aligned Beats is enabled : 0x1
11RESERVEDR0hReserved.
10RESERVEDR0hReserved.
9-8RESERVEDR0hReserved.
7RESERVEDR0hReserved.
6RESERVEDR0hReserved.
5RESERVEDR0hReserved.
4RESERVEDR0hReserved.
3RESERVEDR0hReserved.
2RESERVEDR0hReserved.
1RESERVEDR0hReserved.
0FBR/W0hFixed Burst Length




When this bit is set to 1, the AHB master initiates burst transfers of
specified length (INCRx or SINGLE).
When this bit is set to 0, the AHB master initiates transfers of unspecified
length (INCR) or SINGLE transfers.



0h = Fixed Burst Length is disabled : 0x0
1h = Fixed Burst Length is enabled : 0x1

43.7.3.231 DMA_Interrupt_Status Register (Offset = 1008h) [Reset = 0h]

DMA_Interrupt_Status is shown in Figure 43-270 and described in Table 43-324.

Return to the Summary Table.

The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels, MTL queues, and the MAC.

Figure 43-270 DMA_Interrupt_Status Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMACISMTLIS
R-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDC1ISDC0IS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 43-324 DMA_Interrupt_Status Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved.
17MACISR0hMAC Interrupt Status
This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source.
0h = MAC Interrupt Status not detected : 0x0
1h = MAC Interrupt Status detected : 0x1
16MTLISR0hMTL Interrupt Status
This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source.
0h = MTL Interrupt Status not detected : 0x0
1h = MTL Interrupt Status detected : 0x1
15-8RESERVEDR0hReserved.
7RESERVEDR0hReserved.
6RESERVEDR0hReserved.
5RESERVEDR0hReserved.
4RESERVEDR0hReserved.
3RESERVEDR0hReserved.
2RESERVEDR0hReserved.
1DC1ISR0hDMA Channel 1 Interrupt Status
This bit indicates an interrupt event in DMA Channel 1. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 1 to get the exact cause of the interrupt and clear its source.
0h = DMA Channel 1 Interrupt Status not detected : 0x0
1h = DMA Channel 1 Interrupt Status detected : 0x1
0DC0ISR0hDMA Channel 0 Interrupt Status
This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 1'b0, the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source.
0h = DMA Channel 0 Interrupt Status not detected : 0x0
1h = DMA Channel 0 Interrupt Status detected : 0x1

43.7.3.232 DMA_Debug_Status0 Register (Offset = 100Ch) [Reset = 0h]

DMA_Debug_Status0 is shown in Figure 43-271 and described in Table 43-325.

Return to the Summary Table.

The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose.

Figure 43-271 DMA_Debug_Status0 Register
3130292827262524
RESERVEDRESERVED
R-0hR-0h
2322212019181716
TPS1RPS1
R-0hR-0h
15141312111098
TPS0RPS0
R-0hR-0h
76543210
RESERVEDRESERVEDAXWHSTS
R-0hR-0hR-0h
Table 43-325 DMA_Debug_Status0 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved.
27-24RESERVEDR0hReserved.
23-20TPS1R0hDMA Channel 1 Transmit Process State
This field indicates the Tx DMA FSM state for Channel 1.
The MSB of this field always returns 0. This field does not generate an interrupt.
0h = Stopped (Reset or Stop Transmit Command issued) : 0x0
1h = Running (Fetching Tx Transfer Descriptor) : 0x1
2h = Running (Waiting for status) : 0x2
3h = Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) : 0x3
4h = Timestamp write state : 0x4
5h = Reserved for future use : 0x5
6h = Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) : 0x6
7h = Running (Closing Tx Descriptor) : 0x7
19-16RPS1R0hDMA Channel 1 Receive Process State
This field indicates the Rx DMA FSM state for Channel 1.
The MSB of this field always returns 0. This field does not generate an interrupt.
0h = Stopped (Reset or Stop Receive Command issued) : 0x0
1h = Running (Fetching Rx Transfer Descriptor) : 0x1
2h = Reserved for future use : 0x2
3h = Running (Waiting for Rx packet) : 0x3
4h = Suspended (Rx Descriptor Unavailable) : 0x4
5h = Running (Closing the Rx Descriptor) : 0x5
6h = Timestamp write state : 0x6
7h = Running (Transferring the received packet data from the Rx buffer to the system memory) : 0x7
15-12TPS0R0hDMA Channel 0 Transmit Process State
This field indicates the Tx DMA FSM state for Channel 0.
The MSB of this field always returns 0. This field does not generate an interrupt.
0h = Stopped (Reset or Stop Transmit Command issued) : 0x0
1h = Running (Fetching Tx Transfer Descriptor) : 0x1
2h = Running (Waiting for status) : 0x2
3h = Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) : 0x3
4h = Timestamp write state : 0x4
5h = Reserved for future use : 0x5
6h = Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) : 0x6
7h = Running (Closing Tx Descriptor) : 0x7
11-8RPS0R0hDMA Channel 0 Receive Process State
This field indicates the Rx DMA FSM state for Channel 0.
The MSB of this field always returns 0. This field does not generate an interrupt.
0h = Stopped (Reset or Stop Receive Command issued) : 0x0
1h = Running (Fetching Rx Transfer Descriptor) : 0x1
2h = Reserved for future use : 0x2
3h = Running (Waiting for Rx packet) : 0x3
4h = Suspended (Rx Descriptor Unavailable) : 0x4
5h = Running (Closing the Rx Descriptor) : 0x5
6h = Timestamp write state : 0x6
7h = Running (Transferring the received packet data from the Rx buffer to the system memory) : 0x7
7-2RESERVEDR0hReserved.
1RESERVEDR0hReserved.
0AXWHSTSR0hAHB Master Status



When high, this bit indicates that the AHB master FSMs are in the non-idle state.
0h = AXI Master Write Channel or AHB Master Status not detected : 0x0
1h = AXI Master Write Channel or AHB Master Status detected : 0x1

43.7.3.233 DMA_CH0_Control Register (Offset = 1100h) [Reset = 0h]

DMA_CH0_Control is shown in Figure 43-272 and described in Table 43-326.

Return to the Summary Table.

The DMA Channeli Control register specifies the MSS value for segmentation, length to skip between two descriptors, and also the features such as header splitting and 8xPBL mode.

Figure 43-272 DMA_CH0_Control Register
3130292827262524
RESERVEDSPH
R-0hR/W-0h
2322212019181716
RESERVEDDSLRESERVEDPBLx8
R-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDMSS
R-0hR/W-0h
76543210
MSS
R/W-0h
Table 43-326 DMA_CH0_Control Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved.
24SPHR/W0hSplit Headers
When this bit is set, the DMA splits the header and payload in the Receive path. The DMA writes the header to the Buffer Address1 of RDES0. The DMA writes the payload to the buffer to which the Buffer Address2 is pointing.
The software must ensure that the header fits into the Receive buffers. If the header length exceeds the receive buffer size, the DMA does not split the header and payload.
This bit is available only if Enable Split Header Structure option is selected.
0h = Split Headers feature is disabled : 0x0
1h = Split Headers feature is enabled : 0x1
23-21RESERVEDR0hReserved.
20-18DSLR/W0hDescriptor Skip Length
This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor.
When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous.
17RESERVEDR0hReserved.
16PBLx8R/W0h8xPBL mode
When this bit is set, the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.
0h = 8xPBL mode is disabled : 0x0
1h = 8xPBL mode is enabled : 0x1
15-14RESERVEDR0hReserved.
13-0MSSR/W0hMaximum Segment Size
This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of DMA_CH0_Tx_Control register is set.
The value programmed in this field must be more than the configured Datawidth in bytes. It is recommended to use a MSS value of 64 bytes or more.

43.7.3.234 DMA_CH0_Tx_Control Register (Offset = 1104h) [Reset = 0h]

DMA_CH0_Tx_Control is shown in Figure 43-273 and described in Table 43-327.

Return to the Summary Table.

The DMA Channeli Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights.

Figure 43-273 DMA_CH0_Tx_Control Register
3130292827262524
RESERVEDRESERVEDRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVEDETICTxPBL
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDTSERESERVED
R-0hR-0hR/W-0hR-0h
76543210
RESERVEDOSFTCWST
R-0hR/W-0hR/W-0hR/W-0h
Table 43-327 DMA_CH0_Tx_Control Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28RESERVEDR0hReserved.
27-24RESERVEDR0hReserved.
23RESERVEDR0hReserved.
22ETICR/W0hEarly Transmit Interrupt Control
When this bit is set, Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set.

When this bit is reset, ETI is set only after a complete packet is transferred to the MTL TX FIFO memory.
0h = Early Transmit Interrupt is disabled : 0x0
1h = Early Transmit Interrupt is enabled : 0x1
21-16TxPBLR/W0hTransmit Programmable Burst Length
These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior.
To transfer more than 32 beats, perform the following steps:
1. Set the 8xPBL mode in DMA_CH0_Control register.
2. Set the TxPBL.
Note: The maximum value of TxPBL must be less than or equal to half the Tx Queue size (TQS field of MTL_TxQ[n]_Operation_Mode register) in terms of beats. This is required so that the Tx Queue has space to store at least another Tx PBL worth of data while the MTL Tx Queue Controller is transferring data to MAC. For example, in 64-bit data width configurations the total locations in Tx Queue of size 512 bytes is 64, TxPBL and 8xPBL needs to be programmed to less than or equal to 32.
15RESERVEDR0hReserved.
14-13RESERVEDR0hReserved.
12TSER/W0hTCP Segmentation Enabled
When this bit is set, the DMA performs the TCP segmentation or UDP Segmentation/Fragmentation for packets in this channel. The TCP segmentation or UDP packet's segmentation/Fragmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor.When this bit is set, the TxPBL value must be greater than 4.
0h = TCP Segmentation is disabled : 0x0
1h = TCP Segmentation is enabled : 0x1
11-5RESERVEDR0hReserved.
4OSFR/W0hOperate on Second Packet
When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained.
0h = Operate on Second Packet disabled : 0x0
1h = Operate on Second Packet enabled : 0x1
3-1TCWR/W0hTransmit Channel Weight
This field indicates the weight assigned to the corresponding Transmit channel. When reset is complete, this field is set to 0 for all channels by default, resulting in equal weights to all channels.
0STR/W0hStart or Stop Transmission Command
When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted.
The DMA tries to acquire descriptor from either of the following positions:
- The current position in the list
This is the base address of the Transmit list set by the DMA_CH0_TxDesc_List_Address register.
- The position at which the transmission was previously stopped
If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the DMA_CH0_Status register is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the DMA_CH0_TxDesc_List_Address register, the DMA behavior is unpredictable.
When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program DMA_CH0_TxDesc_List_Address register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state.
0h = Stop Transmission Command : 0x0
1h = Start Transmission Command : 0x1

43.7.3.235 DMA_CH0_Rx_Control Register (Offset = 1108h) [Reset = 0h]

DMA_CH0_Rx_Control is shown in Figure 43-274 and described in Table 43-328.

Return to the Summary Table.

The DMA Channeli Receive Control register controls the Rx features such as PBL, buffer size, and extended status.

Figure 43-274 DMA_CH0_Rx_Control Register
3130292827262524
RPFRESERVEDRESERVED
R/W-0hR-0hR-0h
2322212019181716
RESERVEDERICRxPBL
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDRBSZ_13_y
R-0hR/W-0h
76543210
RBSZ_13_yRBSZ_x_0SR
R/W-0hR-0hR/W-0h
Table 43-328 DMA_CH0_Rx_Control Register Field Descriptions
BitFieldTypeResetDescription
31RPFR/W0hRx Packet Flush.
When this bit is set to 1, then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel, when it is stopped. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this RxDMA was stopped, get flushed out. The packets that are received by the MAC after the RxDMA is re-started are routed to the RxDMA. The flushing happens on the Read side of the Rx Queue.
When this bit is set to 0, the DWC_ether_qos not flush the packet in the Rx Queue destined to this RxDMA Channel when it is STOP state. This may in turn cause head-of-line blocking in the corresponding RxQueue.
0h = Rx Packet Flush is disabled : 0x0
1h = Rx Packet Flush is enabled : 0x1
30-28RESERVEDR0hReserved.
27-24RESERVEDR0hReserved.
23RESERVEDR0hReserved.
22ERICR/W0hEarly Receive Interrupt Control
When this bit is set, Early Receive Interrupt (ERI) status is set after completion of every burst transfer of data from the Rx DMA to the buffer.

When this bit is reset, ERI is set only after a complete buffer is filled up by the RxDMA.
0h = Early Receive Interrupt is disabled : 0x0
1h = Early Receive Interrupt is enabled : 0x1
21-16RxPBLR/W0hReceive Programmable Burst Length
These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior.
To transfer more than 32 beats, perform the following steps:
1. Set the 8xPBL mode in the DMA_CH0_Control register.
2. Set the RxPBL.
Note: The maximum value of RxPBL must be less than or equal to half the Rx Queue size (RQS field of MTL_RxQ[n]_Operation_Mode register) in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the Rx DMA is transferring a block of data. For example, in 64-bit data width configurations the total locations in Rx Queue of size 512 bytes is 64, so RxPBL and 8xPBL needs to be programmed to less than or equal to 32.
15RESERVEDR0hReserved.
14-3RBSZ_13_yR/W0hReceive Buffer size High
RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is applicable to payload buffers when split headers are enabled.
Note: The buffer size must be a multiple of 4, 8, or 16 depending on the data bus widths (32-bit, 64-bit, or 128-bit respectively). This is required even if the value of buffer address pointer is not aligned to data bus width. Hence the lower RBSZ_x_0 bits are read-only and the value is considered as all-zero. Thus the RBSZ_13_y indicates the buffer size in terms of locations (with the width same as bus-width).
2-1RBSZ_x_0R0hReceive Buffer size Low
RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration.
This field is of width 2, 3, or 4 bits for 32-bit, 64-bit, or 128-bit data bus width respectively. This field is read-only (RO).
0SRR/W0hStart or Stop Receive
When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets.
The DMA tries to acquire descriptor from either of the following positions:
- The current position in the list
This is the address set by the DMA_CH0_RxDesc_List_Address register.
- The position at which the Rx process was previously stopped
If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the DMA_CH0_Status register is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the DMA_CH0_RxDesc_List_Address register, the DMA behavior is unpredictable.
When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state.
0h = Stop Receive : 0x0
1h = Start Receive : 0x1

43.7.3.236 DMA_CH0_TxDesc_List_Address Register (Offset = 1114h) [Reset = 0h]

DMA_CH0_TxDesc_List_Address is shown in Figure 43-275 and described in Table 43-329.

Return to the Summary Table.

The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low.
You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in DMA_CH0_Tx_Control register. When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address. If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier.

Figure 43-275 DMA_CH0_TxDesc_List_Address Register
3130292827262524
TDESLA
R/W-0h
2322212019181716
TDESLA
R/W-0h
15141312111098
TDESLA
R/W-0h
76543210
TDESLARESERVED
R/W-0hR-0h
Table 43-329 DMA_CH0_TxDesc_List_Address Register Field Descriptions
BitFieldTypeResetDescription
31-2TDESLAR/W0hStart of Transmit List
This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO).
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.237 DMA_CH0_RxDesc_List_Address Register (Offset = 111Ch) [Reset = 0h]

DMA_CH0_RxDesc_List_Address is shown in Figure 43-276 and described in Table 43-330.

Return to the Summary Table.

The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list.
This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given. You can write to this register only when Rx DMA has stopped, that is, SR bit is set to zero in DMA_CH0_Rx_Control register. When stopped, this register can be written with a new descriptor list address.
When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.

Figure 43-276 DMA_CH0_RxDesc_List_Address Register
3130292827262524
RDESLA
R/W-0h
2322212019181716
RDESLA
R/W-0h
15141312111098
RDESLA
R/W-0h
76543210
RDESLARESERVED
R/W-0hR-0h
Table 43-330 DMA_CH0_RxDesc_List_Address Register Field Descriptions
BitFieldTypeResetDescription
31-2RDESLAR/W0hStart of Receive List
This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO).
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.238 DMA_CH0_TxDesc_Tail_Pointer Register (Offset = 1120h) [Reset = 0h]

DMA_CH0_TxDesc_Tail_Pointer is shown in Figure 43-277 and described in Table 43-331.

Return to the Summary Table.

The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor.

Figure 43-277 DMA_CH0_TxDesc_Tail_Pointer Register
3130292827262524
TDTP
R/W-0h
2322212019181716
TDTP
R/W-0h
15141312111098
TDTP
R/W-0h
76543210
TDTPRESERVED
R/W-0hR-0h
Table 43-331 DMA_CH0_TxDesc_Tail_Pointer Register Field Descriptions
BitFieldTypeResetDescription
31-2TDTPR/W0hTransmit Descriptor Tail Pointer
This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers.
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.239 DMA_CH0_RxDesc_Tail_Pointer Register (Offset = 1128h) [Reset = 0h]

DMA_CH0_RxDesc_Tail_Pointer is shown in Figure 43-278 and described in Table 43-332.

Return to the Summary Table.

The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor.

Figure 43-278 DMA_CH0_RxDesc_Tail_Pointer Register
3130292827262524
RDTP
R/W-0h
2322212019181716
RDTP
R/W-0h
15141312111098
RDTP
R/W-0h
76543210
RDTPRESERVED
R/W-0hR-0h
Table 43-332 DMA_CH0_RxDesc_Tail_Pointer Register Field Descriptions
BitFieldTypeResetDescription
31-2RDTPR/W0hReceive Descriptor Tail Pointer
This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors referenced between the head and the tail pointer registers.
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.240 DMA_CH0_TxDesc_Ring_Length Register (Offset = 112Ch) [Reset = 0h]

DMA_CH0_TxDesc_Ring_Length is shown in Figure 43-279 and described in Table 43-333.

Return to the Summary Table.

The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring.

Figure 43-279 DMA_CH0_TxDesc_Ring_Length Register
313029282726252423222120191817161514131211109876543210
RESERVEDTDRL
R-0hR/W-0h
Table 43-333 DMA_CH0_TxDesc_Ring_Length Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved.
9-0TDRLR/W0hTransmit Descriptor Ring Length
This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For example, You can program any value up to 0x3FF in this field. This field is 10 bits wide, if you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9.

43.7.3.241 DMA_CH0_RxDesc_Ring_Length Register (Offset = 1130h) [Reset = 0h]

DMA_CH0_RxDesc_Ring_Length is shown in Figure 43-280 and described in Table 43-334.

Return to the Summary Table.

The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring.

Figure 43-280 DMA_CH0_RxDesc_Ring_Length Register
313029282726252423222120191817161514131211109876543210
RESERVEDRDRL
R-0hR/W-0h
Table 43-334 DMA_CH0_RxDesc_Ring_Length Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved.
9-0RDRLR/W0hReceive Descriptor Ring Length
This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example, You can program any value up to 0x3FF in this field. This field is 10 bits wide, if you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9.

43.7.3.242 DMA_CH0_Interrupt_Enable Register (Offset = 1134h) [Reset = 0h]

DMA_CH0_Interrupt_Enable is shown in Figure 43-281 and described in Table 43-335.

Return to the Summary Table.

The Channeli Interrupt Enable register enables the interrupts reported by the Status register.

Figure 43-281 DMA_CH0_Interrupt_Enable Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NIEAIECDEEFBEEERIEETIERWTERSE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RBUERIERESERVEDTBUETXSETIE
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-335 DMA_CH0_Interrupt_Enable Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15NIER/W0hNormal Interrupt Summary Enable
When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register:
- Bit 0: Transmit Interrupt
- Bit 2: Transmit Buffer Unavailable
- Bit 6: Receive Interrupt
- Bit 11: Early Receive Interrupt
When this bit is reset, the normal interrupt summary is disabled.
0h = Normal Interrupt Summary is disabled : 0x0
1h = Normal Interrupt Summary is enabled : 0x1
14AIER/W0hAbnormal Interrupt Summary Enable
When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register:
- Bit 1: Transmit Process Stopped
- Bit 7: Rx Buffer Unavailable
- Bit 8: Receive Process Stopped
- Bit 9: Receive Watchdog Timeout
- Bit 10: Early Transmit Interrupt
- Bit 12: Fatal Bus Error
- Bit 13: Context Descriptor Error
When this bit is reset, the abnormal interrupt summary is disabled.
0h = Abnormal Interrupt Summary is disabled : 0x0
1h = Abnormal Interrupt Summary is enabled : 0x1
13CDEER/W0hContext Descriptor Error Enable
When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. When this bit is reset, the Descriptor error interrupt is disabled.
0h = Context Descriptor Error is disabled : 0x0
1h = Context Descriptor Error is enabled : 0x1
12FBEER/W0hFatal Bus Error Enable
When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled.
0h = Fatal Bus Error is disabled : 0x0
1h = Fatal Bus Error is enabled : 0x1
11ERIER/W0hEarly Receive Interrupt Enable
When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled.
0h = Early Receive Interrupt is disabled : 0x0
1h = Early Receive Interrupt is enabled : 0x1
10ETIER/W0hEarly Transmit Interrupt Enable
When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled.
0h = Early Transmit Interrupt is disabled : 0x0
1h = Early Transmit Interrupt is enabled : 0x1
9RWTER/W0hReceive Watchdog Timeout Enable
When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled.
0h = Receive Watchdog Timeout is disabled : 0x0
1h = Receive Watchdog Timeout is enabled : 0x1
8RSER/W0hReceive Stopped Enable
When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled.
0h = Receive Stopped is disabled : 0x0
1h = Receive Stopped is enabled : 0x1
7RBUER/W0hReceive Buffer Unavailable Enable
When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled.
0h = Receive Buffer Unavailable is disabled : 0x0
1h = Receive Buffer Unavailable is enabled : 0x1
6RIER/W0hReceive Interrupt Enable
When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
0h = Receive Interrupt is disabled : 0x0
1h = Receive Interrupt is enabled : 0x1
5-3RESERVEDR0hReserved.
2TBUER/W0hTransmit Buffer Unavailable Enable
When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled.
0h = Transmit Buffer Unavailable is disabled : 0x0
1h = Transmit Buffer Unavailable is enabled : 0x1
1TXSER/W0hTransmit Stopped Enable
When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled.
0h = Transmit Stopped is disabled : 0x0
1h = Transmit Stopped is enabled : 0x1
0TIER/W0hTransmit Interrupt Enable
When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled.
0h = Transmit Interrupt is disabled : 0x0
1h = Transmit Interrupt is enabled : 0x1

43.7.3.243 DMA_CH0_Rx_Interrupt_Watchdog_Timer Register (Offset = 1138h) [Reset = 0h]

DMA_CH0_Rx_Interrupt_Watchdog_Timer is shown in Figure 43-282 and described in Table 43-336.

Return to the Summary Table.

The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value, it enables the watchdog timer for the RI bit of the DMA_CHi_Status register.

Figure 43-282 DMA_CH0_Rx_Interrupt_Watchdog_Timer Register
31302928272625242322212019181716
RESERVEDRWTU
R-0hR/W-0h
1514131211109876543210
RESERVEDRWT
R-0hR/W-0h
Table 43-336 DMA_CH0_Rx_Interrupt_Watchdog_Timer Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved.
17-16RWTUR/W0hReceive Interrupt Watchdog Timer Count Units
This fields indicates the number of system clock cycles corresponding to one unit in RWT field.
- 2'b00: 256
- 2'b01: 512
- 2'b10: 1024
- 2'b11: 2048
For example, when RWT=2 and RWTU=1, the watchdog timer is set for 2*512=1024 system clock cycles.
15-8RESERVEDR0hReserved.
7-0RWTR/W0hReceive Interrupt Watchdog Timer Count
This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the DMA_CH0_Status register, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30].
When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet.

43.7.3.244 DMA_CH0_Current_App_TxDesc Register (Offset = 1144h) [Reset = 0h]

DMA_CH0_Current_App_TxDesc is shown in Figure 43-283 and described in Table 43-337.

Return to the Summary Table.

The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA.

Figure 43-283 DMA_CH0_Current_App_TxDesc Register
313029282726252423222120191817161514131211109876543210
CURTDESAPTR
R-0h
Table 43-337 DMA_CH0_Current_App_TxDesc Register Field Descriptions
BitFieldTypeResetDescription
31-0CURTDESAPTRR0hApplication Transmit Descriptor Address Pointer
The DMA updates this pointer during Tx operation. This pointer is cleared on reset.

43.7.3.245 DMA_CH0_Current_App_RxDesc Register (Offset = 114Ch) [Reset = 0h]

DMA_CH0_Current_App_RxDesc is shown in Figure 43-284 and described in Table 43-338.

Return to the Summary Table.

The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA.

Figure 43-284 DMA_CH0_Current_App_RxDesc Register
313029282726252423222120191817161514131211109876543210
CURRDESAPTR
R-0h
Table 43-338 DMA_CH0_Current_App_RxDesc Register Field Descriptions
BitFieldTypeResetDescription
31-0CURRDESAPTRR0hApplication Receive Descriptor Address Pointer
The DMA updates this pointer during Rx operation. This pointer is cleared on reset.

43.7.3.246 DMA_CH0_Current_App_TxBuffer Register (Offset = 1154h) [Reset = 0h]

DMA_CH0_Current_App_TxBuffer is shown in Figure 43-285 and described in Table 43-339.

Return to the Summary Table.

The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA.

Figure 43-285 DMA_CH0_Current_App_TxBuffer Register
313029282726252423222120191817161514131211109876543210
CURTBUFAPTR
R-0h
Table 43-339 DMA_CH0_Current_App_TxBuffer Register Field Descriptions
BitFieldTypeResetDescription
31-0CURTBUFAPTRR0hApplication Transmit Buffer Address Pointer
The DMA updates this pointer during Tx operation. This pointer is cleared on reset.

43.7.3.247 DMA_CH0_Current_App_RxBuffer Register (Offset = 115Ch) [Reset = 0h]

DMA_CH0_Current_App_RxBuffer is shown in Figure 43-286 and described in Table 43-340.

Return to the Summary Table.

The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA.

Figure 43-286 DMA_CH0_Current_App_RxBuffer Register
313029282726252423222120191817161514131211109876543210
CURRBUFAPTR
R-0h
Table 43-340 DMA_CH0_Current_App_RxBuffer Register Field Descriptions
BitFieldTypeResetDescription
31-0CURRBUFAPTRR0hApplication Receive Buffer Address Pointer
The DMA updates this pointer during Rx operation. This pointer is cleared on reset.

43.7.3.248 DMA_CH0_Status Register (Offset = 1160h) [Reset = 0h]

DMA_CH0_Status is shown in Figure 43-287 and described in Table 43-341.

Return to the Summary Table.

The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA.
Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx DMA Channels and Tx DMA Channels.

Figure 43-287 DMA_CH0_Status Register
31302928272625242322212019181716
RESERVEDREBTEB
R-0hR-0hR-0h
1514131211109876543210
NISAISCDEFBEERIETIRWTRPSRBURIRESERVEDTBUTPSTI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-341 DMA_CH0_Status Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved.
21-19REBR0hRx DMA Error Bits
This field indicates the type of error that caused a Bus Error. For example, error response on the AHB or AXI interface.
Bit 21
- 1'b1: Error during data transfer by Rx DMA
- 1'b0: No Error during data transfer by Rx DMA
Bit 20
- 1'b1: Error during descriptor access
- 1'b0: Error during data buffer access
Bit 19
- 1'b1: Error during read transfer
- 1'b0: Error during write transfer
This field is valid only when the FBE bit is set. This field does not generate an interrupt.
18-16TEBR0hTx DMA Error Bits
This field indicates the type of error that caused a Bus Error. For example, error response on the AHB or AXI interface.
Bit 18
- 1'b1: Error during data transfer by Tx DMA
- 1'b0: No Error during data transfer by Tx DMA
Bit 17
- 1'b1: Error during descriptor access
- 1'b0: Error during data buffer access
Bit 16
- 1'b1: Error during read transfer
- 1'b0: Error during write transfer
This field is valid only when the FBE bit is set. This field does not generate an interrupt.
15NISR/W0hNormal Interrupt Summary
Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register:
- Bit 0: Transmit Interrupt
- Bit 2: Transmit Buffer Unavailable
- Bit 6: Receive Interrupt
- Bit 11: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH0_Interrupt_Enable register) affect the Normal Interrupt Summary bit.
This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Normal Interrupt Summary status not detected : 0x0
1h = Normal Interrupt Summary status detected : 0x1
14AISR/W0hAbnormal Interrupt Summary
Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register:
- Bit 1: Transmit Process Stopped
- Bit 7: Receive Buffer Unavailable
- Bit 8: Receive Process Stopped
- Bit 10: Early Transmit Interrupt
- Bit 12: Fatal Bus Error
- Bit 13: Context Descriptor Error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Abnormal Interrupt Summary status not detected : 0x0
1h = Abnormal Interrupt Summary status detected : 0x1
13CDER/W0hContext Descriptor Error
This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Context Descriptor Error status not detected : 0x0
1h = Context Descriptor Error status detected : 0x1
12FBER/W0hFatal Bus Error
This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Fatal Bus Error status not detected : 0x0
1h = Fatal Bus Error status detected : 0x1
11ERIR/W0hEarly Receive Interrupt
This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory.

When ERIC=0, this bit is set only after the Rx DMA has filled up a complete receive buffer with packet data. When ERIC=1, this bit is set after every burst transfer of data from the Rx DMA to the buffer.

The setting of RI bit automatically clears this bit.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Early Receive Interrupt status not detected : 0x0
1h = Early Receive Interrupt status detected : 0x1
10ETIR/W0hEarly Transmit Interrupt
This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory.

When ETIC=0, this bit is set only after the Tx DMA has transferred a complete packet to MTL. When ETIC=1, this bit is set after completion of (partial) packet data transfer from buffers in the Transmit descriptor in which IOC=1.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Early Transmit Interrupt status not detected : 0x0
1h = Early Transmit Interrupt status detected : 0x1
9RWTR/W0hReceive Watchdog Timeout
This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
0h = Receive Watchdog Timeout status not detected : 0x0
1h = Receive Watchdog Timeout status detected : 0x1
8RPSR/W0hReceive Process Stopped
This bit is asserted when the Rx process enters the Stopped state.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Process Stopped status not detected : 0x0
1h = Receive Process Stopped status detected : 0x1
7RBUR/W0hReceive Buffer Unavailable
This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Buffer Unavailable status not detected : 0x0
1h = Receive Buffer Unavailable status detected : 0x1
6RIR/W0hReceive Interrupt
This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor.
The reception remains in the Running state.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Interrupt status not detected : 0x0
1h = Receive Interrupt status detected : 0x1
5-3RESERVEDR0hReserved.
2TBUR/W0hTransmit Buffer Unavailable
This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit Process state transitions.
To resume processing the Transmit descriptors, the application should do the following:
1. Change the ownership of the descriptor by setting Bit 31 of TDES3.
2. Issue a Transmit Poll Demand command.
For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Buffer Unavailable status not detected : 0x0
1h = Transmit Buffer Unavailable status detected : 0x1
1TPSR/W0hTransmit Process Stopped
This bit is set when the transmission is stopped.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Process Stopped status not detected : 0x0
1h = Transmit Process Stopped status detected : 0x1
0TIR/W0hTransmit Interrupt
This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Interrupt status not detected : 0x0
1h = Transmit Interrupt status detected : 0x1

43.7.3.249 DMA_CH0_Miss_Frame_Cnt Register (Offset = 1164h) [Reset = 0h]

DMA_CH0_Miss_Frame_Cnt is shown in Figure 43-288 and described in Table 43-342.

Return to the Summary Table.

This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH${i}_Rx_Control register.

Figure 43-288 DMA_CH0_Miss_Frame_Cnt Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
MFCORESERVEDMFC
R-0hR-0hR-0h
76543210
MFC
R-0h
Table 43-342 DMA_CH0_Miss_Frame_Cnt Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15MFCOR0hOverflow status of the MFC Counter
When this bit is set then the MFC counter does not get incremented
further. The bit gets cleared when this register is read.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
14-11RESERVEDR0hReserved.
10-0MFCR0hDropped Packet Counters
This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing
RPF field in DMA_CH${i}_Rx_Control register. The counter gets cleared when this register is read.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

43.7.3.250 DMA_CH0_RX_ERI_Cnt Register (Offset = 116Ch) [Reset = 0h]

DMA_CH0_RX_ERI_Cnt is shown in Figure 43-289 and described in Table 43-343.

Return to the Summary Table.

Figure 43-289 DMA_CH0_RX_ERI_Cnt Register
313029282726252423222120191817161514131211109876543210
RESERVEDECNT
R-0hR-0h
Table 43-343 DMA_CH0_RX_ERI_Cnt Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11-0ECNTR0hERI Counter
When ERIC bit of DMA_CH(#i)_RX_Control register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet.

43.7.3.251 DMA_CH1_Control Register (Offset = 1180h) [Reset = 0h]

DMA_CH1_Control is shown in Figure 43-290 and described in Table 43-344.

Return to the Summary Table.

The DMA Channeli Control register specifies the MSS value for segmentation, length to skip between two descriptors, and also the features such as header splitting and 8xPBL mode.

Figure 43-290 DMA_CH1_Control Register
3130292827262524
RESERVEDSPH
R-0hR/W-0h
2322212019181716
RESERVEDDSLRESERVEDPBLx8
R-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDMSS
R-0hR/W-0h
76543210
MSS
R/W-0h
Table 43-344 DMA_CH1_Control Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved.
24SPHR/W0hSplit Headers
When this bit is set, the DMA splits the header and payload in the Receive path. The DMA writes the header to the Buffer Address1 of RDES0. The DMA writes the payload to the buffer to which the Buffer Address2 is pointing.
The software must ensure that the header fits into the Receive buffers. If the header length exceeds the receive buffer size, the DMA does not split the header and payload.
This bit is available only if Enable Split Header Structure option is selected.
0h = Split Headers feature is disabled : 0x0
1h = Split Headers feature is enabled : 0x1
23-21RESERVEDR0hReserved.
20-18DSLR/W0hDescriptor Skip Length
This bit specifies the Word, Dword, or Lword number (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor.
When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous.
17RESERVEDR0hReserved.
16PBLx8R/W0h8xPBL mode
When this bit is set, the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.
0h = 8xPBL mode is disabled : 0x0
1h = 8xPBL mode is enabled : 0x1
15-14RESERVEDR0hReserved.
13-0MSSR/W0hMaximum Segment Size
This field specifies the maximum segment size that should be used while segmenting the packet. This field is valid only if the TSE bit of DMA_CH0_Tx_Control register is set.
The value programmed in this field must be more than the configured Datawidth in bytes. It is recommended to use a MSS value of 64 bytes or more.

43.7.3.252 DMA_CH1_Tx_Control Register (Offset = 1184h) [Reset = 0h]

DMA_CH1_Tx_Control is shown in Figure 43-291 and described in Table 43-345.

Return to the Summary Table.

The DMA Channeli Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights.

Figure 43-291 DMA_CH1_Tx_Control Register
3130292827262524
RESERVEDRESERVEDRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVEDETICTxPBL
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDTSERESERVED
R-0hR-0hR/W-0hR-0h
76543210
RESERVEDOSFTCWST
R-0hR/W-0hR/W-0hR/W-0h
Table 43-345 DMA_CH1_Tx_Control Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved.
28RESERVEDR0hReserved.
27-24RESERVEDR0hReserved.
23RESERVEDR0hReserved.
22ETICR/W0hEarly Transmit Interrupt Control
When this bit is set, Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set.

When this bit is reset, ETI is set only after a complete packet is transferred to the MTL TX FIFO memory.
0h = Early Transmit Interrupt is disabled : 0x0
1h = Early Transmit Interrupt is enabled : 0x1
21-16TxPBLR/W0hTransmit Programmable Burst Length
These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior.
To transfer more than 32 beats, perform the following steps:
1. Set the 8xPBL mode in DMA_CH0_Control register.
2. Set the TxPBL.
Note: The maximum value of TxPBL must be less than or equal to half the Tx Queue size (TQS field of MTL_TxQ[n]_Operation_Mode register) in terms of beats. This is required so that the Tx Queue has space to store at least another Tx PBL worth of data while the MTL Tx Queue Controller is transferring data to MAC. For example, in 64-bit data width configurations the total locations in Tx Queue of size 512 bytes is 64, TxPBL and 8xPBL needs to be programmed to less than or equal to 32.
15RESERVEDR0hReserved.
14-13RESERVEDR0hReserved.
12TSER/W0hTCP Segmentation Enabled
When this bit is set, the DMA performs the TCP segmentation or UDP Segmentation/Fragmentation for packets in this channel. The TCP segmentation or UDP packet's segmentation/Fragmentation is done only for those packets for which the TSE bit (TDES0[19]) is set in the Tx Normal descriptor.When this bit is set, the TxPBL value must be greater than 4.
0h = TCP Segmentation is disabled : 0x0
1h = TCP Segmentation is enabled : 0x1
11-5RESERVEDR0hReserved.
4OSFR/W0hOperate on Second Packet
When this bit is set, it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained.
0h = Operate on Second Packet disabled : 0x0
1h = Operate on Second Packet enabled : 0x1
3-1TCWR/W0hTransmit Channel Weight
This field indicates the weight assigned to the corresponding Transmit channel. When reset is complete, this field is set to 0 for all channels by default, resulting in equal weights to all channels.
0STR/W0hStart or Stop Transmission Command
When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted.
The DMA tries to acquire descriptor from either of the following positions:
- The current position in the list
This is the base address of the Transmit list set by the DMA_CH0_TxDesc_List_Address register.
- The position at which the transmission was previously stopped
If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the DMA_CH0_Status register is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the DMA_CH0_TxDesc_List_Address register, the DMA behavior is unpredictable.
When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program DMA_CH0_TxDesc_List_Address register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state.
0h = Stop Transmission Command : 0x0
1h = Start Transmission Command : 0x1

43.7.3.253 DMA_CH1_Rx_Control Register (Offset = 1188h) [Reset = 0h]

DMA_CH1_Rx_Control is shown in Figure 43-292 and described in Table 43-346.

Return to the Summary Table.

The DMA Channeli Receive Control register controls the Rx features such as PBL, buffer size, and extended status.

Figure 43-292 DMA_CH1_Rx_Control Register
3130292827262524
RPFRESERVEDRESERVED
R/W-0hR-0hR-0h
2322212019181716
RESERVEDERICRxPBL
R-0hR/W-0hR/W-0h
15141312111098
RESERVEDRBSZ_13_y
R-0hR/W-0h
76543210
RBSZ_13_yRBSZ_x_0SR
R/W-0hR-0hR/W-0h
Table 43-346 DMA_CH1_Rx_Control Register Field Descriptions
BitFieldTypeResetDescription
31RPFR/W0hRx Packet Flush.
When this bit is set to 1, then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel, when it is stopped. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this RxDMA was stopped, get flushed out. The packets that are received by the MAC after the RxDMA is re-started are routed to the RxDMA. The flushing happens on the Read side of the Rx Queue.
When this bit is set to 0, the DWC_ether_qos not flush the packet in the Rx Queue destined to this RxDMA Channel when it is STOP state. This may in turn cause head-of-line blocking in the corresponding RxQueue.
0h = Rx Packet Flush is disabled : 0x0
1h = Rx Packet Flush is enabled : 0x1
30-28RESERVEDR0hReserved.
27-24RESERVEDR0hReserved.
23RESERVEDR0hReserved.
22ERICR/W0hEarly Receive Interrupt Control
When this bit is set, Early Receive Interrupt (ERI) status is set after completion of every burst transfer of data from the Rx DMA to the buffer.

When this bit is reset, ERI is set only after a complete buffer is filled up by the RxDMA.
0h = Early Receive Interrupt is disabled : 0x0
1h = Early Receive Interrupt is enabled : 0x1
21-16RxPBLR/W0hReceive Programmable Burst Length
These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior.
To transfer more than 32 beats, perform the following steps:
1. Set the 8xPBL mode in the DMA_CH0_Control register.
2. Set the RxPBL.
Note: The maximum value of RxPBL must be less than or equal to half the Rx Queue size (RQS field of MTL_RxQ[n]_Operation_Mode register) in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the Rx DMA is transferring a block of data. For example, in 64-bit data width configurations the total locations in Rx Queue of size 512 bytes is 64, so RxPBL and 8xPBL needs to be programmed to less than or equal to 32.
15RESERVEDR0hReserved.
14-3RBSZ_13_yR/W0hReceive Buffer size High
RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is applicable to payload buffers when split headers are enabled.
Note: The buffer size must be a multiple of 4, 8, or 16 depending on the data bus widths (32-bit, 64-bit, or 128-bit respectively). This is required even if the value of buffer address pointer is not aligned to data bus width. Hence the lower RBSZ_x_0 bits are read-only and the value is considered as all-zero. Thus the RBSZ_13_y indicates the buffer size in terms of locations (with the width same as bus-width).
2-1RBSZ_x_0R0hReceive Buffer size Low
RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration.
This field is of width 2, 3, or 4 bits for 32-bit, 64-bit, or 128-bit data bus width respectively. This field is read-only (RO).
0SRR/W0hStart or Stop Receive
When this bit is set, the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets.
The DMA tries to acquire descriptor from either of the following positions:
- The current position in the list
This is the address set by the DMA_CH0_RxDesc_List_Address register.
- The position at which the Rx process was previously stopped
If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the DMA_CH0_Status register is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the DMA_CH0_RxDesc_List_Address register, the DMA behavior is unpredictable.
When this bit is reset, the Rx DMA operation is stopped after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state.
0h = Stop Receive : 0x0
1h = Start Receive : 0x1

43.7.3.254 DMA_CH1_TxDesc_List_Address Register (Offset = 1194h) [Reset = 0h]

DMA_CH1_TxDesc_List_Address is shown in Figure 43-293 and described in Table 43-347.

Return to the Summary Table.

The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low.
You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in DMA_CH0_Tx_Control register. When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address. If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier.

Figure 43-293 DMA_CH1_TxDesc_List_Address Register
3130292827262524
TDESLA
R/W-0h
2322212019181716
TDESLA
R/W-0h
15141312111098
TDESLA
R/W-0h
76543210
TDESLARESERVED
R/W-0hR-0h
Table 43-347 DMA_CH1_TxDesc_List_Address Register Field Descriptions
BitFieldTypeResetDescription
31-2TDESLAR/W0hStart of Transmit List
This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO).
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.255 DMA_CH1_RxDesc_List_Address Register (Offset = 119Ch) [Reset = 0h]

DMA_CH1_RxDesc_List_Address is shown in Figure 43-294 and described in Table 43-348.

Return to the Summary Table.

The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list.
This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory space of the application and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given. You can write to this register only when Rx DMA has stopped, that is, SR bit is set to zero in DMA_CH0_Rx_Control register. When stopped, this register can be written with a new descriptor list address.
When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.

Figure 43-294 DMA_CH1_RxDesc_List_Address Register
3130292827262524
RDESLA
R/W-0h
2322212019181716
RDESLA
R/W-0h
15141312111098
RDESLA
R/W-0h
76543210
RDESLARESERVED
R/W-0hR-0h
Table 43-348 DMA_CH1_RxDesc_List_Address Register Field Descriptions
BitFieldTypeResetDescription
31-2RDESLAR/W0hStart of Receive List
This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width and internally takes these bits as all-zero. Therefore, these LSB bits are read-only (RO).
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.256 DMA_CH1_TxDesc_Tail_Pointer Register (Offset = 11A0h) [Reset = 0h]

DMA_CH1_TxDesc_Tail_Pointer is shown in Figure 43-295 and described in Table 43-349.

Return to the Summary Table.

The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor.

Figure 43-295 DMA_CH1_TxDesc_Tail_Pointer Register
3130292827262524
TDTP
R/W-0h
2322212019181716
TDTP
R/W-0h
15141312111098
TDTP
R/W-0h
76543210
TDTPRESERVED
R/W-0hR-0h
Table 43-349 DMA_CH1_TxDesc_Tail_Pointer Register Field Descriptions
BitFieldTypeResetDescription
31-2TDTPR/W0hTransmit Descriptor Tail Pointer
This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the descriptors between the head and the tail pointer registers.
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.257 DMA_CH1_RxDesc_Tail_Pointer Register (Offset = 11A8h) [Reset = 0h]

DMA_CH1_RxDesc_Tail_Pointer is shown in Figure 43-296 and described in Table 43-350.

Return to the Summary Table.

The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor.

Figure 43-296 DMA_CH1_RxDesc_Tail_Pointer Register
3130292827262524
RDTP
R/W-0h
2322212019181716
RDTP
R/W-0h
15141312111098
RDTP
R/W-0h
76543210
RDTPRESERVED
R/W-0hR-0h
Table 43-350 DMA_CH1_RxDesc_Tail_Pointer Register Field Descriptions
BitFieldTypeResetDescription
31-2RDTPR/W0hReceive Descriptor Tail Pointer
This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors referenced between the head and the tail pointer registers.
The width of this field depends on the configuration:
- 31:2 for 32-bit configuration
- 31:3 for 64-bit configuration
- 31:4 for 128-bit configuration
1-0RESERVEDR0h

43.7.3.258 DMA_CH1_TxDesc_Ring_Length Register (Offset = 11ACh) [Reset = 0h]

DMA_CH1_TxDesc_Ring_Length is shown in Figure 43-297 and described in Table 43-351.

Return to the Summary Table.

The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring.

Figure 43-297 DMA_CH1_TxDesc_Ring_Length Register
313029282726252423222120191817161514131211109876543210
RESERVEDTDRL
R-0hR/W-0h
Table 43-351 DMA_CH1_TxDesc_Ring_Length Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved.
9-0TDRLR/W0hTransmit Descriptor Ring Length
This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For example, You can program any value up to 0x3FF in this field. This field is 10 bits wide, if you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9.

43.7.3.259 DMA_CH1_RxDesc_Ring_Length Register (Offset = 11B0h) [Reset = 0h]

DMA_CH1_RxDesc_Ring_Length is shown in Figure 43-298 and described in Table 43-352.

Return to the Summary Table.

The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring.

Figure 43-298 DMA_CH1_RxDesc_Ring_Length Register
313029282726252423222120191817161514131211109876543210
RESERVEDRDRL
R-0hR/W-0h
Table 43-352 DMA_CH1_RxDesc_Ring_Length Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved.
9-0RDRLR/W0hReceive Descriptor Ring Length
This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example, You can program any value up to 0x3FF in this field. This field is 10 bits wide, if you program 0x3FF, you can have 1024 descriptors. If you want to have 10 descriptors, program it to a value of 0x9.

43.7.3.260 DMA_CH1_Interrupt_Enable Register (Offset = 11B4h) [Reset = 0h]

DMA_CH1_Interrupt_Enable is shown in Figure 43-299 and described in Table 43-353.

Return to the Summary Table.

The Channeli Interrupt Enable register enables the interrupts reported by the Status register.

Figure 43-299 DMA_CH1_Interrupt_Enable Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NIEAIECDEEFBEEERIEETIERWTERSE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RBUERIERESERVEDTBUETXSETIE
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-353 DMA_CH1_Interrupt_Enable Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15NIER/W0hNormal Interrupt Summary Enable
When this bit is set, the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register:
- Bit 0: Transmit Interrupt
- Bit 2: Transmit Buffer Unavailable
- Bit 6: Receive Interrupt
- Bit 11: Early Receive Interrupt
When this bit is reset, the normal interrupt summary is disabled.
0h = Normal Interrupt Summary is disabled : 0x0
1h = Normal Interrupt Summary is enabled : 0x1
14AIER/W0hAbnormal Interrupt Summary Enable
When this bit is set, the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register:
- Bit 1: Transmit Process Stopped
- Bit 7: Rx Buffer Unavailable
- Bit 8: Receive Process Stopped
- Bit 9: Receive Watchdog Timeout
- Bit 10: Early Transmit Interrupt
- Bit 12: Fatal Bus Error
- Bit 13: Context Descriptor Error
When this bit is reset, the abnormal interrupt summary is disabled.
0h = Abnormal Interrupt Summary is disabled : 0x0
1h = Abnormal Interrupt Summary is enabled : 0x1
13CDEER/W0hContext Descriptor Error Enable
When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. When this bit is reset, the Descriptor error interrupt is disabled.
0h = Context Descriptor Error is disabled : 0x0
1h = Context Descriptor Error is enabled : 0x1
12FBEER/W0hFatal Bus Error Enable
When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. When this bit is reset, the Fatal Bus Error error interrupt is disabled.
0h = Fatal Bus Error is disabled : 0x0
1h = Fatal Bus Error is enabled : 0x1
11ERIER/W0hEarly Receive Interrupt Enable
When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. When this bit is reset, the Early Receive interrupt is disabled.
0h = Early Receive Interrupt is disabled : 0x0
1h = Early Receive Interrupt is enabled : 0x1
10ETIER/W0hEarly Transmit Interrupt Enable
When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. When this bit is reset, the Early Transmit interrupt is disabled.
0h = Early Transmit Interrupt is disabled : 0x0
1h = Early Transmit Interrupt is enabled : 0x1
9RWTER/W0hReceive Watchdog Timeout Enable
When this bit is set along with the AIE bit, the Receive Watchdog Timeout interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout interrupt is disabled.
0h = Receive Watchdog Timeout is disabled : 0x0
1h = Receive Watchdog Timeout is enabled : 0x1
8RSER/W0hReceive Stopped Enable
When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped interrupt is disabled.
0h = Receive Stopped is disabled : 0x0
1h = Receive Stopped is enabled : 0x1
7RBUER/W0hReceive Buffer Unavailable Enable
When this bit is set along with the AIE bit, the Receive Buffer Unavailable interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable interrupt is disabled.
0h = Receive Buffer Unavailable is disabled : 0x0
1h = Receive Buffer Unavailable is enabled : 0x1
6RIER/W0hReceive Interrupt Enable
When this bit is set along with the NIE bit, the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
0h = Receive Interrupt is disabled : 0x0
1h = Receive Interrupt is enabled : 0x1
5-3RESERVEDR0hReserved.
2TBUER/W0hTransmit Buffer Unavailable Enable
When this bit is set along with the NIE bit, the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable interrupt is disabled.
0h = Transmit Buffer Unavailable is disabled : 0x0
1h = Transmit Buffer Unavailable is enabled : 0x1
1TXSER/W0hTransmit Stopped Enable
When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. When this bit is reset, the Transmission Stopped interrupt is disabled.
0h = Transmit Stopped is disabled : 0x0
1h = Transmit Stopped is enabled : 0x1
0TIER/W0hTransmit Interrupt Enable
When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled.
0h = Transmit Interrupt is disabled : 0x0
1h = Transmit Interrupt is enabled : 0x1

43.7.3.261 DMA_CH1_Rx_Interrupt_Watchdog_Timer Register (Offset = 11B8h) [Reset = 0h]

DMA_CH1_Rx_Interrupt_Watchdog_Timer is shown in Figure 43-300 and described in Table 43-354.

Return to the Summary Table.

The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value, it enables the watchdog timer for the RI bit of the DMA_CHi_Status register.

Figure 43-300 DMA_CH1_Rx_Interrupt_Watchdog_Timer Register
31302928272625242322212019181716
RESERVEDRWTU
R-0hR/W-0h
1514131211109876543210
RESERVEDRWT
R-0hR/W-0h
Table 43-354 DMA_CH1_Rx_Interrupt_Watchdog_Timer Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved.
17-16RWTUR/W0hReceive Interrupt Watchdog Timer Count Units
This fields indicates the number of system clock cycles corresponding to one unit in RWT field.
- 2'b00: 256
- 2'b01: 512
- 2'b10: 1024
- 2'b11: 2048
For example, when RWT=2 and RWTU=1, the watchdog timer is set for 2*512=1024 system clock cycles.
15-8RESERVEDR0hReserved.
7-0RWTR/W0hReceive Interrupt Watchdog Timer Count
This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the DMA_CH0_Status register, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30].
When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet.

43.7.3.262 DMA_CH1_Current_App_TxDesc Register (Offset = 11C4h) [Reset = 0h]

DMA_CH1_Current_App_TxDesc is shown in Figure 43-301 and described in Table 43-355.

Return to the Summary Table.

The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA.

Figure 43-301 DMA_CH1_Current_App_TxDesc Register
313029282726252423222120191817161514131211109876543210
CURTDESAPTR
R-0h
Table 43-355 DMA_CH1_Current_App_TxDesc Register Field Descriptions
BitFieldTypeResetDescription
31-0CURTDESAPTRR0hApplication Transmit Descriptor Address Pointer
The DMA updates this pointer during Tx operation. This pointer is cleared on reset.

43.7.3.263 DMA_CH1_Current_App_RxDesc Register (Offset = 11CCh) [Reset = 0h]

DMA_CH1_Current_App_RxDesc is shown in Figure 43-302 and described in Table 43-356.

Return to the Summary Table.

The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA.

Figure 43-302 DMA_CH1_Current_App_RxDesc Register
313029282726252423222120191817161514131211109876543210
CURRDESAPTR
R-0h
Table 43-356 DMA_CH1_Current_App_RxDesc Register Field Descriptions
BitFieldTypeResetDescription
31-0CURRDESAPTRR0hApplication Receive Descriptor Address Pointer
The DMA updates this pointer during Rx operation. This pointer is cleared on reset.

43.7.3.264 DMA_CH1_Current_App_TxBuffer Register (Offset = 11D4h) [Reset = 0h]

DMA_CH1_Current_App_TxBuffer is shown in Figure 43-303 and described in Table 43-357.

Return to the Summary Table.

The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA.

Figure 43-303 DMA_CH1_Current_App_TxBuffer Register
313029282726252423222120191817161514131211109876543210
CURTBUFAPTR
R-0h
Table 43-357 DMA_CH1_Current_App_TxBuffer Register Field Descriptions
BitFieldTypeResetDescription
31-0CURTBUFAPTRR0hApplication Transmit Buffer Address Pointer
The DMA updates this pointer during Tx operation. This pointer is cleared on reset.

43.7.3.265 DMA_CH1_Current_App_RxBuffer Register (Offset = 11DCh) [Reset = 0h]

DMA_CH1_Current_App_RxBuffer is shown in Figure 43-304 and described in Table 43-358.

Return to the Summary Table.

The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA.

Figure 43-304 DMA_CH1_Current_App_RxBuffer Register
313029282726252423222120191817161514131211109876543210
CURRBUFAPTR
R-0h
Table 43-358 DMA_CH1_Current_App_RxBuffer Register Field Descriptions
BitFieldTypeResetDescription
31-0CURRBUFAPTRR0hApplication Receive Buffer Address Pointer
The DMA updates this pointer during Rx operation. This pointer is cleared on reset.

43.7.3.266 DMA_CH1_Status Register (Offset = 11E0h) [Reset = 0h]

DMA_CH1_Status is shown in Figure 43-305 and described in Table 43-359.

Return to the Summary Table.

The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA.
Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx DMA Channels and Tx DMA Channels.

Figure 43-305 DMA_CH1_Status Register
31302928272625242322212019181716
RESERVEDREBTEB
R-0hR-0hR-0h
1514131211109876543210
NISAISCDEFBEERIETIRWTRPSRBURIRESERVEDTBUTPSTI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 43-359 DMA_CH1_Status Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved.
21-19REBR0hRx DMA Error Bits
This field indicates the type of error that caused a Bus Error. For example, error response on the AHB or AXI interface.
Bit 21
- 1'b1: Error during data transfer by Rx DMA
- 1'b0: No Error during data transfer by Rx DMA
Bit 20
- 1'b1: Error during descriptor access
- 1'b0: Error during data buffer access
Bit 19
- 1'b1: Error during read transfer
- 1'b0: Error during write transfer
This field is valid only when the FBE bit is set. This field does not generate an interrupt.
18-16TEBR0hTx DMA Error Bits
This field indicates the type of error that caused a Bus Error. For example, error response on the AHB or AXI interface.
Bit 18
- 1'b1: Error during data transfer by Tx DMA
- 1'b0: No Error during data transfer by Tx DMA
Bit 17
- 1'b1: Error during descriptor access
- 1'b0: Error during data buffer access
Bit 16
- 1'b1: Error during read transfer
- 1'b0: Error during write transfer
This field is valid only when the FBE bit is set. This field does not generate an interrupt.
15NISR/W0hNormal Interrupt Summary
Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register:
- Bit 0: Transmit Interrupt
- Bit 2: Transmit Buffer Unavailable
- Bit 6: Receive Interrupt
- Bit 11: Early Receive Interrupt
Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH0_Interrupt_Enable register) affect the Normal Interrupt Summary bit.
This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Normal Interrupt Summary status not detected : 0x0
1h = Normal Interrupt Summary status detected : 0x1
14AISR/W0hAbnormal Interrupt Summary
Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register:
- Bit 1: Transmit Process Stopped
- Bit 7: Receive Buffer Unavailable
- Bit 8: Receive Process Stopped
- Bit 10: Early Transmit Interrupt
- Bit 12: Fatal Bus Error
- Bit 13: Context Descriptor Error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Abnormal Interrupt Summary status not detected : 0x0
1h = Abnormal Interrupt Summary status detected : 0x1
13CDER/W0hContext Descriptor Error
This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Context Descriptor Error status not detected : 0x0
1h = Context Descriptor Error status detected : 0x1
12FBER/W0hFatal Bus Error
This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Fatal Bus Error status not detected : 0x0
1h = Fatal Bus Error status detected : 0x1
11ERIR/W0hEarly Receive Interrupt
This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory.

When ERIC=0, this bit is set only after the Rx DMA has filled up a complete receive buffer with packet data. When ERIC=1, this bit is set after every burst transfer of data from the Rx DMA to the buffer.

The setting of RI bit automatically clears this bit.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Early Receive Interrupt status not detected : 0x0
1h = Early Receive Interrupt status detected : 0x1
10ETIR/W0hEarly Transmit Interrupt
This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory.

When ETIC=0, this bit is set only after the Tx DMA has transferred a complete packet to MTL. When ETIC=1, this bit is set after completion of (partial) packet data transfer from buffers in the Transmit descriptor in which IOC=1.

Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Early Transmit Interrupt status not detected : 0x0
1h = Early Transmit Interrupt status detected : 0x1
9RWTR/W0hReceive Watchdog Timeout
This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
0h = Receive Watchdog Timeout status not detected : 0x0
1h = Receive Watchdog Timeout status detected : 0x1
8RPSR/W0hReceive Process Stopped
This bit is asserted when the Rx process enters the Stopped state.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Process Stopped status not detected : 0x0
1h = Receive Process Stopped status detected : 0x1
7RBUR/W0hReceive Buffer Unavailable
This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Buffer Unavailable status not detected : 0x0
1h = Receive Buffer Unavailable status detected : 0x1
6RIR/W0hReceive Interrupt
This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor.
The reception remains in the Running state.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Receive Interrupt status not detected : 0x0
1h = Receive Interrupt status detected : 0x1
5-3RESERVEDR0hReserved.
2TBUR/W0hTransmit Buffer Unavailable
This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit Process state transitions.
To resume processing the Transmit descriptors, the application should do the following:
1. Change the ownership of the descriptor by setting Bit 31 of TDES3.
2. Issue a Transmit Poll Demand command.
For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Buffer Unavailable status not detected : 0x0
1h = Transmit Buffer Unavailable status detected : 0x1
1TPSR/W0hTransmit Process Stopped
This bit is set when the transmission is stopped.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Process Stopped status not detected : 0x0
1h = Transmit Process Stopped status detected : 0x1
0TIR/W0hTransmit Interrupt
This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor.
Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.
0h = Transmit Interrupt status not detected : 0x0
1h = Transmit Interrupt status detected : 0x1

43.7.3.267 DMA_CH1_Miss_Frame_Cnt Register (Offset = 11E4h) [Reset = 0h]

DMA_CH1_Miss_Frame_Cnt is shown in Figure 43-306 and described in Table 43-360.

Return to the Summary Table.

This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH${i}_Rx_Control register.

Figure 43-306 DMA_CH1_Miss_Frame_Cnt Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
MFCORESERVEDMFC
R-0hR-0hR-0h
76543210
MFC
R-0h
Table 43-360 DMA_CH1_Miss_Frame_Cnt Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved.
15MFCOR0hOverflow status of the MFC Counter
When this bit is set then the MFC counter does not get incremented
further. The bit gets cleared when this register is read.
Access restriction applies. Clears on read. Self-set to 1 on internal event.
14-11RESERVEDR0hReserved.
10-0MFCR0hDropped Packet Counters
This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing
RPF field in DMA_CH${i}_Rx_Control register. The counter gets cleared when this register is read.
Access restriction applies. Clears on read. Self-set to 1 on internal event.

43.7.3.268 DMA_CH1_RX_ERI_Cnt Register (Offset = 11ECh) [Reset = 0h]

DMA_CH1_RX_ERI_Cnt is shown in Figure 43-307 and described in Table 43-361.

Return to the Summary Table.

Figure 43-307 DMA_CH1_RX_ERI_Cnt Register
313029282726252423222120191817161514131211109876543210
RESERVEDECNT
R-0hR-0h
Table 43-361 DMA_CH1_RX_ERI_Cnt Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11-0ECNTR0hERI Counter
When ERIC bit of DMA_CH(#i)_RX_Control register is set, this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet.