SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
FILE: adc_ex15_high_priority_soc.c
This example demonstrates configuration of ADC high priority SOCs in order to sample fastest control loop signals with high priority while low priority signals are sampled with default round robin priority.
ADC PPB block is configured to capture delay between SOC trigger and actual start of the SOC sampling in order to quantify the jitters in sampling high priority signals due to low priority signals. The delay in processing an SOC is captured in ADCPPBxSTAMP.DLYSTAMP register field and the total delay in sampling an SOC is equal to (DLYSTAMP - 2) cycles. In an optimal design the high priority SOC is expected to have less delay between SOC trigger and actual start of the sample.
In this example ADCA, ADCB and ADCD are configured to sample both high and low priority signals. SOC0-3 are configured as high priority SOCs while rest are configured with default round-robin priority. ADCA SOC0-3 are configured as high priority SOCs sampling channels A0-A3, ADCB SOC0-1 are configured as high priority SOCs sampling channels B0-B1 and ADCD SOC0-1 are configured as high priority SOCs sampling channels D0-D1. For sampling low priority signals SOC4-SOC5 are configured sampling channel 4 and channel 13 respectively for ADCA and channel 4 and 5 for ADCB and ADCD. For ADCA, channel 13 is connected to internal temperature sensor output and hence no signal needs to be connected to channel A13. High priority SOC results are read in ADCINT1 ISR while low priority SOC results are read in idle loop.
This example has two modes of operation as follows. Desired mode can be selected by configuring the EX_ADC_LP_SOC_TRIGGER macro accordingly. Mode 0: ADCINT as round robin SOC trigger Mode 1: EPWM2 as round robin SOC trigger
In mode 0, EPWM1 is configured as trigger for high priority SOCs while ADCINT1 is configured as low priority SOC trigger. ADCINT1 is configured to be triggered on completion of SOC1 conversion which in turn trigger low priority SOCs 4 and 5 and ADCINT2 is configured to be triggered on completion of SOC5. ADC result for high priority SOCs are read in ADCINT ISR while low priority SOC results are read in idle loop. ADCINT3 is configured to be triggered on completion of SOC3 and hence SOC2-SOC3 results for ADCA are read post checking if the conversion is complete in ADCINT1 ISR.
In mode 0, SOC0-SOC1 for all ADCs will experience minimal delay(0 and 1 conversions) in processing due to the high priority configuration. For ADCA, SOC4-SOC5 are triggered when SOC2-SOC3 conversion is ongoing, hence SOC4-SOC5 will see some delay(2 and 3 conversions) in processing as expected. For ADCB and ADCD, SOC4-SOC5 will see minimal delay (0 and 1 conversions) in processing as expected.
In mode 1, EPWM1 is configured as trigger for high priority SOCs while EPWM2 is configured as low priority SOC trigger. ADCINT1 is configured to be triggered on completion of SOC3 conversion and ADC result for high priority SOCs are read in the ADCINT ISR. Low priority SOCs 4 and 5 are triggered through EPWM2 and ADCINT2 is configured to be triggered on completion of SOC5. The result for low priority SOCs are read in background loop. Since, SOC4-5 are triggered post SOC2-3 conversion(due to configured EPWM1 and EPWM2 trigger frequency and duty), SOC4-SOC5 will have minimal delay(0 and 1 conversions respectively) in SOC processing as expected.
Optimization Level: Example is expected to run with opt level = O2.
To view ADC results, put breakpoint at the statement where indexB is reset to zero in idle loop.
External Connections
Watch Variables
ADC Results:
SOC conversion delays: