SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

12.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)

Note: During the entirety of an asynchronous write operation, the EM1OE pin is driven high.

An asynchronous write is performed when any of the requesters mentioned in Section 12.2.2 request a write to memory in the asynchronous bank of EMIF. After the request is received, a write operation is initiated once the request becomes the EMIF's highest priority task, according to the priority scheme detailed in Section 12.2.13. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles are performed by the EMIF until the entire request is fulfilled. The details of an asynchronous write operation in select strobe mode are described in Table 12-24. Also, Figure 12-14 shows an example timing diagram of a basic write operation.

Table 12-24 Asynchronous Write Operation in Select Strobe Mode

Time Interval	Pin Activity in Select Strobe Mode
Turnaround period	Once the write operation becomes the highest priority task for the EMIF, the EMIF waits for the programmed number of turnaround cycles before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA field of the asynchronous n configuration register (ASYNC_CSn_CR). Between each access (Write or Read) EMIF inserts two cycles of delay even though TA field is programmed as 0. After the EMIF has waited for the turnaround cycles to complete, the EMIF again checks to make sure that the write operation is still the highest priority task. If so, the EMIF proceeds to the setup period of the operation. If the write operation is no longer the highest priority task, the EMIF terminates the operation.
Start of the setup period	The following actions occur at the start of the setup period: The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values in ASYNC_CSn_CR. The address pins EM1A and EM1BA and the data pins EM1D become valid. The EM1A and EM1BA pins carry the values described in Section 12.2.6.1. The EM1DQM pins become active as byte enables.
Strobe period	The following actions occur at the start of the strobe period of a write operation: EM1CS[n] (n = 2, 3, or 4) and EM1WE fall The following actions occur on the rising edge of the clock which is concurrent with the end of the strobe period: EM1CS[n] (n = 2, 3, or 4) and EM1WE rise In Figure 12-14, EM1WAIT is inactive. If EM1WAIT is instead activated, the strobe period can be extended by the external device to give more time to accept the data. Section 12.2.6.6 contains more details on using the EM1WAIT pin.
End of the hold period	At the end of the hold period: The address pins EM1A and EM1BA become invalid The data pins become invalid The EM1DQM pins become invalid The EMIF can be required to issue additional write operations to a device with a small data bus width to complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this case. If the entire word access has been completed, the EMIF returns to the previous state unless another asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF instead enters directly into the turnaround period for the pending read or write operation.

F2838x Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode

Figure 12-14 Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode