SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

41.6.2 CM Subsystem Exceptions Handling

Table 41-2 provides information on different exceptions supported by NVIC on the CM subsystem.

Table 41-2 CM Subsystem Exceptions

Exception Type	Vector Number	Priority	Description
Reset	1	-3 (highest	This exception is invoked on power up and on any other reset. On the first instruction, Reset drops to the lowest priority and then is called the base level of activation. This exception is asynchronous.
Non-Maskable Interrupt(NMI)	2	-2	A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset.
Hard Fault	3	-1	This exception is caused by all classes of Fault when the fault cannot activate due to priority or the configurable fault handler has been disabled. This exception is synchronous.
Memory Management	4	Configurable	This exception is caused by an MPU mismatch, including access violation and no match. This exception is synchronous.
Bus Fault	5	Configurable	A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled.
Usage Fault	6	Configurable	This exception is caused by a usage fault, such as an undefined instruction executed or an illegal state transition attempt. This exception is synchronous.

From the exceptions in Table 41-2, the NMI and bus faults are generated by the digital subsystem, whereas memory management errors are generated internally by the M4 MPU.

Bus Fault Exceptions:

For all uncorrectable memory errors during M4 CPU reads or writes (address, parity, or double data error), HRESP-based and HREADY-based error responses are generated by the memory C28 logic.

Write Accesses:

When an HRESP-error is generated for write accesses, if the intended write was a stack push, STKERR status is set by the NVIC upon seeing the bus fault indication for the stack push operation. If the application so prefers, the application can treat a STKERR as a low-priority exception and pend the same, except when stacking for an exception.

Read Accesses:

For all uncorrectable errors during reads, the same HRESP-error indication is generated. The M4 core uses this error indication in the following manner:

For bus errors during normal data reads, the M4 can generate a bus fault, but the application can treat this as a lower priority, thereby enabling a higher priority exception to be serviced by the CPU. As an example, there can be a bus fault in a user thread and still the CPU can service an interrupt to handle critical interrupts - the bus fault can be handled afterwards. But if the read occurs during an ISR bus fault, the read is treated as a hard fault, since the read is in code for an exception that must never fault.
For bus errors during stack pops, the NVIC sets the UNSTKERR status indication and the M4 generates a bus fault.
For bus errors during vector table reads, the NVIC sets VECTTBL and the M4 generates a bus fault. If there is a double fault when the bus fault handler tries to read the vector, the M4 CPU enters a LOCKUP condition. In this condition, the M4 WDT timers time out and issue a reset to the system.
For bus errors during fetches, even if the M4 sees an error response, M4 does not internally bus fault unless the CPU is decoding the erroneous instruction fetched.

For more details on how the remaining exceptions are generated by the Cortex^®-M4 CPU, refer to Section 41.7.

Refer to the ROM Code and Peripheral Booting chapter for more details on how boot ROM handles HARDFAULT exceptions, if the exception occurs during boot ROM execution.

On the CM subsystem, the following errors generate a BUSFAULT:

RAMUNCERR - RAM Uncorrectable error. This is a double bit error generated by the RAM wrapper logic as a bus error.
RAMACCVIOL - Ram Access violation.