SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

3.7.7.1 Missing Clock Detection Logic

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source. This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift on the OSCCLK.

This circuit monitors the OSCLK (primary clock) using the 10MHz clock provided by the INTOSC1 (secondary clock) as a backup clock. This circuit functions as:

The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named MCDPCNT). This counter is asynchronously reset with XRSn.
The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named MCDSCNT). This counter is asynchronously reset with XRSn.
Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not slower than INTOSC1 by a factor of 64, MCDSCNT never overflows.
If OSCCLK stops for some reason or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT overflows and a missing clock condition is detected on OSCCLK.
The above check is continuously active, unless the MCD is disabled using the MCDCR register (by making the MCLKOFF bit 1).
If the circuit ever detects a missing OSCCLK, the following occurs:
- The MCDSTS flag is set.
- The MCDSCNT counter is frozen to prevent further missing clock detection.
- The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to CPU1.NMIWDand CPU2.NMIWD.
- PLL is forcefully bypassed and the OSCCLK source is switched to INTOSC1 (System Clock Frequency = INTOSC1 Freq (10MHz)/SYSDIV). PLLMULT is zeroed out automatically in this case.
- While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully connected to INTOSC1.
- PLLRAWCLK going to the system is switched to INTOSC1 automatically.
If the MCLKCLR bit is written (this is a W=1 bit), the MCDSTS bit is cleared and the OSCCLK source is decided by the OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters to allow the circuit to re-evaluate missing clock detection. If the user wants to lock the PLL after missing clock detection, switch the clock source to INTOSC1 (using OSCCLKSRCSEL register), do an MCLKCLR, and re-lock the PLL.
The MCD is enabled at power up.

Figure 3-11 shows the missing clock logic functional flow.

Figure 3-11 Missing Clock Detection Logic

Note:

On a complete clock failure when OSCCLK is dead, it may take a maximum time of 8192 INTOSC1 cycles (that is, 0.8192ms) before the CLOCKFAIL signal goes high, after which:

NMI is generated
OSCCLK is switched to INTOSC1
PWM Trip happens