SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

7.3.7 BGCRC Golden CRC-32 Value Computation

The C28x is a little-endian, 16-bit word addressable CPU. Therefore, the 32-bit value of 0x12345678 stored at address 0x100 is stored in the C28x memory as shown in Table 7-2.

Table 7-2 Data Address Location Example 1

Address	0x100	0x101
Data	0x5678	0x1234

The BGCRC order of byte calculations of the above example is 0x78, 0x56, 0x34, 0x12 and yields 0x6A330D2D. The 32-bit polynomial 0x04C11DB7 is used with an initialization vector of 0x00000000. The following code snippet shows the effective bit processing. Processing for all 32-bits within a word occurs in a single cycle within the BGCRC hardware.

seed = 0x0UL; //Initialize With Seed
poly = 0x04C11DB7UL: //32-Bit Polynomial
crc32 = seed;

for(i=0; i<dataSize; i++)
{
         byteSwappedData = ((data[i] & 0x000000FF) << 24)|
                         = ((data[i] & 0x0000FF00) << 8) |
                         = ((data[i] & 0x00FF0000) >> 8) |
                         = ((data[i] & 0xFF000000) >> 24);
		
		crc32 = byteSwappedData^crc32;
		for(j=0; j<32; j++)
		{
			if(crc32 & 0x80000000) crc32 = (crc32 << 1)^poly;
			else crc32 = crc32 << 1;
			
			crc32 = crc32 & 0xFFFFFFFF;
		}
}

A second example (Table 7-3) with two 32-bit words, 0x12345678 and 0x9ABCDEF0 at address 0x100 and 0x102 successively, calculates the bytes in the order 0x78, 0x56, 0x34, 0x12, 0xDE, 0xBC, and 0x9A and yield 0x7E0B4164.

Table 7-3 Data Address Location Example 2

Address	0x100	0x101	0x102	0x103
Data	0x5678	0x1234	0xDEF0	0x9ABC

All data input to the BGCRC must align to a 32-bit boundary, both in the starting address and the size. It is possible to include 16-bit data within the span of data; however, when the data is read by the BGCRC, it always assume 32-bits and conform to the above calculation order. For example, if two 16-bit words (0xA0B1 and 0xC2D3) were placed in between the previous two 32-bit words (Table 7-4), the calculations are performed in byte order 0x78, 0x56, 0x34, 0x12, 0xB1, 0xA0, 0xD3, 0xC2, 0xF0, 0xDE, 0xBC, and 0x9A and yield 0x2AEFD987.

Table 7-4 Data Address Location Example 3

Address	0x100	0x101	0x102	0x103	0x104	0x105
Data	0x5678	0x1234	0xA0B1	0xC2D3	0xDEF0	0x9ABC