In this mode, the DCC is used by the
application to make sure that two clock signals maintain the correct frequency
ratio. Suppose the application wants to make sure that the PLL output signal always
maintains a fixed frequency relationship with the XTAL:
- In this case, the application
can use the XTAL as the Clock0 signal (for Counter0 and Valid0) and the PLL
output as the Clock1 (for Counter1).
- The seed values of Counter0,
Valid0 and Counter1 are selected based on the equations defined in Section 10.2.1 such that if the actual frequencies of Clock0 and Clock1 are equal to the
expected frequencies, then the Counter1 reaches zero during the count down
of the Valid0 counter.
- If the Counter1 reaches zero
during the count down of the Valid0 counter, then all the counters
(Counter0, Valid0, Counter1) are reloaded with the initial seed values.
- This sequence of counting
down and checking then continues as long as there is no error, or until the
DCC module is disabled.
- The counters must get
reloaded if the application resets and restarts the DCC module.
Error Conditions:
An error condition is generated by one
of the following:
- Counter1 counts down to 0
before Counter0 reaches 0. This means that Clock1 is faster than expected or
Clock0 is slower than expected. This condition includes the case when Clock0
is stuck at 1 or 0.
- Counter1 does not reach 0
even when Counter0 and Valid0 have both reached 0. This means that Clock1 is
slower than expected. This condition includes the case when Clock1 is stuck
at 1 or 0.
Any error freezes the counters from
counting. An application can then read out the counter values to help determine what
caused the error.