The Flash bank and pump consume a
significant amount of power when active. The Flash module provides a mechanism to
power-down Flash banks and pump. Special timers automatically sequence the power-up
of the CPU1 Flash bank, CPU2 Flash bank, and CM Flash bank independently
of each other. The shared charge pump
module includes an independent power-up timer as well.
The Flash bank and OTP memory operate
in three power modes: Sleep (lowest power), Standby, and Active (highest power)
- Sleep State
This is the state after a device reset. In this
state, a CPU data read or opcode fetch automatically initiates a change in power
mode to the standby state and then to the active state. During this transition
time to the active state, the CPU execution is automatically stalled.
- Standby State
This state uses more power than the sleep state,
but takes a shorter time to transition to the active or read state. In this
state, a CPU data read or opcode fetch automatically initiates a change in power
mode to the active state. During this transition time to the active state, the
CPU execution is automatically stalled. Once the Flash/OTP has reached the
active state, the CPU access completes as normal.
- Active or Read State
In this state, the bank and pump are in active
power mode state (highest power)
The charge pump operates in two power
modes:
- Sleep (lowest power)
- Active (highest power)
Any access to any Flash bank/OTP
causes the charge pump to go into active mode, if in sleep mode. An erase or program
command causes the charge pump and bank to become active. If any bank is in active
or in standby mode, the charge pump is in active mode, independent of the pump power
mode control configuration (PMPPWR bit field in the FPAC1 register).
To power
down the Flash pump, all three cores (CPU1, CPU2, and CM) must each power down the
Flash Pump without any Flash accesses in between. The Flash Pump does not enter
low-power mode if the following sequence of operations is not executed.
- When the system is ready to power
down the Flash completely, synchronize CPU1, CPU2, and CM. CM executes the Flash
power-down phase (steps 2, 3, and 4) while CPU1 and CPU2 wait for CM to complete
the Flash power-down sequence.
- Acquire the Pump Semaphore with
the CM.
- Change the CM Flash Bank Fall
Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
- Change the CM Flash Charge Pump
Fall Back power-mode to Sleep: FPAC1.PMPPWR = 0. Using IPC, notify CPU1 and CPU2
that the CM has completed the above sequence. After sending the notification,
wait until CPU1 and CPU2 have completed steps 5 to 11, and an IPC notification
has been received to confirm that all cores have completed the power-down
sequence.
- Acquire the Pump Semaphore with
the CPU2.
- Change the CPU2 Flash Bank Fall
Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
- Change the CPU2 Flash Charge Pump
Fall Back power mode to Sleep: FPAC1.PMPPWR = 0.
- Release the Pump Semaphore from
the CPU2. Using IPC, notify CPU1 that CPU2 has completed the power-down
sequence. After sending the notification, wait until CPU1 completes steps 9, 10
and 11.
- Acquire the Pump Semaphore with
the CPU1.
- Change the CPU1 Flash Bank Fall
Back power mode to Sleep: FBFALLBACK.BNKPWR = 0.
- Change the CPU1 Flash Charge Pump
Fall Back power mode to Sleep: FPAC1.PMPPWR = 0.
- Release the Pump Semaphore from
the CPU1. Using IPC, notify CPU2 and CM that CPU1 has completed the power-down
sequence so that all three (CPU1, CPU2, and CM) subsystems can continue.
The previously described procedure can only be executed
from RAM, not from Flash.
Note: Before
configuring FPAC1.PMPPWR as described above, be sure to gain exclusive control of
the Flash pump by using PUMPREQUEST register. Since the charge pump is shared
between CPU1-FMC, CPU2-FMC, and CM-FMC, the effective PMPPWR value used when
powering down the pump is the FMC (out of these three) that currently owns the pump.
The application code can check the current power mode of the Flash bank by reading
the FBPRDY register. The effective power mode of the charge pump is a logical OR of
the FBPRDY.PUMPRDY register bits in CPU1-FMC, CPU2-FMC, and CM-FMC. A value of 0 in
the PUMPRDY bit in all three FMCs indicates that the charge pump is in sleep mode.
If the value of FBPRDY.PUMPRDY in any of the FMCs is 1, then the charge pump is in
active mode. For more details, see the Flash register descriptions in
Section 13.15.
While the
pump is in sleep state, a charge pump sleep down counter holds a user configurable
value (PSLEEP bit field in the FPAC1 register). When the charge pump exits sleep
mode, the device waits for PSLEEP pre-scaled SYSCLK/CMCLK clock cycles (pre-scaled
clock is SYSCLK/2 for CPU1 and CPU2, and is CMCLK/2 for CM) before putting the
charge pump into active power mode. The configured PSLEEP value must result in a
minimum delay of 20 µs before the pump enters active mode. For more details, see the
Flash register descriptions in Section 13.15.
Following
are the cycle counts required for the bank and pump to wake up from low-power
modes.
- Pump sleep to active = PSLEEP
* (SYSCLK or CMCLK)/2 cycles
- Bank sleep to standby = 425
Flash clock cycles
- Bank standby to active = 90
Flash clock cycles
Where:
Flash clock = (SYSCLK or CMCLK)/(RWAIT+1)