SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The minimum PTP clock frequency depends on the time required between two consecutive SFD bytes and the time taken for synchronizing the time to the MII clock domain. This relationship is given in the following equation:
3 * PTP clock period + 4 * MII clock period <+ Minimum gap between two SFDs
The MII clock frequency is fixed by IEEE specification. Therefore, the minimum PTP clock frequency required for proper operation depends on the operating mode and operating speed of the MAC as shown in Table 43-12.
When IEEE 1588 timestamp feature is enabled with internal timestamp, use a PTP clock frequency that is greater than 5MHz. This is because the 8-bit MAC_Sub_Second_Increment register limits the minimum PTP frequency that can be used to approximately 4MHz.
| Mode | Minimum Gap Between Two SFDs | Minimum PTP Frequency with External Timestamp Input | Minimum PTP Frequency with Internal Timestamp |
|---|---|---|---|
| 10Mbps full duplex | 168 MII clocks | Approximately 45KHz | 5MHz |
| (128 clocks for a 64-byte packet + 24 clocks of IFG + 16 clocks of preamble) | |||
| 10Mbps half duplex | 48 MII clocks | 170KHz | 5MHz |
| (8 clocks for a JAM pattern sent just after SFD because of collision + 24 IFG + 16 preamble) | |||
| 100Mbps full duplex | 168 MII clocks | Approximately 0.5MHz | 5MHz |
| (128 clocks for a 64-byte packet + 24 clocks of minimum IFG + 16 clocks of preamble) | |||
| 100Mbps half duplex | 48 MII clocks | 4.55MHz | 5MHz |
| (8 clocks for a JAM pattern sent just after SFD because of collision + 24 IFG + 16 preamble) |