Note: The waveforms in this chapter show the behavior
of the ePWMs for a static compare register value. In a running system, the active
compare registers (CMPA and CMPB) are typically updated from the respective shadow
registers once every period. Specify when the update takes place: either when the
time-base counter reaches zero or when the time-base counter reaches the period.
There are some cases when the action based on the new value can be delayed by one
period or the action based on the old value can take effect for an extra period.
Some PWM configurations avoid this situation. These include, but are not limited to,
the following:
Use up-down
count mode to generate a symmetric PWM:
Use up-down count
mode to generate an asymmetric PWM:
- To achieve 50%-0%
asymmetric PWM use the following configuration: Load CMPA/CMPB on period
and use the period action to clear the PWM and a compare-up action to
set the PWM. Modulate the compare value from 0 to TBPRD to achieve
50%-0% PWM duty.
When using
up-count mode to generate an asymmetric PWM:
- To achieve 0-100%
asymmetric PWM, you must load CMPA/CMPB on TBPRD. When CMPA/CMPB
is not loaded on TBCTR=PRD, boundary conditions can occur depending on
the timing of the write and the value written to CMPA/CMPB. Use the Zero
action to set the PWM and a compare-up action to clear the PWM. Modulate
the compare value from 0 to TBPRD+1 to achieve 0-100% PWM duty.
When using
up-count mode to generate an asymmetric PWM with deadband enabled:
- To achieve 0%-100% PWM
use the following configuration: When the CMPA value is too close to 0
or PRD such that the following conditions are met (CMPX < Deadband)
or (CMPX > PRD – Deadband), the actions specified by the AQCTL
register for CMPX do not take effect. To avoid this, the AQCTL settings
must be altered under these conditions only to generate either high or
low pulses for both CAU or CAD events (both set or both clear). Make
sure that this software update is occurring synchronous to the PWM
carrier cycle, and shadow mode is enabled.
When using up-down
count mode to generate an asymmetric PWM with deadband enabled:
- To achieve 0%-100% PWM
use the following configuration: When the CMPA value is too close to 0
or PRD such that the following conditions are met (CMPX < Deadband/2)
or (CMPX > PRD – (Deadband)/2), the actions specified by the AQCTL
register for CMPX do not take effect. To avoid this, the AQCTL settings
must be altered under these conditions only to generate either high or
low pulses for both CAU or CAD events (both set or both clear). Make
sure that this software update is occurring synchronous to the PWM
carrier cycle, and shadow mode is enabled.
See Using
Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle
Control.
Figure 26-26 shows how a symmetric PWM waveform can be generated using the up-down-count mode
of the TBCTR. In this mode, 0%-100% DC modulation is achieved by using equal compare
matches on the up count and down count portions of the waveform. In the example
shown, CMPA is used to make the comparison. When the counter is incrementing, the
CMPA match pulls the PWM output high. Likewise when the counter is decrementing, the
compare match pulls the PWM signal low. When CMPA = 0, the PWM signal is high for
the entire period giving a 100% duty waveform. When CMPA = TBPRD, the PWM signal is
low achieving 0% duty.
When using this configuration in practice, if loading CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1. If loading CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1. This means there is always a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system.
The PWM waveforms in Figure 26-27 through Figure 26-32 show some common action-qualifier configurations. Some conventions used in the
figures and examples are as follows:
- TBPRD, CMPA, and CMPB refer to the value written
in the respective registers. The active register, not the shadow register, is
used by the hardware.
- CMPx, refers to either CMPA or CMPB.
- EPWMxA and EPWMxB refer to the output signals from ePWMx
- Up-Down means count-up-and count-down mode, Up
means up-count mode and Down means down-count mode
- Sym = Symmetric, Asym = Asymmetric
![F2838x Up, Single Edge
Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—Active
Low F2838x Up, Single Edge
Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—Active
Low](/ods/images/SPRUII0F/GUID-BC869BA7-48E4-4880-BC53-109CAEAF8EB4-low.gif)
A. PWM period = (TBPRD + 1) × TTBCLK
B. Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA).
C. Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
D. Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCTR wraps from period to 0000.
Figure 26-28 Up, Single Edge
Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—Active
Low![F2838x Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA F2838x Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA](/ods/images/SPRUII0F/GUID-C116A72C-BCF8-4D4E-8616-481B526BBB4F-low.gif)
A. PWM frequency = 1/((TBPRD + 1) × TTBCLK)
B. Pulse can be placed anywhere within the PWM cycle (0000 - TBPRD)
C. High time duty proportional to (CMPB - CMPA)
Figure 26-29 Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA
![F2838x Up-Down Count, Dual-Edge
Symmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB —
Complementary F2838x Up-Down Count, Dual-Edge
Symmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB —
Complementary](/ods/images/SPRUII0F/GUID-93908E5E-FD55-4E8D-9705-6C035118AFA2-low.gif)
A. PWM period = 2 × TBPRD × TTBCLK
B. Duty modulation for EPWMxA is set by CMPA, and is active low, that is, low time duty proportional to CMPA.
C. Duty modulation for EPWMxB is set by CMPB and is active high, that is, high time duty proportional to CMPB.
D. Outputs EPWMx can drive upper/lower (complementary) power switches.
E. Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module is also available if the more classical edge delay method is required.
Figure 26-31 Up-Down Count, Dual-Edge
Symmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB —
Complementary
![F2838x Up-Down Count, PWM Waveform Generation
Utilizing T1 and T2 Events F2838x Up-Down Count, PWM Waveform Generation
Utilizing T1 and T2 Events](/ods/images/SPRUII0F/GUID-626DB554-A6FD-43EA-AFFD-20C76A3E6152-low.gif)
A. PWM period = 2 × TBPRD × TTBCLK
B. Independent T1 event actions when counter is counting up and when the counter is counting down are used to generate EPWMxA output.
C. Independent T2 event actions when counter is counting up and when the counter is counting down are used to generate EPWMxB output.
D. TZ1 is selected as the source for T1.
E. TZ2 is selected as the source for T2.
Figure 26-33 Up-Down Count, PWM Waveform Generation
Utilizing T1 and T2 Events