SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

43.3.2.1.1.3 Ingress Correction

In the Receive side the timestamp captured at the internal snapshot point is delayed (later in time) as compared to the time at which that packet's SFD bit is received at the port's boundary. Therefore, the captured timestamp must be reduced by the ingress latency and the errors in CDC sampling. This correction value must be determined/calculated by the software and written into the MAC_Timestamp_Ingress_Corr_* registers.

The correction value consists of the following three components:

External latency in the PHY layer between boundary point and the input of the core. If the PHY is compliant to the IEEE 802.3 Clause 45 MMD registers, the PHY has a register indicating the maximum and minimum ingress latency. The software can read these registers and determine the average ingress latency in the PHY. Alternatively (if the PHY does not support these registers), the ingress latency must be determined from the data sheet or timing characteristics.
Internal latency from the input of the core to the internal capture point. The internal ingress latency can be read from the MAC_Ingress_Timestamp_Latency register. This is a read-only register and gives the latency in scaledNanoseconds format defined in IEEE 1588 Clause 5.3.2. The latency differs based on the active PHY interface (RMII, so on) and the operating speed. Therefore, the software must read this register after any speed change in the MAC to determine the current internal latency.
CDC Synchronization. The CDC synchronization error is almost equal to two times the clock-period of the PTP clock (clk_pt- p_ref_i).

The values determined from these three components must be added by the software and must be written into the TSIC and TSICSNS fields of the MAC_Timestamp_Ingress_Corr_* registers.

Note: The value written to the register must be negative (two's complement as explained below), because the value has to be subtracted from the captured timestamp. The MAC Receiver adds the value in this register to the captured timestamp and then gives the resultant value as the timestamp of the received packet.

When TSCTRLSSR bit in MAC_Timestamp_Control register is set, the nanoseconds field of the captured timestamp is in decimal format with a granularity of 1ns. So bit[31] of TSIC must be set to 1 (for negative value) and bits[30:0] must be written with "10⁹ - total ingress_correction_value[nanosecond part]" represented in binary. For example, if the required correction value is -5ns, then the value is 0xBB9A C9FB.

When TSCTRLSSR bit in MAC_Timestamp_Control register is reset, the nanoseconds field of the captured timestamp is in binary format with a granularity of approximately 0.466ns. Therefore, bits[30:0] must be written with "2³¹ - total ingress_correction_value" represented in binary with bit[31] = 1.