SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

43.4.3.2.4 RDES3 Normal Descriptor (Write-Back Format)

Table 43-69 RDES3 Normal Descriptor (Write-Back Format)

31	30	29	28	27	26	25	24	23	22	21	20	19	18:16	15	14:0
OWN	CTXT	FD	LD	RS2V	RS1V	RS0V	CE	GP	RWT	OE	RE	DE	LT	ES	PL

Table 43-70 RDES3 Normal Descriptor (Write-Back Format) Description

Bit	Name	Description
31	OWN	Own Bit
		When this bit is set, the bit indicates that the Ethernet module DMA owns the descriptor. When this bit is reset, the bit indicates that the application owns the descriptor. The DMA clears this bit when either of the following conditions is true:
		The DMA completes the packet reception.
		The buffers associated with the descriptor are full.
30	CTXT	Receive Context Descriptor
		When this bit is set, the bit indicates that the current descriptor is a context type descriptor. The DMA writes 0 to this bit for normal receive descriptor.
		When CTXT and FD bits are used together, {CTXT, FD}:
		00: Intermediate Descriptor
		01: First Descriptor
		10: Reserved
		11: Descriptor Error (due to all 1s)
		Note: When Descriptor Error occurs, the Receive DMA closes the receive descriptor indicating Descriptor Error. This receive descriptor is skipped and the buffer addresses are not used to write the packet data. The Receive DMA sets the CDE bit in DMA_CH#_Status register but not the RI bit even when IOC is set, as this is not marked as last receive descriptor for the packet. The subsequent valid receive descriptor is used to write the packet data.
29	FD	First Descriptor
		When this bit is set, the bit indicates that this descriptor contains the first buffer of the packet. If the size of the first buffer is 0, the second buffer contains the beginning of the packet. If the size of the second buffer is also 0, the next descriptor contains the beginning of the packet.
		See the CTXT bit description for details of using the CTXT bit and FD bit together.
28	LD	Last Descriptor
28	LD	When this bit is set, the bit indicates that the buffers to which this descriptor is pointing are the last buffers of the packet.
27	RS2V	Receive Status RDES2 Valid
27	RS2V	When this bit is set, the bit indicates that the status in RDES2 is valid and it is written by the DMA. This bit is valid only when the LD bit of RDES3 is set.
26	RS1V	Receive Status RDES1 Valid
26	RS1V	When this bit is set, the bit indicates that the status in RDES1 is valid and it is written by the DMA. This bit is valid only when the LD bit of RDES3 is set.
25	RS0V	Receive Status RDES0 Valid
25	RS0V	When this bit is set, the bit indicates that the status in RDES0 is valid and it is written by the DMA. This bit is valid only when the LD bit of RDES3 is set.
24	CE	CRC Error
24	CE	When this bit is set, the bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received packet. This field is valid only when the LD bit of RDES3 is set.
23	GP	Giant Packet
		When this bit is set, the bit indicates that the packet length exceeds the specified maximum Ethernet size of 1518, 1522, or 2000 bytes (9018 or 9022 bytes if jumbo packet enable is set).
		Note: Giant packet indicates only the packet length and does not cause any packet truncation.
22	RWT	Receive Watchdog Timeout
22	RWT	When this bit is set, the bit indicates that the Receive Watchdog Timer has expired while receiving the current packet. The current packet is truncated after watchdog timeout.
21	OE	Overflow Error
		When this bit is set, the bit indicates that the received packet is damaged because of buffer overflow in Rx FIFO.
		Note: This bit is set only when the DMA transfers a partial packet to the application. This happens only when the Rx FIFO is operating in the threshold mode. In the store-and-forward mode, all partial packets are dropped completely in Rx FIFO.
20	RE	Receive Error
20	RE	When this bit is set, the bit indicates that the gmii_rxer_i signal is asserted while the gmii_rxdv_i signal is asserted during packet reception. This error also includes carrier extension error in the MII and half-duplex mode. Error can be of less or no extension, or error (rxd!= 0f) during extension.
19	DE	Dribble Bit Error
19	DE	When this bit is set, the bit indicates that the received packet has a non-integer multiple of bytes (odd nibbles). This bit is valid only in the MII Mode.
18-16	LT	Length/Type Field
		This field indicates if the packet received is a length packet or a type packet. The encoding of the 3 bits is:
		000: The packet is a length packet
		001: The packet is a type packet
		010: Reserved
		011: The packet is a ARP Request packet type
		100: The packet is a type packet with VLAN Tag
		101: The packet is a type packet with Double VLAN Tag
		110: The packet is a MAC Control packet type
		111: The packet is a OAM packet type
15	ES	Error Summary
		When this bit is set, the bit indicates the logical OR of the following bits:
		RDES3[24]: CRC Error
		RDES3[19]: Dribble Error
		RDES3[20]: Receive Error
		RDES3[22]: Watchdog Timeout
		RDES3[21]: Overflow Error
		RDES3[23]: Giant Packet
		RDES2[17]: Destination Address Filter Fail, when Flexible RX Parser is enabled
		RDES2[16]: SA Address Filter Fail, when Flexible RX Parser is enabled
		This field is valid only when the LD bit of RDES3 is set.
14-0	PL	Packet Length
		These bits indicate the byte length of the received packet that was transferred to system memory (including CRC).
		This field is valid when the LD bit of RDES3 is set and Overflow Error bits are reset. The packet length also includes the two bytes appended to the Ethernet packet when IP checksum calculation is enabled and the received packet is not a MAC control packet.
		This field is valid when the LD bit of RDES3 is set. When the Last Descriptor and Error Summary bits are not set, this field indicates the accumulated number of bytes that have been transferred for the current packet.