SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

12.2.5.1 SDRAM Commands

The EMIF controller supports the SDRAM commands described in Table 12-5. Table 12-6 shows the truth table for the SDRAM commands, and an example timing waveform of the PRE command is shown in Figure 12-3. EM1A[10] is pulled low in this example to deactivate only the bank specified by the EM1BA pins.

Table 12-5 EMIF SDRAM Commands

Command	Function
PRE	Precharge. Depending on the value of EM1A[10], the PRE command either deactivates the open row in all banks (EM1A[10] = 1) or only the bank specified by the EM1BA[1:0] pins (EM1A[10] = 0).
ACTV	Activate. The ACTV command activates the selected row in a particular bank for the current access.
READ	Read. The READ command outputs the starting column address and signals the SDRAM to begin the burst read operation. Address EM1A[10] is always pulled low to avoid auto precharge. This allows for better bank interleaving performance.
WRT	Write. The WRT command outputs the starting column address and signals the SDRAM to begin the burst write operation. Address EM1A[10] is always pulled low to avoid auto precharge. This allows for better bank interleaving performance.
BT	Burst terminate. The BT command is used to truncate the current read or write burst request. On this device, all the SDRAM accesses are single access except when EMIF controller splits a single access into multiple access (for example, a 32-bit access from CPU is split into two 16-bit accesses if external SDRAM device is 16 bit (NM =1).
LMR	Load mode register. The LMR command sets the mode register of the attached SDRAM devices and is only issued during the SDRAM initialization sequence described in Section 12.2.5.4.
REFR	Auto refresh. The REFR command signals the SDRAM to perform an auto refresh according to the internal address.
SLFR	Self refresh. The self-refresh command places the SDRAM into self-refresh mode, during which the SDRAM provides a clock signal and auto refresh cycles.
NOP	No operation. The NOP command is issued during all cycles in which one of the above commands is not issued.

Table 12-6 Truth Table for SDRAM Commands

SDRAM Pins:	CKE	nCS	nRAS	nCAS	nWE	BA[1:0]	A[12:11]	A[10]	A[9:0]
EMIF Pins:	EM1SDCKE	EM1CS[0]	EM1RAS	EM1CAS	EM1WE	EM1BA[1:0]	EM1A[12:11]	EM1A[10]	EM1A[9:0]
PRE	H	L	L	H	L	Bank/X	X	L/H	X
ACTV	H	L	L	H	H	Bank	Row	Row	Row
READ	H	L	H	L	H	Bank	Column	L	Column
WRT	H	L	H	L	L	Bank	Column	L	Column
BT	H	L	H	H	L	X	X	X	X
LMR	H	L	L	L	L	X	Mode	Mode	Mode
REFR	H	L	L	L	H	X	X	X	X
SLFR	L	L	L	L	H	X	X	X	X
NOP	H	L	H	H	H	X	X	X	X

F2838x Timing Waveform of SDRAM PRE Command

Figure 12-3 Timing Waveform of SDRAM PRE Command