The serial port initialization
procedure is as follows:
- Make XRST = RRST = GRST = 0 in
SPCR[1,2]. If coming out of a device reset, this step is not required.
- While the serial port is in the
reset state, program only the McBSP configuration registers (not the data
registers) as required.
- Wait for two clock cycles. This
makes sure of proper internal synchronization.
- Set up data acquisition as
required (such as writing to DXR[1,2]).
- Make XRST = RRST = 1 to enable
the serial port. Make sure that as you set these reset bits, you do not modify
any of the other bits in SPCR1 and SPCR2. Otherwise, you change the
configuration you selected in step 2.
- Set FRST = 1, if internally
generated frame synchronization is required.
- Wait two clock cycles for the
receiver and transmitter to become active.
Alternatively, on either write (step 1
or 5), the transmitter and receiver can be placed in or taken out of reset
individually by modifying the desired bit.
The previous procedure for
reset/initialization can be applied in general when the receiver or transmitter must
be reset during normal operation and when the sample rate generator is not used for
either operation.
Note:
- The necessary duration of the
active-low period of XRST or RRST is at least two MCLKR/CLKX cycles.
- The appropriate bits in
serial port configuration registers SPCR[1,2], PCR, RCR[1,2], XCR[1,2], and
SRGR[1,2] must only be modified when the affected portion of the serial port
is in the reset state.
- In most cases, the data
transmit registers (DXR[1,2]) must be loaded by the CPU or by the DMA
controller only when the transmitter is enabled (XRST = 1). An exception to
this rule is when these registers are used for companding internal data (see
Section 34.3.2.2).
- The bits of the channel
control registers—MCR[1,2], RCER[A-H], XCER[A-H]—can be modified at any time
as long as the bits are not being used by the current reception/transmission
in a multichannel selection mode.