SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

43.3.2.2.3 System Time Register Module

The system time generator module is an optional module and is not available if external time updating is enabled. The 80-bit time is maintained in this module and updated using the input reference clock (clk_ptp_ref_i). This time is the source for taking snapshots (timestamps) of Ethernet packets being transmitted or received at the MII interface.

The system time counter can be initialized or corrected using the coarse correction method. In this method, the initial value or the offset value is written to the Timestamp Update register. For initialization, the system time counter is written with the value in the Timestamp Update register. For system time correction, the offset value is added to or subtracted from the system time.

In the fine correction method, the frequency offset and/or frequency drift of a slave clock (clk_ptp_ref_i) with respect to the master clock (as defined in IEEE 1588-2002) is corrected over a period of time instead of in one clock, as in coarse correction. This helps maintain linear time and does not introduce drastic changes (or a large jitter) in the reference time between PTP Sync message intervals. In this method, an accumulator sums up the contents of the Addend register, as shown in Figure 43-12. The arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter. The accumulator and the addend are 32-bit registers. The accumulator acts as a high-precision frequency multiplier or divider.

Note: You must connect a PTP clock with a frequency higher than the frequency required for the specified accuracy.

This algorithm is shown in Figure 43-12.

The system time update logic requires a 50MHz clock frequency to achieve 20ns accuracy. The frequency division is the ratio of the reference clock frequency to the required clock frequency. For example, if the reference clock (clk_ptp_ref_i) is 66MHz, this ratio is calculated as 66MHz/50MHz = 1.32. Therefore, the default addend value to be set in the register is 2³²/ 1.32, 0xC1F0 7C1F.

If the reference clock drifts lower, for example, to 65MHz, the ratio is 65/50, or 1.3 and the value to set in the addend register is 2³² / 1.30, or 0xC4EC 4EC4. If the clock drifts higher, for example, to 67MHz, the addend register must be set to 0xBF0B 7672. When the clock drift is nil, the default addend value of 0xC1F0 7C1F (2³² / 1.32) must be programmed.

F2838x System Time Update Using Fine Method

Figure 43-12 System Time Update Using Fine Method

In Figure 43-12, the constant value used to accumulate the sub-second register is decimal 43, which achieves an accuracy of 20ns in the system time (in other words, incremented in 20ns steps). When External Time Update is enabled, the optional System Time module is not available.

The software must calculate the drift in frequency based on the Sync messages and accordingly update the Addend register.

Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This value is:

FreqCompensationValue0 = 2³² / FreqDivisionRatio

The algorithm is:

At time MasterSyncTime_n, the master sends the slave clock a Sync message. The slave receives this message when the local clock is SlaveClockTime_n and computes MasterClockTime_n as MasterClockTime_n = MasterSyncTime_n + MasterToSlaveDelay_n
The master clock count for current Sync cycle, MasterClockCount_n, is MasterClockCount_n = MasterClockTime_n – MasterClockTime_n – 1 (assuming that MasterToSlaveDelay is the same for Sync cycles n and n – 1)
The slave clock count for current Sync cycle, SlaveClockCount_n, is SlaveClockCount_n = SlaveClockTime_n – SlaveClockTime_n – 1
The difference between master and slave clock counts for current Sync cycle, ClockDiffCount_n, is ClockDiffCount_n = MasterClockTime_n – SlaveClockTime_n
The frequency-scaling factor for slave clock, FreqScaleFactor_n, is FreqScaleFactor_n = (MasterClockCount_n + ClockDiffCount_n) / SlaveClockCount_n
The frequency compensation value for Addend register, FreqCompensationValue_n, is FreqCompensationValue_n = FreqScaleFactor_n * FreqCompensationValue_n – 1

Note: Modes of Internal Reference time can be set through the TSCTRLSSR bit in the MAC_Timestamp_Control register.