SPRUII0 User guide

SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

31.2.6.2 Clocking

Two functional clock inputs are defined for the ESC: CLK25 (25MHz) and CLK100 (100MHz).

EtherCAT functional clock inputs CLK25 and CLK100 are sourced by the MCU clocking module either using SYSPLL or AUXPLL. At the SoC level, you have multiple options to choose from regarding what inputs are used for the SYSPLL or AUXPLL.

Due to the 25ppm requirement for EtherCAT, an external oscillator of 25MHz is suggested to be used as the main clock source.
A less accurate clock than 25ppm limits the ability of the ESC to act as the network reference clock. For practical reasons, clock accuracy must be the same or better than the Ethernet clock source that is 50ppm.

Note:

CLK25 and CLK100 are used for the ESC core operation. These two clocks and the clocks to the PHY must have a common source, which establishes a deterministic phase relationship between PHY clocks and ESC clocks.
In MII mode, 25MHz RX clock is sourced by the PHY while the TX clock from PHY is optional (which effectively saves a pin). The phase differential between the PHY TX clock and CLK25 can be compensated to the TX data and TX EN using the manual compensation mode in increments of 10ns.

Figure 31-10 shows the clocks connectivity. Refer to the System Control and Interrupts chapter for additional details of the PLL source selections and clock dividers.

Figure 31-10 Clocking of ESC

In the case of a low-accuracy clock (up to 100ppm) being used, a clock accuracy of 25ppm cannot be feasible, then the following restrictions apply:

RX FIFO size cannot be reduced lower than 7 (default for 100ppm), which in turn affects the latency of the transfer as the transfer starts after half of the FIFO full threshold, thus resulting in a RX Delay.
This ECS cannot be used as the first slave from the master in the network, as typically the first slave from the master is treated as the reference clock for the distributed clocks functionality.
The number of iterations required for synchronizing clocks (specially the drift computation) increases.