SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

6.4.14.11 PRU_MII_RT_MII_RT Registers

Table 6-1328 lists the memory-mapped registers for the PRU_MII_RT_MII_RT registers. All register offset addresses not listed in Table 6-1328 should be considered as reserved locations and the register contents should not be modified.

Table 6-1327 PRU_MII_RT_MII_RT Instances

Instance	Base Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2000h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2000h

Table 6-1328 PRU_MII_RT_MII_RT Registers

Offset	Acronym	Register Name	PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG Physical Address	PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG Physical Address
0h	MII_RT_RXCFG0	RX Configuration 0 Register	3003 2000h	300B 2000h
4h	MII_RT_RXCFG1	RX Configuration 1 Register	3003 2004h	300B 2004h
10h	MII_RT_TXCFG0	TX Control Register 0	3003 2010h	300B 2010h
14h	MII_RT_TXCFG1	TX Control Register 1	3003 2014h	300B 2014h
20h	MII_RT_TX_CRC0	Transmit CRC32 Register 0	3003 2020h	300B 2020h
24h	MII_RT_TX_CRC1	Transmit CRC32 Register 1	3003 2024h	300B 2024h
30h	MII_RT_TX_IPG0	TX IPG Register 0	3003 2030h	300B 2030h
34h	MII_RT_TX_IPG1	TX IPG Register 1	3003 2034h	300B 2034h
38h	MII_RT_PRS0	PORT_RAW_STATUS Register 0	3003 2038h	300B 2038h
3Ch	MII_RT_PRS1	PORT_RAW_STATUS Register 1	3003 203Ch	300B 203Ch
40h	MII_RT_RX_FRMS0	RX Frame Size Register 0	3003 2040h	300B 2040h
44h	MII_RT_RX_FRMS1	RX Frame Size Register 1	3003 2044h	300B 2044h
48h	MII_RT_RX_PCNT0	RX Preamble Cnt Register 0	3003 2048h	300B 2048h
4Ch	MII_RT_RX_PCNT1	RX Preamble Cnt Register 1	3003 204Ch	300B 204Ch
50h	MII_RT_RX_ERR0	RX Error Register 0	3003 2050h	300B 2050h
54h	MII_RT_RX_ERR1	RX Error Register 1	3003 2054h	300B 2054h
60h	MII_RT_RX_FIFO_LEVEL0	RX FIFO Level 0 Register	3003 2060h	300B 2060h
64h	MII_RT_RX_FIFO_LEVEL1	RX FIFO Level 1 Register	3003 2064h	300B 2064h
68h	MII_RT_TX_FIFO_LEVEL0	TX FIFO Register 0	3003 2068h	300B 2068h
6Ch	MII_RT_TX_FIFO_LEVEL1	TX FIFO Register 1	3003 206Ch	300B 206Ch

4.14.11.1 MII_RT_RXCFG0 Register (Offset = 0h) [reset = X]

MII_RT_RXCFG0 is shown in Figure 6-670 and described in Table 6-1330.

Return to Summary Table.

RX Configuration 0 Register. This register contains the configuration variables for the RX path. MII_RT_RXCFG0 is attached to PRU0 core and controls which RX port is attached to PRU0.

Table 6-1329 MII_RT_RXCFG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2000h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2000h

Figure 6-670 MII_RT_RXCFG0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED						RX_EOF_SCLR_DIS0	RX_ERR_RAW0
R-0h						R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RX_SFD_RAW0	RX_AUTO_FWD_PRE0	RX_BYTE_SWAP0	RX_L2_EN0	RX_MUX_SEL0	RX_CUT_PREAMBLE0	RX_DATA_RDY_MODE_DIS0	RX_ENABLE0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1330 MII_RT_RXCFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h
9	RX_EOF_SCLR_DIS0	R/W	0h	0h = RX_EOF flag in R31 and RXL2 is selfcleared by HW when RX2L is enabled 1h = RX_EOF flag in R31 and RXL2 is not selfcleared by HW when RX2L is enabled. A RX_EOF_CLR must get issued
8	RX_ERR_RAW0	R/W	0h	0h = ERR Raw Mode Disabled RX_ERR qualified with RX_DV RX_DV must be 1 before RX_ERR action/event is generated 1h = ERR Raw Mode Enabled RX_ERR is not qualified with RX_DV RX_ERR action/event is generated , even if RX_DV = 0
7	RX_SFD_RAW0	R/W	0h	0h = SFD Raw Mode Disabled RX_SFD requires a pattern of 5D 1h = SFD Raw Mode Enable The first byte of any pattern after RX_DV assertion will trigger RX_SFD event. The first nibble of the frame(RX_DV = 1) will be in the RX FIFO
6	RX_AUTO_FWD_PRE0	R/W	0h	Auto Forward Preamble Mode 0h = Disable 1h = Enable If Enabled, RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE must be disabled This will forward the preamble nibbles including the SFD to the TX FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is DA Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes
5	RX_BYTE_SWAP0	R/W	0h	Controls the order of the Byte0/1 placement for RX R31 and RX L2. 0h = Byte1 is the high byte for R31 and RX L2 MSB {Byte1:Byte0} LSB RX R31 15:8 = Byte1 RX R31 7:0 = Byte0 1h = Byte1 is the low byte for R31 and RX L2 MSB {Byte0:Byte1} LSB RX R31 15:8 = Byte0 RX R31 7:0 = Byte1 Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order Note this cannot get enabled if TX_AUTO_SEQUENCE enabled since TX_BYTE_SWAP on swaps the PRU output.
4	RX_L2_EN0	R/W	0h	0h = Disables RX L2 buffer. Can be used as generic scratch pad. 1h = Enables RX L2 buffer
3	RX_MUX_SEL0	R/W	0h	0h = Select MII RX Data from Port 0 1h = Select MII RX Data from Port 1 The encoding is identical for both MII Ports and PRUs. Typically, the setting for this will not be identical for the two MII Receive Configuration registers.
2	RX_CUT_PREAMBLE0	R/W	0h	0h = All data from Ethernet PHY are passed on to PRU register. This assume Ethernet PHY which does not shorten the preamble 1h = MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA
1	RX_DATA_RDY_MODE_DIS0	R/W	0h	0h = R31:16 is DATA_RDY mapped 1h = R31:16 is TX_EOF mapped
0	RX_ENABLE0	R/W	0h	This enables RX traffic which is currently selected by RX_MUX_SELECT

4.14.11.2 MII_RT_RXCFG1 Register (Offset = 4h) [reset = X]

MII_RT_RXCFG1 is shown in Figure 6-671 and described in Table 6-1332.

Return to Summary Table.

RX Configuration 1 Register. This register contains the configuration variables for the RX path. MII_RT_RXCFG1 is attached to PRU1 core and controls which RX port is attached to PRU1.

Table 6-1331 MII_RT_RXCFG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2004h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2004h

Figure 6-671 MII_RT_RXCFG1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED						RX_EOF_SCLR_DIS1	RX_ERR_RAW1
R-0h						R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RX_SFD_RAW1	RX_AUTO_FWD_PRE1	RX_BYTE_SWAP1	RX_L2_EN1	RX_MUX_SEL1	RX_CUT_PREAMBLE1	RX_DATA_RDY_MODE_DIS1	RX_ENABLE1
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1332 MII_RT_RXCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h
9	RX_EOF_SCLR_DIS1	R/W	0h	0h = RX_EOF flag in R31 and RXL2 is self cleared by HW when RX2L is enabled 1h = RX_EOF flag in R31 and RXL2 is not self cleared by HW when RX2L is enabled. A RX_EOF_CLR must get issued
8	RX_ERR_RAW1	R/W	0h	0h = ERR Raw Mode Disabled RX_ERR qualified with RX_DV RX_DV must be 1 before RX_ERR action/event is generated 1h = ERR Raw Mode Enabled RX_ERR is not qualified with RX_DV RX_ERR action/event is generated , even if RX_DV = 0
7	RX_SFD_RAW1	R/W	0h	0h = SFD Raw Mode Disabled RX_SFD requires a pattern of 5D 1h = SFD Raw Mode Enable The first byte of any pattern after RX_DV assertion will trigger RX_SFD event. The first nibble of the frame(RX_DV = 1) will be in the RX FIFO
6	RX_AUTO_FWD_PRE1	R/W	0h	Auto Forward Preamble Mode 0h = Disable 1h = Enable If Enabled, RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE must be disabled This will forward the preamble nibbles including the SFD to the TX FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is DA Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes
5	RX_BYTE_SWAP1	R/W	0h	Controls the order of the Byte0/1 placement for RX R31 and RX L2. 0h = Byte1 is the high byte for R31 and RX L2 MSB {Byte1:Byte0} LSB RX R31 15:8 = Byte1 RX R31 7:0 = Byte0 1h = Byte1 is the low byte for R31 and RX L2 MSB {Byte0:Byte1} LSB RX R31 15:8 = Byte0 RX R31 7:0 = Byte1 Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order Note this cannot get enabled if TX_AUTO_SEQUENCE enabled since TX_BYTE_SWAP on swaps the PRU output.
4	RX_L2_EN1	R/W	0h	0h = Disables RX L2 buffer. Can be used as generic scratch pad. 1h = Enables RX L2 buffer
3	RX_MUX_SEL1	R/W	1h	0h = Select MII RX Data from Port 0 1h = Select MII RX Data from Port 1 The encoding is identical for both MII Ports and PRUs. Typically, the setting for this will not be identical for the two MII Receive Configuration registers.
2	RX_CUT_PREAMBLE1	R/W	0h	0h = All data from Ethernet PHY are passed on to PRU register. This assume Ethernet PHY which does not shorten the preamble 1h = MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA
1	RX_DATA_RDY_MODE_DIS1	R/W	0h	0h = R31:16 is DATA_RDY mapped 1h = R31:16 is TX_EOF mapped
0	RX_ENABLE1	R/W	0h	This enables RX traffic which is currently selected by RX_MUX_SELECT

4.14.11.3 MII_RT_TXCFG0 Register (Offset = 10h) [reset = X]

MII_RT_TXCFG0 is shown in Figure 6-672 and described in Table 6-1334.

Return to Summary Table.

TX Control Register 0. This register contains the control information for the transmit path on one of the MII interfaces. MII_RT_TXCFG0 is attached to Port TX0 and controls which PRU core is selected for TX0.

Table 6-1333 MII_RT_TXCFG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2010h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2010h

Figure 6-672 MII_RT_TXCFG0 Register

31	30	29	28	27	26	25	24
RESERVED	TX_CLK_DELAY0			RESERVED		TX_START_DELAY0
R-0h	R/W-0h			R-0h		R/W-40h

23	22	21	20	19	18	17	16
TX_START_DELAY0
R/W-40h

15	14	13	12	11	10	9	8
RESERVED			TX_IPG_WIRE_CLK_EN	TX_32_MODE_EN0	PRE_TX_AUTO_ESC_ERR0	PRE_TX_AUTO_SEQUENCE0	TX_MUX_SEL0
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-1h

7	6	5	4	3	2	1	0
RESERVED				TX_BYTE_SWAP0	TX_EN_MODE0	TX_AUTO_PREAMBLE0	TX_ENABLE0
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1334 MII_RT_TXCFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h
30-28	TX_CLK_DELAY0	R/W	0h	Number of MII_RT clock cycles to wait before launching data on the MII interface. This can be tweaked to meet setup/hold time requirements on the MII TXCLK. The range is one to seven cycles after the MII Transmit edge has been synchronized to MII_RT clock domain. For example TX_CLK_DELAY Delay (ns) 0h = (10-15) + SoC delay 1h = (15-20) + SoC delay <n> (<n>*5 +10/+15) + SoC delay Note that the switch event can get pushed into the next TXCLK cycle.
27-26	RESERVED	R	0h
25-16	TX_START_DELAY0	R/W	40h	The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame. This is programmed in number of MII_RT clock cycles. Default should be to have 320ns of delay which is optimized for min latency at 16 bit processing. Counter is started with RXDV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. Uses core_clk Note: it will not start until the TX FIFO is not empty. This delay only defines the minimum delay. If the TX FIFO has data when the delay expires, then TX will start sending data. If the TX FIFO is empty, it will not start until it is not empty. If TX_AUTO_PREAMBLE is enabled, TX FIFO will not get preamble until the first wrt occurs. Note: the TX FIFO size is 64Bytes. It is possible to overflow the TX FIFO with the max delay setting when auto forwarding is enabled since the time delay is larger than the amount of data it needs to store. If TX OVERFLOW occurs, then SW will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64Byte times, but you need to allow delays for synchronization. Due to this fact; a MAX delay should be 80ns less when auto forwarding is enabled. 0x3F0 is the max in this configuration This register is also used in RGMII mode. For 1 Gbit rate the RGMII_CLK used is 250 MHz and the values in TX_START_DELAY0/1 register is multiplied by 4 ns. At 1 Gbit rate there is a min setting of 0xf which means 60 ns. The measured RGMII to RGMII delay is 160 ns with this settings. Additional delay comes from L0 FIFOs.
15-13	RESERVED	R	0h
12	TX_IPG_WIRE_CLK_EN	R/W	0h	0h = Use ICSSGn_CORE_CLK (where n = 0 to 1) core clock for the TX_IPG counter 1h = Use the TX interface clock for the TX_IPG counter Note: Using TX interface clock the user should see zero jitter as long as the data is ready to transmit.MUST BE SET THE SAME FOR BOTH PORTS
11	TX_32_MODE_EN0	R/W	0h	0h = Disable 32-bit Data Push mode 1h = Enabled 32-bit, 16-bit, and 8-bit Data Push mode with TX_MASK disabled In this mode, the internal PRU R30 byte write strobes are used and NOT the R31 CMD TX_PUSH Any update to R30 will trigger an TX PUSH See TX_PUSH Table
10	PRE_TX_AUTO_ESC_ERR0	R/W	0h	This bit enables the HW actions required to implement the ESC Error handing table.
9	PRE_TX_AUTO_SEQUENCE0	R/W	0h	When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter. The transmit data source is determined by TX_MUX_SEL setting. When this bit is set, the masking logic that allows for a Boolean combination of PRU or MII data to be transmitted is disabled and only the MII data is used.
8	TX_MUX_SEL0	R/W	1h	0h = TX data from PRU0 is selected 1h = TX data from PRU1 is selected The default/reset setting for TX Port 0 is 1h. This setting permits MII TX Port 0 to receive data from PRU1 and the MII RX Port 1 which is connected to PRU1 by default. For MII TX Port 1, the default is zero which allows it to receive data from PRU0 and MII0 that is connected to PRU0 by default.
7-4	RESERVED	R	0h
3	TX_BYTE_SWAP0	R/W	0h	Controls the order of the Byte0/1 placement for TX R30. 0h = Byte1 is the high byte for R30 MSB {Byte1:Byte0} LSB TX R30 15:8 = Byte1 TX R30 7:0 = Byte0 TX R30 31:24 = TX_MASK[15:8] TX R30 23:16 = TX_MASK[7:0] 1h = Byte1 is the low byte for R30 MSB {Byte0:Byte1} LSB TX R30 15:8 = Byte0 TX R30 7:0 = Byte1 TX R30 31:24 = TX_MASK[7:0] TX R30 23:16 = TX_MASK[15:8] Must be selected/updated when the port is disabled or no traffic It only effects R30 pulling order
2	TX_EN_MODE0	R/W	0h	0h = Disables TX_ENABLE self clear for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1 1h = Enables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1 Note when enabled, iep_cmp[3] must be set before the TX will start for TX0, and iep_cmp[4] for TX1 This is just a new dependency to start transmission to the current set of dependencies, which are FIFO NOT empty and TX_START_DELAY met.
1	TX_AUTO_PREAMBLE0	R/W	0h	0h = PRU will provide full pre-amble 1h = TX FIFO will insert pre-amble automatically Note that the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency.
0	TX_ENABLE0	R/W	0h	0h = TX PORT is disabled/stopped immediately 1h = TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired When read value is zero, TX is disabled When read value is one, TX is enabled If TX_EN_MODE is set then TX_ENABLE will self clear during a TX_EOF event Note: SW can use this to pre-fill the TX FIFO and then start the TX Frame during none ECS operations.

4.14.11.4 MII_RT_TXCFG1 Register (Offset = 14h) [reset = X]

MII_RT_TXCFG1 is shown in Figure 6-673 and described in Table 6-1336.

Return to Summary Table.

TX Control Register 1. This register contains the control information for the transmit path on one of the MII interfaces. MII_RT_TXCFG1 is attached to Port TX1 and controls which PRU core is selected for TX1.

Table 6-1335 MII_RT_TXCFG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2014h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2014h

Figure 6-673 MII_RT_TXCFG1 Register

31	30	29	28	27	26	25	24
RESERVED	TX_CLK_DELAY1			RESERVED		TX_START_DELAY1
R-0h	R/W-0h			R-0h		R/W-40h

23	22	21	20	19	18	17	16
TX_START_DELAY1
R/W-40h

15	14	13	12	11	10	9	8
RESERVED			TX_IPG_WIRE_CLK_EN	TX_32_MODE_EN1	PRE_TX_AUTO_ESC_ERR1	PRE_TX_AUTO_SEQUENCE1	TX_MUX_SEL1
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED				TX_BYTE_SWAP1	TX_EN_MODE1	TX_AUTO_PREAMBLE1	TX_ENABLE1
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1336 MII_RT_TXCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h
30-28	TX_CLK_DELAY1	R/W	0h	Number of MII_RT clock cycles to wait before launching data on the MII interface. This can be tweaked to meet setup/hold time requirements on the MII TXCLK. The range is one to seven cycles after the MII Transmit edge has been synchronized to MII_RT clock domain. For example TX_CLK_DELAY Delay (ns) 0h = (10-15) + SOC delay 1h = (15-20) + SOC delay <n> (<n>*5 +10/+15) + SOC delay Note that the switch event can get pushed into the next TXCLK cycle. Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz or 250 MHz and the TX_CLK_DELAY0 bit field in the MII_RT_TXCFG0 register must be set to 0h (default value).
27-26	RESERVED	R	0h
25-16	TX_START_DELAY1	R/W	40h	The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame. This is programmed in number of MII_RT clock cycles. Default should be to have 320 ns of delay which is optimized for min latency at 16 bit processing. Counter is started with RXDV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. Uses core_clk Note it will not start until the TX FIFO is not empty. This delay only defines the minimum delay. If the TX FIFO has data when the delay expires, then TX will start sending data. If the TX FIFO is empty, it will not start until it is not empty. If TX_AUTO_PREAMBLE is enabled, TX FIFO will not get preamble until the first wrt occurs. Note the TX FIFO size is 64 Bytes. It is possible to overflow the TX FIFO with the max delay setting when auto forwarding is enabled since the time delay is larger than the amount of data it needs to store. If TX OVERFLOW occurs, then SW will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64 Byte times, but you need to allow delays for synchronization. Do to this fact; a MAX delay should be 80 ns less when auto forwarding is enabled. 0x3F0 is the max in this configuration This register is also used in RGMII mode. For 1 Gbit rate the RGMII_CLK used is 250 MHz and the values in TX_START_DELAY0/1 register is multiplied by 4 ns. At 1 Gbit rate there is a min setting of 0xf which means 60 ns. The measured RGMII to RGMII delay is 160 ns with this settings. Additional delay comes from L0 FIFOs.
15-13	RESERVED	R	0h
12	TX_IPG_WIRE_CLK_EN	R/W	0h	0h = Use ICSSGn_CORE_CLK (where n = 0 to 1) core clock for the TX_IPG counter 1h = Use the TX interface clock for the TX_IPG counter Note: Using TX interface clock the user should see zero jitter as long as the data is ready to transmit.MUST BE SET THE SAME FOR BOTH PORTS
11	TX_32_MODE_EN1	R/W	0h	0h = Disable 32-bit Data Push mode 1h = Enabled 32-bit, 16-bit, and 8 Data Push mode with TX_MASK disabled In this mode, the internal PRU R30 byte write strobes are used and NOT the R31 CMD TX_PUSH Any update to R30 will trigger an TX PUSH See TX_PUSH Table
10	PRE_TX_AUTO_ESC_ERR1	R/W	0h	This bit enables the HW actions required to implement the ESC Error handing table.
9	PRE_TX_AUTO_SEQUENCE1	R/W	0h	When set to one, it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter. The transmit data source is determined by TX_MUX_SEL setting. When this bit is set, the masking logic that allows for a Boolean combination of PRU or MII data to be transmitted is disabled and only the MII data is used.
8	TX_MUX_SEL1	R/W	0h	0h = TX data from PRU0 is selected 1h = TX data from PRU1 is selected The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII RX Port 1 which is connected to PRU1 by default. For MII TX Port 1, the default is zero which allows it to receive data from PRU0 and MII0 that is connected to PRU0 by default.
7-4	RESERVED	R	0h
3	TX_BYTE_SWAP1	R/W	0h	Controls the order of the Byte0/1 placement for TX R30. 0h = Byte1 is the high byte for R30 MSB {Byte1:Byte0} LSB TX R30 15:8 = Byte1 TX R30 7:0 = Byte0 TX R30 31:24 = TX_MASK[15:8] TX R30 23:16 = TX_MASK[7:0] 1h = Byte1 is the low byte for R30 MSB {Byte0:Byte1} LSB TX R30 15:8 = Byte0 TX R30 7:0 = Byte1 TX R30 31:24 = TX_MASK[7:0] TX R30 23:16 = TX_MASK[15:8] Must be selected /updated when the port is disabled or no traffic It only effects R30 pulling order
2	TX_EN_MODE1	R/W	0h	0h = Disables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1 1h = Enables TX_ENABLE self clr for a TX_EOF event iep_cmp[3] for TX0 and iep_cmp[4] for TX1 Note when enabled, iep_cmp[3] must be set before the TX will start for TX0, and iep_cmp[4] for TX1 This is just a new dependency to start transmission to the current set of dependencies, which are FIFO NOT empty and TX_START_DELAY met.
1	TX_AUTO_PREAMBLE1	R/W	0h	0h = PRU will provide full pre-amble 1h = TX FIFO will insert pre-amble automatically Note that the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency.
0	TX_ENABLE1	R/W	0h	0h = TX PORT is disabled/stopped immediately 1h = TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired When read value is zero, TX is disabled When read value is one, TX is enabled If TX_EN_MODE is set then TX_ENABLE will self clear during a TX_EOF event Note SW can use this to pre-fill the TX FIFO and then start the TX Frame during none ECS operations.

4.14.11.5 MII_RT_TX_CRC0 Register (Offset = 20h) [reset = 0h]

MII_RT_TX_CRC0 is shown in Figure 6-674 and described in Table 6-1338.

Return to Summary Table.

Transmit CRC32 Register 0. It contains CRC which PRU core can read.

Table 6-1337 MII_RT_TX_CRC0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2020h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2020h

Figure 6-674 MII_RT_TX_CRC0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TX_CRC0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1338 MII_RT_TX_CRC0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TX_CRC0	R	0h	FCS (CRC32) data can be read by PRU core for diagnostics It is only valid after 6 clocks after a TX_CRC_HIGH command is given.

4.14.11.6 MII_RT_TX_CRC1 Register (Offset = 24h) [reset = 0h]

MII_RT_TX_CRC1 is shown in Figure 6-675 and described in Table 6-1340.

Return to Summary Table.

Transmit CRC32 Register 1. It contains CRC which PRU core can read.

Table 6-1339 MII_RT_TX_CRC1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2024h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2024h

Figure 6-675 MII_RT_TX_CRC1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TX_CRC1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1340 MII_RT_TX_CRC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TX_CRC1	R	0h	FCS (CRC32) data can be read by PRU for diagnostics It is only valid after 6 clocks after a TX_CRC_HIGH command is given.

4.14.11.7 MII_RT_TX_IPG0 Register (Offset = 30h) [reset = X]

MII_RT_TX_IPG0 is shown in Figure 6-676 and described in Table 6-1342.

Return to Summary Table.

TX IPG Register 0.

Table 6-1341 MII_RT_TX_IPG0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2030h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2030h

Figure 6-676 MII_RT_TX_IPG0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						TX_IPG0
R-0h																						R/W-28h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1342 MII_RT_TX_IPG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h
15-0	TX_IPG0	R/W	28h	Define the minimum Inter Packet Gap. When MII_RT_TXCFG0[12] TX_IPG_WIRE_CLK_EN = 0h. This defines the minimum of ICSSGn_CORE_CLK (4 ns/5 ns) cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum. In general, software should program in increments of 8, 40 ns to insure the extra delays takes effect. When TX_IPG_WIRE_CLK_EN = 1h. This defines the minimum of TX interface clock cycles between the end of a frame and the start of a new frame 0h = 1 TX interface clock 3h = 4 TX interface clocks (96 ns for 1G) <n> = <n> +1 TX interface clocks expect for in SGMII 100M mode Note: In SGMII 100M mode, it will be <n> = <n> +5 TX interface clocks When software does an update, it takes 4 SGMII/RGMII/MII TX_CLKs before it goes into effect Min Values: MII >= 10 RGMII/SGMII 1G >= 11 (8 ns period) RGMII 100M >= 8 (40 ns period) SGMII 100M >= 24 (8 ns period) If the user violate, will get a jitter. The root cause most likely is that the data is not ready. TX MII Odd Nibble is NOT supported in this mode.

Bit

Field

Type

Reset

Description

31-16

RESERVED

15-0

TX_IPG0

R/W

28h

Define the minimum Inter Packet Gap.

When MII_RT_TXCFG0[12] TX_IPG_WIRE_CLK_EN = 0h. This defines the minimum of ICSSGn_CORE_CLK (4 ns/5 ns) cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum. In general, software should program in increments of 8, 40 ns to insure the extra delays takes effect.

When TX_IPG_WIRE_CLK_EN = 1h. This defines the minimum of TX interface clock cycles between the end of a frame and the start of a new frame

0h = 1 TX interface clock
3h = 4 TX interface clocks (96 ns for 1G)
<n> = <n> +1 TX interface clocks expect for in SGMII 100M mode

Note: In SGMII 100M mode, it will be <n> = <n> +5 TX interface clocks

When software does an update, it takes 4 SGMII/RGMII/MII TX_CLKs before it goes into effect

Min Values:
MII >= 10
RGMII/SGMII 1G >= 11 (8 ns period)
RGMII 100M >= 8 (40 ns period)
SGMII 100M >= 24 (8 ns period)

If the user violate, will get a jitter. The root cause most likely is that the data is not ready. TX MII Odd Nibble is NOT supported in this mode.

4.14.11.8 MII_RT_TX_IPG1 Register (Offset = 34h) [reset = X]

MII_RT_TX_IPG1 is shown in Figure 6-677 and described in Table 6-1344.

Return to Summary Table.

TX IPG Register 1.

Table 6-1343 MII_RT_TX_IPG1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2034h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2034h

Figure 6-677 MII_RT_TX_IPG1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						TX_IPG1
R/W-X																						R/W-28h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1344 MII_RT_TX_IPG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	TX_IPG1	R/W	28h	Define the minimum Inter Packet Gap. When MII_RT_TXCFG0[12] TX_IPG_WIRE_CLK_EN = 0h. This defines the minimum of ICSSGn_CORE_CLK (4 ns/5 ns) cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum. In general, software should program in increments of 8, 40 ns to insure the extra delays takes effect. When TX_IPG_WIRE_CLK_EN = 1h. This defines the minimum of TX interface clock cycles between the end of a frame and the start of a new frame 0h = 1 TX interface clock 3h = 4 TX interface clocks (96 ns for 1G) <n> = <n> +1 TX interface clocks expect for in SGMII 100M mode Note: In SGMII 100M mode, it will be <n> = <n> +5 TX interface clocks When software does an update, it takes 4 SGMII/RGMII/MII TX_CLKs before it goes into effect Min Values: MII >= 10 RGMII/SGMII 1G >= 11 (8 ns period) RGMII 100M >= 8 (40 ns period) SGMII 100M >= 24 (8 ns period) If the user violate, will get a jitter. The root cause most likely is that the data is not ready. TX MII Odd Nibble is NOT supported in this mode.

Bit

Field

Type

Reset

Description

31-16

RESERVED

R/W

15-0

TX_IPG1

R/W

28h

Define the minimum Inter Packet Gap.

When TX_IPG_WIRE_CLK_EN = 1h. This defines the minimum of TX interface clock cycles between the end of a frame and the start of a new frame

0h = 1 TX interface clock
3h = 4 TX interface clocks (96 ns for 1G)
<n> = <n> +1 TX interface clocks expect for in SGMII 100M mode

Note: In SGMII 100M mode, it will be <n> = <n> +5 TX interface clocks

When software does an update, it takes 4 SGMII/RGMII/MII TX_CLKs before it goes into effect

Min Values:
MII >= 10
RGMII/SGMII 1G >= 11 (8 ns period)
RGMII 100M >= 8 (40 ns period)
SGMII 100M >= 24 (8 ns period)

If the user violate, will get a jitter. The root cause most likely is that the data is not ready. TX MII Odd Nibble is NOT supported in this mode.

4.14.11.9 MII_RT_PRS0 Register (Offset = 38h) [reset = X]

MII_RT_PRS0 is shown in Figure 6-678 and described in Table 6-1346.

Return to Summary Table.

PORT_RAW_STATUS Register 0.

Table 6-1345 MII_RT_PRS0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2038h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2038h

Figure 6-678 MII_RT_PRS0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						SYNC_MII0_CRS	SYNC_MII0_COL
R-0h						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1346 MII_RT_PRS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h
1	SYNC_MII0_CRS	R	0h	Read the current state of PR1_MII0_CRS
0	SYNC_MII0_COL	R	0h	Read the current state of PR1_MII0_COL

4.14.11.10 MII_RT_PRS1 Register (Offset = 3Ch) [reset = X]

MII_RT_PRS1 is shown in Figure 6-679 and described in Table 6-1348.

Return to Summary Table.

PORT_RAW_STATUS Register 1.

Table 6-1347 MII_RT_PRS1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 203Ch
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 203Ch

Figure 6-679 MII_RT_PRS1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						SYNC_MII1_CRS	SYNC_MII1_COL
R-0h						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1348 MII_RT_PRS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h
1	SYNC_MII1_CRS	R	0h	Read the current state of PR1_MII1_CRS
0	SYNC_MII1_COL	R	0h	Read the current state of PR1_MII1_COL

4.14.11.11 MII_RT_RX_FRMS0 Register (Offset = 40h) [reset = 05F1003Fh]

MII_RT_RX_FRMS0 is shown in Figure 6-680 and described in Table 6-1350.

Return to Summary Table.

RX Frame Size Register 0.

Table 6-1349 MII_RT_RX_FRMS0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2040h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2040h

Figure 6-680 MII_RT_RX_FRMS0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_MAX_FRM0																RX_MIN_FRM0
R/W-5F1h																R/W-3Fh

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1350 MII_RT_RX_FRMS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RX_MAX_FRM0	R/W	5F1h	If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set. 0h = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC Notes if the incoming frame is truncated at the marker. So, RX CRC and RX ODD NIBBLE will not get asserted. If the PRU is moving the data the TX frame size will be aligned to the size of the push. For example push32, mod 4 bytes example push16, mod 2 bytes so, software should set the RX_MAX_FRM_CNT in this mode to align with the max push size. The event is always byte aligned. The final TX size is aligned to the push size.
15-0	RX_MIN_FRM0	R/W	3Fh	If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set. 0h = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC Notes: If the PRU is moving the data the TX frame size will be aligned to the size of the push. For example push32, mod 4 bytes example push16, mod 2 bytes so, software should set the RX_MIN_FRM_CNT in this mode to align with the max push size. The event is always byte aligned. The final TX size is aligned to the push size

4.14.11.12 MII_RT_RX_FRMS1 Register (Offset = 44h) [reset = 05F1003Fh]

MII_RT_RX_FRMS1 is shown in Figure 6-681 and described in Table 6-1352.

Return to Summary Table.

RX Frame Size Register 1.

Table 6-1351 MII_RT_RX_FRMS1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2044h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2044h

Figure 6-681 MII_RT_RX_FRMS1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX_MAX_FRM1																RX_MIN_FRM1
R/W-5F1h																R/W-3Fh

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1352 MII_RT_RX_FRMS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RX_MAX_FRM1	R/W	5F1h	If the FRAME total byte count is more than defined value, RX_MAX_FRM_ERR will get set. 0h = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC Notes if the incoming frame is truncated at the marker. So, RX CRC and RX ODD NIBBLE will not get asserted. If the PRU is moving the data the TX frame size will be aligned to the size of the push. For example push32, mod 4 bytes example push16, mod 2 bytes so, software should set the RX_MAX_FRM_CNT in this mode to align with the max push size. The event is always byte aligned. The final TX size is aligned to the push size.
15-0	RX_MIN_FRM1	R/W	3Fh	If the FRAME total byte count is less than defined value, RX_MIN_FRM_ERR will get set. 0h = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC Notes: If the PRU is moving the data the TX frame size will be aligned to the size of the push. For example push32, mod 4 bytes example push16, mod 2 bytes so, software should set the RX_MIN_FRM_CNT in this mode to align with the max push size. The event is always byte aligned. The final TX size is aligned to the push size

4.14.11.13 MII_RT_RX_PCNT0 Register (Offset = 48h) [reset = X]

MII_RT_RX_PCNT0 is shown in Figure 6-682 and described in Table 6-1354.

Return to Summary Table.

RX Preamble Cnt Register 0.

Table 6-1353 MII_RT_RX_PCNT0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2048h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2048h

Figure 6-682 MII_RT_RX_PCNT0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED							RX_MAX_PCNT0					RX_MIN_PCNT0
R-0h							R/W-Eh					R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1354 MII_RT_RX_PCNT0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h
8-4	RX_MAX_PCNT0	R/W	Eh	Define the max number of nibbles until first SFD/SMD is matched. RX_MAX_PRE_COUNT_ERR will set if the preamble count more than 0h= Disabled 1h = Reserved 2h = 4th nibble needs to have built 0xD5/SMD Eh= 16th nibble needs to have built 0xD5/SMD if not matched then 16th nibble will cause the error to assert and truncate the incoming frame. Note the 16th nibble is transmitted Any valid IET SMD or 0xD5 If > max then, hardware will issue a SFD and set error flags CRC can/will be bad for this packet
3-0	RX_MIN_PCNT0	R/W	1h	Define the minimum number of nibbles before SFD 0xD5 RX_MIN_PRE_COUNT_ERR will set if the preamble count less than 0h = is Disabled 1h = Minimum of 1 0x5 before 0xD5 2h = Minimum of 2 0x5 before 0xD5 <n> minimum of <n> 0x5 before 0xD5 Note it does not need to be “0x5”

4.14.11.14 MII_RT_RX_PCNT1 Register (Offset = 4Ch) [reset = X]

MII_RT_RX_PCNT1 is shown in Figure 6-683 and described in Table 6-1356.

Return to Summary Table.

RX Preamble Cnt Register 1.

Table 6-1355 MII_RT_RX_PCNT1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 204Ch
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 204Ch

Figure 6-683 MII_RT_RX_PCNT1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED							RX_MAX_PCNT1					RX_MIN_PCNT1
R-0h							R/W-Eh					R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1356 MII_RT_RX_PCNT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h
8-4	RX_MAX_PCNT1	R/W	Eh	Define the max number of nibbles until first SFD/SMD is matched. RX_MAX_PRE_COUNT_ERR will set if the preamble count more than 0h = Disabled 1h = Reserved 2h = 4th nibble needs to have built 0xD5/SMD Eh= 16th nibble needs to have built 0xD5/SMD if not matched then 16th nibble will cause the error to assert and truncate the incoming frame. Note the 16th nibble is transmitted Any valid IET SMD or 0xD5 If > max then, hardware will issue a SFD and set error flags CRC can/will be bad for this packet
3-0	RX_MIN_PCNT1	R/W	1h	Define the minimum number of nibbles before SFD 0xD5 RX_MIN_PRE_COUNT_ERR will set if the preamble count less than 0h = is Disabled 1h = Minimum of 1 0x5 before 0xD5 2h = Minimum of 2 0x5 before 0xD5 <n> minimum of <n> 0x5 before 0xD5 Note it does not need to be “0x5”

4.14.11.15 MII_RT_RX_ERR0 Register (Offset = 50h) [reset = X]

MII_RT_RX_ERR0 is shown in Figure 6-684 and described in Table 6-1358.

Return to Summary Table.

RX Error Register 0.

Table 6-1357 MII_RT_RX_ERR0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2050h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2050h

Figure 6-684 MII_RT_RX_ERR0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RX_MAX_FRM_ERR0	RX_MIN_FRM_ERR0	RX_MAX_PCNT_ERR0	RX_MIN_PCNT_ERR0
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1358 MII_RT_RX_ERR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	RX_MAX_FRM_ERR0	R/W	0h	Set when the FRAME total byte count is more than defined value. Write 1 to Clear
2	RX_MIN_FRM_ERR0	R/W	0h	Set when the FRAME total byte count is less than defined value. Write 1 to Clear
1	RX_MAX_PCNT_ERR0	R/W	0h	Set when of x nibbles before SFD 0xD5 is more than defined value. Write 1 to Clear
0	RX_MIN_PCNT_ERR0	R/W	0h	Set when of 0x5 before SFD 0xD5 is less than defined value. Write 1 to Clear

4.14.11.16 MII_RT_RX_ERR1 Register (Offset = 54h) [reset = X]

MII_RT_RX_ERR1 is shown in Figure 6-685 and described in Table 6-1360.

Return to Summary Table.

RX Error Register 1.

Table 6-1359 MII_RT_RX_ERR1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2054h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2054h

Figure 6-685 MII_RT_RX_ERR1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RX_MAX_FRM_ERR1	RX_MIN_FRM_ERR1	RX_MAX_PCNT_ERR1	RX_MIN_PCNT_ERR1
R-0h				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1360 MII_RT_RX_ERR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h
3	RX_MAX_FRM_ERR1	R/W	0h	Set when the FRAME total byte count is more than defined value. Write 1 to Clear
2	RX_MIN_FRM_ERR1	R/W	0h	Set when the FRAME total byte count is less than defined value. Write 1 to Clear
1	RX_MAX_PCNT_ERR1	R/W	0h	Set when of x nibbles before SFD 0xD5 is more than defined value. Write 1 to Clear
0	RX_MIN_PCNT_ERR1	R/W	0h	Set when of 0x5 before SFD 0xD5 is less than defined value. Write 1 to Clear

4.14.11.17 MII_RT_RX_FIFO_LEVEL0 Register (Offset = 60h) [reset = X]

MII_RT_RX_FIFO_LEVEL0 is shown in Figure 6-686 and described in Table 6-1362.

Return to Summary Table.

RX FIFO Level 0 Register.

Table 6-1361 MII_RT_RX_FIFO_LEVEL0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2060h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2060h

Figure 6-686 MII_RT_RX_FIFO_LEVEL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								RX_FIFO_LEVEL0
R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1362 MII_RT_RX_FIFO_LEVEL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	RX_FIFO_LEVEL0	R	0h	Define the number of valid bytes in the RX FIFO. 0h = Empty 1h = 1 Byte/ 2 Nibbles 2h = 2 Byte/ 4 Nibble ... 20h = 32 Bytes/ 64 Nibbles

4.14.11.18 MII_RT_RX_FIFO_LEVEL1 Register (Offset = 64h) [reset = X]

MII_RT_RX_FIFO_LEVEL1 is shown in Figure 6-687 and described in Table 6-1364.

Return to Summary Table.

RX FIFO Level 1 Register.

Table 6-1363 MII_RT_RX_FIFO_LEVEL1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2064h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2064h

Figure 6-687 MII_RT_RX_FIFO_LEVEL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								RX_FIFO_LEVEL1
R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1364 MII_RT_RX_FIFO_LEVEL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	RX_FIFO_LEVEL1	R	0h	Define the number of valid bytes in the RX FIFO. 0h = Empty 1h = 1 Byte/ 2 Nibbles 2h = 2 Byte/ 4 Nibble ... 20h = 32 Bytes/ 64 Nibbles

4.14.11.19 MII_RT_TX_FIFO_LEVEL0 Register (Offset = 68h) [reset = X]

MII_RT_TX_FIFO_LEVEL0 is shown in Figure 6-688 and described in Table 6-1366.

Return to Summary Table.

TX FIFO Register 0.

Table 6-1365 MII_RT_TX_FIFO_LEVEL0 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 2068h
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 2068h

Figure 6-688 MII_RT_TX_FIFO_LEVEL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TX_FIFO_LEVEL0
R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1366 MII_RT_TX_FIFO_LEVEL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	TX_FIFO_LEVEL0	R	0h	Define the number of valid nibbles in the TX FIFO. 0 = Empty 1 = 1 Nibble 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles

4.14.11.20 MII_RT_TX_FIFO_LEVEL1 Register (Offset = 6Ch) [reset = X]

MII_RT_TX_FIFO_LEVEL1 is shown in Figure 6-689 and described in Table 6-1368.

Return to Summary Table.

TX FIFO Register 1.

Table 6-1367 MII_RT_TX_FIFO_LEVEL1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG	3003 206Ch
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG	300B 206Ch

Figure 6-689 MII_RT_TX_FIFO_LEVEL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TX_FIFO_LEVEL1
R-X								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1368 MII_RT_TX_FIFO_LEVEL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h
7-0	TX_FIFO_LEVEL1	R	0h	Define the number of valid nibbles in the TX FIFO. 0 = Empty 1 = 1 Nibble 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles