SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

10.2.5.1 TIMERMGR_CFG_CFG Registers

Table 10-90 lists the memory-mapped registers for the TIMERMGR_CFG_CFG. All register offset addresses not listed in Table 10-90 should be considered as reserved locations and the register contents should not be modified.

CFG MMR definitions

Table 10-89 TIMERMGR_CFG_CFG Instances

Instance	Base Address
TIMERMGR0_CFG	3CD0 0000h

Table 10-90 TIMERMGR_CFG_CFG Registers

Offset	Acronym	Register Name	TIMERMGR0_CFG Physical Address
0h	TIMERMGR_PID	Peripheral ID register	3CD0 0000h
4h	TIMERMGR_CNTL	Timer manager control	3CD0 0004h
8h	TIMERMGR_COUNTER	The current counter value	3CD0 0008h
A0h	TIMERMGR_TIMEOUT_STATUS0	Must be read whenever the timer interrupt fires	3CD0 00A0h
A4h	TIMERMGR_TIMEOUT_STATUS1	Contains the IDs of the second and third timers to expire	3CD0 00A4h
A8h	TIMERMGR_TIMEOUT_STATUS_BANK0	Contains the status of each timer bank for banks 31-0	3CD0 00A8h
100h + formula	TIMERMGR_STATUS_y	Each bit is the timeout status for an individual timer	3CD0 0100h + formula

2.5.1.1 TIMERMGR_PID Register (Offset = 0h) [reset = Xh]

TIMERMGR_PID is shown in Figure 10-47 and described in Table 10-92.

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This is the standard TI peripheral ID register that exists at address 0 in the peripheral space

Reset = CDF0 5201h

Table 10-91 TIMERMGR_PID Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 0000h

Figure 10-47 TIMERMGR_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		FUNCTION
R-1h		R-2h		R-6F8h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTL_VER					MAJOR_REV			CUSTOM		MINOR_REV
R-5h					R-1h			R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 10-92 TIMERMGR_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	scheme
29-28	BU	R	2h	bu identifier
27-16	FUNCTION	R	6F8h	function identifier
15-11	RTL_VER	R	5h	RTL version number
10-8	MAJOR_REV	R	1h	Major revision number
7-6	CUSTOM	R	0h	custom
5-0	MINOR_REV	R	1h	Minor revision number

2.5.1.2 TIMERMGR_CNTL Register (Offset = 4h) [reset = X]

TIMERMGR_CNTL is shown in Figure 10-48 and described in Table 10-94.

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This register controls the overall behavior of the timer manager module

Table 10-93 TIMERMGR_CNTL Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 0004h

Figure 10-48 TIMERMGR_CNTL Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED			MASS_ENABLE	RESERVED	MAX_TIMER
R/W-X			W-0h	R/W-X	R/W-3FFh

7	6	5	4	3	2	1	0
MAX_TIMER							ENABLE
R/W-3FFh							R/W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 10-94 TIMERMGR_CNTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R/W	X
12	MASS_ENABLE	W	0h	Always reads zero. When a 1 is written to this bit, all timers from 0 to the MAX_TIMER will be enabled. Useful for initial programming, to not need to loop over every TIMERMGR_CONTROL_j_k register to enable every timer if many or all are being used. This should only be used during initialization, or when ENABLE is set to 0, as this does not set the timers, only enable them
11	RESERVED	R/W	X
10-1	MAX_TIMER	R/W	3FFh	The maximum timer that will be checked - e.g. if only using 512 timers, set this to 511. All timers above this number will be ignored. Should be set once during initialization
0	ENABLE	R/W	0h	Enables the timer manager. When this bit is zero, the timers will all be halted and will not count 0h = Timer Manager is disabled 1h = Timer Manager is enabled

2.5.1.3 TIMERMGR_COUNTER Register (Offset = 8h) [reset = 0h]

TIMERMGR_COUNTER is shown in Figure 10-49 and described in Table 10-96.

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This register contains the current TIMERMGR_COUNTER value

Table 10-95 TIMERMGR_COUNTER Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 0008h

Figure 10-49 TIMERMGR_COUNTER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 10-96 TIMERMGR_COUNTER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R	0h	The current timer_counter value, in the timebase being used by all timers in this module

2.5.1.4 TIMERMGR_TIMEOUT_STATUS0 Register (Offset = A0h) [reset = X]

TIMERMGR_TIMEOUT_STATUS0 is shown in Figure 10-50 and described in Table 10-98.

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This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1, this is the only register that needs to be read. Depending on the value of NUM_EXPIRED_TIMERS, either TIMERMGR_TIMEOUT_STATUS1 or TIMERMGR_TIMEOUT_STATUS_BANK0 may be read by the software to avoid needing to read all 32 TIMERMGR_STATUS_y registers.

Table 10-97 TIMERMGR_TIMEOUT_STATUS0 Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 00A0h

Figure 10-50 TIMERMGR_TIMEOUT_STATUS0 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
VALID0	EXPIRED_TIMER0
R-0h	R-0h

15	14	13	12	11	10	9	8
EXPIRED_TIMER0				NUM_EXPIRED_TIMERS
R-0h				R-0h

7	6	5	4	3	2	1	0
NUM_EXPIRED_TIMERS
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 10-98 TIMERMGR_TIMEOUT_STATUS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X
23	VALID0	R	0h	1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers > 0, this should always be a 1
22-12	EXPIRED_TIMER0	R	0h	The ID of the first timer to expire
11-0	NUM_EXPIRED_TIMERS	R	0h	The total number of expired timers

2.5.1.5 TIMERMGR_TIMEOUT_STATUS1 Register (Offset = A4h) [reset = X]

TIMERMGR_TIMEOUT_STATUS1 is shown in Figure 10-51 and described in Table 10-100.

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This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all 1024 timers.

Table 10-99 TIMERMGR_TIMEOUT_STATUS1 Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 00A4h

Figure 10-51 TIMERMGR_TIMEOUT_STATUS1 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
VALID2	EXPIRED_TIMER2
R-0h	R-0h

15	14	13	12	11	10	9	8
EXPIRED_TIMER2				VALID1	EXPIRED_TIMER1
R-0h				R-0h	R-0h

7	6	5	4	3	2	1	0
EXPIRED_TIMER1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 10-100 TIMERMGR_TIMEOUT_STATUS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X
23	VALID2	R	0h	1 indicates that expired_timer2 is valid
22-12	EXPIRED_TIMER2	R	0h	The ID of the third timer to expire
11	VALID1	R	0h	1 indicates that expired_timer1 is valid
10-0	EXPIRED_TIMER1	R	0h	The ID of the second timer to expire

2.5.1.6 TIMERMGR_TIMEOUT_STATUS_BANK0 Register (Offset = A8h) [reset = 0h]

TIMERMGR_TIMEOUT_STATUS_BANK0 is shown in Figure 10-52 and described in Table 10-102.

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This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt, if the num_expired_timers bit is greater than 3, this register may be read to see which banks contain expired timers. The TIMERMGR_STATUS_y registers corresponding to those banks may then be read.

Table 10-101 TIMERMGR_TIMEOUT_STATUS_BANK0 Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 00A8h

Figure 10-52 TIMERMGR_TIMEOUT_STATUS_BANK0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 10-102 TIMERMGR_TIMEOUT_STATUS_BANK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R	0h	A 1 in bit N indicates that the corresponding bank has expired timers

2.5.1.7 TIMERMGR_STATUS_y Register (Offset = 100h + formula) [reset = 0h]

TIMERMGR_STATUS_y is shown in Figure 10-53 and described in Table 10-104.

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Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled, 1 = timer has timed out

Offset = 100h + (y * 4h); where y = 0h to 1Fh

Table 10-103 TIMERMGR_STATUS_y Instances

Instance	Physical Address
TIMERMGR0_CFG	3CD0 0100h + formula

Figure 10-53 TIMERMGR_STATUS_y Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 10-104 TIMERMGR_STATUS_y Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R	0h	Each bit is the timeout status for an individual timer