SPRUIM2 User guide

12.2.1.6.3 CPSW0_CPTS Registers

Table 12-751 lists the memory-mapped registers for the CPSW0_CPTS. All register offset addresses not listed in Table 12-751 should be considered as reserved locations and the register contents should not be modified.

Table 12-750 CPSW0_CPTS Instances

Instance	Base Address
CPSW0_NUSS_CPTS	0800 0000h

Table 12-751 CPSW0_CPTS Registers

Offset⁽¹⁾	Acronym	Register Name	CPSW0_NUSS_CPTS Physical Address
0003D000h	CPSW_CPTS_IDVER_REG	CPSW0 CPTS Identification and Version Register	0803 D000h
0003D004h	CPSW_CPTS_CONTROL_REG	Time Sync Control Register	0803 D004h
0003D008h	CPSW_CPTS_RFTCLK_SEL_REG	Reference Clock Select Register	0803 D008h
0003D00Ch	CPSW_CPTS_TS_PUSH_REG	Time Stamp Event Push Register	0803 D00Ch
0003D010h	CPSW_CPTS_TS_LOAD_VAL_REG	Time Stamp Load Low Value (lower 32-bits) Register	0803 D010h
0003D014h	CPSW_CPTS_TS_LOAD_EN_REG	Time Stamp Load Enable Register	0803 D014h
0003D018h	CPSW_CPTS_TS_COMP_VAL_REG	Time Stamp Comparison Low Value (lower 32-bits) Register	0803 D018h
0003D01Ch	CPSW_CPTS_TS_COMP_LEN_REG	Time Stamp Comparison Length Register	0803 D01Ch
0003D020h	CPSW_CPTS_INTSTAT_RAW_REG	Interrupt Status Raw Register	0803 D020h
0003D024h	CPSW_CPTS_INTSTAT_MASKED_REG	Interrupt Status Masked Register	0803 D024h
0003D028h	CPSW_CPTS_INT_ENABLE_REG	Interrupt Enable Register Register	0803 D028h
0003D02Ch	CPSW_CPTS_TS_COMP_NUDGE_REG	Time Stamp Comparison Nudge Value Register	0803 D02Ch
0003D030h	CPSW_CPTS_EVENT_POP_REG	Event Interrupt Pop Register	0803 D030h
0003D034h	CPSW_CPTS_EVENT_0_REG	Lower 32-bits of the Event Value Register	0803 D034h
0003D038h	CPSW_CPTS_EVENT_1_REG	Lower Middle 32-bits of the Event Value Register	0803 D038h
0003D03Ch	CPSW_CPTS_EVENT_2_REG	Upper Middle 32-bits of the Event Value Register	0803 D03Ch
0003D040h	CPSW_CPTS_EVENT_3_REG	Upper 32-bits of the Event Value Register	0803 D040h
0003D044h	CPSW_CPTS_TS_LOAD_HIGH_VAL_REG	Time Stamp Load High Value (upper 32-bits) Register	0803 D044h
0003D048h	CPSW_CPTS_TS_COMP_HIGH_VAL_REG	Time Stamp Comparison High Value (upper 32-bits) Register	0803 D048h
0003D04Ch	CPSW_CPTS_TS_ADD_VAL_REG	Time Stamp Add Value Register	0803 D04Ch
0003D050h	CPSW_CPTS_TS_PPM_LOW_VAL_REG	Time Stamp PPM Load Low Value (lower 32-bits) Register	0803 D050h
0003D054h	CPSW_CPTS_TS_PPM_HIGH_VAL_REG	Time Stamp PPM Load High Value (upper 32-bits) Register	0803 D054h
0003D058h	CPSW_CPTS_TS_NUDGE_VAL_REG	Time Stamp Nudge Value Register	0803 D058h
0003 D0D0h	CPSW_CPTS_TS_CONFIG_REG	Time Stamp Configuration Read Register	0803 D0D0h
0003D0E0h	CPSW_GENF0_COMP_LOW_REG	GENF0 Time Stamp Comparison Value Lower 32-bits Registers	0803 D0E0h
0003D0E4h	CPSW_GENF0_COMP_HIGH_REG	GENF0 Time Stamp Comparison Value Upper 32-bits Registers	0803 D0E4h
0003D0E8h	CPSW_GENF0_CONTROL_REG	GENF0 Control Register Registers	0803 D0E8h
0003D0ECh	CPSW_GENF0_LENGTH_REG	GENF0 Length Value Registers	0803 D0ECh
0003D0F0h	CPSW_GENF0_PPM_LOW_REG	GENF0 PPM Value Lower 32-bits Registers	0803 D0F0h
0003D0F4h	CPSW_GENF0_PPM_HIGH_REG	GENF0 PPM Value Upper 32-bits Registers	0803 D0F4h
0003D0F8h	CPSW_GENF0_NUDGE_REG	GENF0 Nudge Value Registers	0803 D0F8h
0003D100h	CPSW_GENF1_COMP_LOW_REG	GENF1 time stamp Comparison Value Lower 32-bits Register	0803 D100h
0003D104h	CPSW_GENF1_COMP_HIGH_REG	GENF1 time stamp Comparison Value Upper 32-bits Register	0803 D104h
0003D108h	CPSW_GENF1_CONTROL_REG	GENF1 Control Register	0803 D108h
0003D10Ch	CPSW_GENF1_LENGTH_REG	GENF1 Length Value Register	0803 D10Ch
0003D110h	CPSW_GENF1_PPM_LOW_REG	GENF1 PPM Value Lower 32-bits Register	0803 D110h
0003D114h	CPSW_GENF1_PPM_HIGH_REG	GENF1 PPM Value Upper 32-bits Register	0803 D114h
0003D118h	CPSW_GENF1_NUDGE_REG	GENF1 Nudge Value Register	0803 D118h
0003D200h + formula	CPSW_ESTF_COMP_LOW_REG_l	ESTFn (n = 1 to 2) Time Stamp Comparison Value Lower 32-bits Register	0803 D200h + formula
0003D204h + formula	CPSW_ESTF_COMP_HIGH_REG_l	ESTFn (n = 1 to 2) Time Stamp Comparison Value Upper 32-bits Register	0803 D204h + formula
0003D208h + formula	CPSW_ESTF_CONTROL_REG_l	ESTFn (n = 1 to 2) Control Register	0803 D208h + formula
0003D20Ch + formula	CPSW_ESTF_LENGTH_REG_l	ESTFn (n = 1 to 2) Length Value Register	0803 D20Ch + formula
0003D210h + formula	CPSW_ESTF_PPM_LOW_REG_l	ESTFn (n = 1 to 2) PPM Value Lower 32-bits Register	0803 D210h + formula
0003D214h + formula	CPSW_ESTF_PPM_HIGH_REG_l	ESTFn (n = 1 to 2) PPM Value Upper 32-bits Register	0803 D214h + formula
0003D218h + formula	CPSW_ESTF_NUDGE_REG_l	ESTFn (n = 1 to 2) Nudge Value Register	0803 D218h + formula

(1) l = 0 to 1

1.6.3.1 CPSW_CPTS_IDVER_REG Register (Offset = 0003D000h) [reset = 4E8A210Bh]

CPSW_CPTS_IDVER_REG is shown in Figure 12-406 and described in Table 12-753.

Return to Summary Table.

CPSW0_NUSS CPTS Identification and Version Register.

Table 12-752 CPSW_CPTS_IDVER_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D000h

Figure 12-406 CPSW_CPTS_IDVER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TX_IDENT
R-4E8Ah

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTL_VER					MAJOR_VER			MINOR_VER
R-4h					R-1h			R-Bh

LEGEND: R = Read Only; -n = value after reset

Table 12-753 CPSW_CPTS_IDVER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TX_IDENT	R	4E8Ah	Identification value.
15-11	RTL_VER	R	4h	RTL version value.
10-8	MAJOR_VER	R	1h	Major version value.
7-0	MINOR_VER	R	Bh	Minor version value.

1.6.3.2 CPSW_CPTS_CONTROL_REG Register (Offset = 0003D004h) [reset = X]

CPSW_CPTS_CONTROL_REG is shown in Figure 12-407 and described in Table 12-755.

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Time Sync Control Register.

Table 12-754 CPSW_CPTS_CONTROL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D004h

Figure 12-407 CPSW_CPTS_CONTROL_REG Register

31	30	29	28	27	26	25	24
TS_SYNC_SEL				RESERVED
R/W-0h				R/W-X

23	22	21	20	19	18	17	16
RESERVED						TS_GENF_CLR_EN	TS_RX_NO_EVENT
R/W-X						R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
HW8_TS_PUSH_EN	HW7_TS_PUSH_EN	HW6_TS_PUSH_EN	HW5_TS_PUSH_EN	HW4_TS_PUSH_EN	HW3_TS_PUSH_EN	HW2_TS_PUSH_EN	HW1_TS_PUSH_EN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
TS_PPM_DIR	TS_COMP_TOG	MODE	SEQUENCE_EN	TSTAMP_EN	TS_COMP_POLARITY	INT_TEST	CPTS_EN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-755 CPSW_CPTS_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	TS_SYNC_SEL	R/W	0h	TS_SYNC output time stamp counter bit select. 0h = TS_SYNC disabled. 1h to Fh = TS_SYNC is time stamp counter bits 31 (Fh) down to 17 (1h).
27-18	RESERVED	R/W	0h
17	TS_GENF_CLR_EN	R/W	0h	GENF (and ESTF) Clear Enable. 0h = A CPTS_GENFn output is not cleared when the associated CPSW_GENF0_LENGTH_REG/ CPSW_GENF1_LENGTH_REG[31:0] is cleared to zero. 1h = A CPTS_GENFn output is cleared when the associated CPSW_GENF0_LENGTH_REG/ CPSW_GENF1_LENGTH_REG[31:0] is cleared to zero.
16	TS_RX_NO_EVENT	R/W	0h	Timestamp Ethernet Receive produces no events. 0h = Ethernet receive timesync events enabled. 1h = Ethernet receive timesync events disabled.
15	HW8_TS_PUSH_EN	R/W	0h	Hardware push 8 enable.
14	HW7_TS_PUSH_EN	R/W	0h	Hardware push 7 enable.
13	HW6_TS_PUSH_EN	R/W	0h	Hardware push 6 enable.
12	HW5_TS_PUSH_EN	R/W	0h	Hardware push 5 enable.
11	HW4_TS_PUSH_EN	R/W	0h	Hardware push 4 enable.
10	HW3_TS_PUSH_EN	R/W	0h	Hardware push 3 enable.
9	HW2_TS_PUSH_EN	R/W	0h	Hardware push 2 enable.
8	HW1_TS_PUSH_EN	R/W	0h	Hardware push 1 enable.
7	TS_PPM_DIR	R/W	0h	PPM Correction Direction. 0h = Increase the TIME_STAMP[63:0] value (CPSW_CPTS_EVENT_0_REG and CPSW_CPTS_EVENT_3_REG) by the PPM value. 1h = Decrease the TIME_STAMP[63:0] value (CPSW_CPTS_EVENT_0_REG and CPSW_CPTS_EVENT_3_REG and) by the PPM value.
6	TS_COMP_TOG	R/W	0h	Time Stamp Compare Toggle mode. 0h = TS_COMP is in non-toggle mode. 1h = TS_COMP is in toggle mode.
5	MODE	R/W	0h	64-Bit Mode. 0h = The time stamp is 32-bits with the upper 32-bits forced to zero. 1h = The time stamp is 64-bits.
4	SEQUENCE_EN	R/W	0h	Sequence Enable. 0h = The time stamp value increments with the selected RFTCLK 1h = The time stamp for received packets is the sequence number of the received packet (first packet is 1, second packet is 2, etc).
3	TSTAMP_EN	R/W	0h	Host Receive Time Stamp Enable. 0h = Time stamps are disabled on received packets to host. 1h = Time stamps enabled on received packets to host (PCIE_CPTS_CONTROL_REG[0] CPTS_EN must be set).
2	TS_COMP_POLARITY	R/W	1h	TS_COMP Polarity. 0h = TS_COMP is asserted low. 1h = TS_COMP is asserted high.
1	INT_TEST	R/W	0h	Interrupt Test. When set, this bit allows the raw interrupt to be written to facilitate interrupt test.
0	CPTS_EN	R/W	0h	Time Sync Enable. When disabled (cleared to zero), the RCLK domain is held in reset.

1.6.3.3 CPSW_CPTS_RFTCLK_SEL_REG Register (Offset = 0003D008h) [reset = X]

CPSW_CPTS_RFTCLK_SEL_REG is shown in Figure 12-408 and described in Table 12-757.

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RFTCLK Select Register.

Table 12-756 CPSW_CPTS_RFTCLK_SEL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D008h

Figure 12-408 CPSW_CPTS_RFTCLK_SEL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											RFTCLK_SEL
R/W-X											R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-757 CPSW_CPTS_RFTCLK_SEL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R/W	X
4-0	RFTCLK_SEL	R/W	0h	Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h = Selects CPSWHSDIV_CLKOUT2 clock 1h = Selects MAINHSDIV_CLKOUT3 clock 2h = Selects MCU_CPTS0_RFT_CLK I/O pin 3h = Selects CPTS0_RFT_CLK I/O pin 4h = Selects MCU_EXT_REFCLK0 I/O pin 5h = Selects EXT_REFCLK1 I/O pin 6h = Selects PCIE0_TXI0_CLK clock 7h = Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL value can be written only when the [0] CPTS_EN and [3] TSTAMP_EN bits are cleared to zero in the CPSW_CPTS_CONTROL_REG register.

Bit

Field

Type

Reset

Description

31-5

RESERVED

R/W

4-0

RFTCLK_SEL

R/W

Reference clock select.

This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference.

0h = Selects CPSWHSDIV_CLKOUT2 clock

1h = Selects MAINHSDIV_CLKOUT3 clock

2h = Selects MCU_CPTS0_RFT_CLK I/O pin

3h = Selects CPTS0_RFT_CLK I/O pin

4h = Selects MCU_EXT_REFCLK0 I/O pin

5h = Selects EXT_REFCLK1 I/O pin

6h = Selects PCIE0_TXI0_CLK clock

7h = Selects PCIE1_TXI0_CLK clock

The RFTCLK_SEL value can be written only when the [0] CPTS_EN and [3] TSTAMP_EN bits are cleared to zero in the CPSW_CPTS_CONTROL_REG register.

1.6.3.4 CPSW_CPTS_TS_PUSH_REG Register (Offset = 0003D00Ch) [reset = X]

CPSW_CPTS_TS_PUSH_REG is shown in Figure 12-409 and described in Table 12-759.

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Time Stamp Event Push Register.

Table 12-758 CPSW_CPTS_TS_PUSH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D00Ch

Figure 12-409 CPSW_CPTS_TS_PUSH_REG Register

31	30	29	28	27	26	25	24
RESERVED
W-X

23	22	21	20	19	18	17	16
RESERVED
W-X

15	14	13	12	11	10	9	8
RESERVED
W-X

7	6	5	4	3	2	1	0
RESERVED							TS_PUSH
W-X							W-0h

LEGEND: W = Write Only; -n = value after reset

Table 12-759 CPSW_CPTS_TS_PUSH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	W	X
0	TS_PUSH	W	0h	Time stamp event push. When a logic high is written to this bit a time stamp event is pushed onto the event FIFO. The time stamp value is the time of the write of this register, not the time of the event read. The time stamp value can then be read on interrupt via the event registers. Software should not push a second time stamp event onto the event FIFO until the first time stamp value has been read from the event FIFO (there should be only one time stamp event in the event FIFO at any given time). This bit is write only and always reads zero.

1.6.3.5 CPSW_CPTS_TS_LOAD_VAL_REG Register (Offset = 0003D010h) [reset = 0h]

CPSW_CPTS_TS_LOAD_VAL_REG is shown in Figure 12-410 and described in Table 12-761.

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Time Stamp Load Low Value Register.

Table 12-760 CPSW_CPTS_TS_LOAD_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D010h

Figure 12-410 CPSW_CPTS_TS_LOAD_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_LOAD_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-761 CPSW_CPTS_TS_LOAD_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TS_LOAD_VAL	R/W	0h	Time stamp load low value.

1.6.3.6 CPSW_CPTS_TS_LOAD_EN_REG Register (Offset = 0003D014h) [reset = X]

CPSW_CPTS_TS_LOAD_EN_REG is shown in Figure 12-411 and described in Table 12-763.

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Time Stamp Load Enable Register.

Table 12-762 CPSW_CPTS_TS_LOAD_EN_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D014h

Figure 12-411 CPSW_CPTS_TS_LOAD_EN_REG Register

31	30	29	28	27	26	25	24
RESERVED
W-X

23	22	21	20	19	18	17	16
RESERVED
W-X

15	14	13	12	11	10	9	8
RESERVED
W-X

7	6	5	4	3	2	1	0
RESERVED							TS_LOAD_EN
W-X							W-0h

LEGEND: W = Write Only; -n = value after reset

Table 12-763 CPSW_CPTS_TS_LOAD_EN_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	W	X
0	TS_LOAD_EN	W	0h	Time Stamp Load Enable. Writing a one to this bit enables the time stamp value to be written with the value in CPSW_CPTS_TS_LOAD_VAL_REG/ CPSW_CPTS_TS_LOAD_HIGH_VAL_REG. This bit is write only and will be cleared by the hardware after one clock. The upper 32-bits of the time stamp (CPSW_CPTS_TS_LOAD_HIGH_VAL_REG) are forced to zero in 32-bit mode.

1.6.3.7 CPSW_CPTS_TS_COMP_VAL_REG Register (Offset = 0003D018h) [reset = 0h]

CPSW_CPTS_TS_COMP_VAL_REG is shown in Figure 12-412 and described in Table 12-765.

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Time Stamp Comparison Low Value (lower 32-bits) Register.

Table 12-764 CPSW_CPTS_TS_COMP_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D018h

Figure 12-412 CPSW_CPTS_TS_COMP_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_COMP_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-765 CPSW_CPTS_TS_COMP_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TS_COMP_VAL	R/W	0h	Time Stamp Comparison Low Value. Writing a non-zero value to the CPSW_CPTS_TS_COMP_LEN_REG[31-0] TS_COMP_LENGTH register causes a pulse of TS_COMP_LENGTH RCLK periods on the TS_COMP output and a comparison event when the TIME_STAMP counter value is equivalent to CPSW_CPTS_TS_COMP_VAL_REG[31-0] TS_COMP_VAL.

1.6.3.8 CPSW_CPTS_TS_COMP_LEN_REG Register (Offset = 0003D01Ch) [reset = 0h]

CPSW_CPTS_TS_COMP_LEN_REG is shown in Figure 12-413 and described in Table 12-767.

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Time Stamp Comparison Length Register.

Table 12-766 CPSW_CPTS_TS_COMP_LEN_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D01Ch

Figure 12-413 CPSW_CPTS_TS_COMP_LEN_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_COMP_LENGTH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-767 CPSW_CPTS_TS_COMP_LEN_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TS_COMP_LENGTH	R/W	0h	Time Stamp Comparison Length. Writing a non-zero value to this field enables the time stamp comparison event and output. This value should be zero when the CPSW_GENF0_COMP_LOW_REG[31-0] COMP_LOW and CPSW_GENF0_COMP_HIGH_REG[31-0] COMP_HIGH registers are written.

1.6.3.9 CPSW_CPTS_INTSTAT_RAW_REG Register (Offset = 0003D020h) [reset = X]

CPSW_CPTS_INTSTAT_RAW_REG is shown in Figure 12-414 and described in Table 12-769.

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Interrupt Status Register Raw.

Table 12-768 CPSW_CPTS_INTSTAT_RAW_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D020h

Figure 12-414 CPSW_CPTS_INTSTAT_RAW_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							TS_PEND_RAW
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-769 CPSW_CPTS_INTSTAT_RAW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	TS_PEND_RAW	R/W	0h	TS_PEND_RAW int read (before enable). Writable when CPSW_CPTS_CONTROL_REG[1] INT_TEST = 1h A one in this bit indicates that there are one or more events in the event FIFO.

1.6.3.10 CPSW_CPTS_INTSTAT_MASKED_REG Register (Offset = 0003D024h) [reset = X]

CPSW_CPTS_INTSTAT_MASKED_REG is shown in Figure 12-415 and described in Table 12-771.

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Interrupt Status Register Masked.

Table 12-770 CPSW_CPTS_INTSTAT_MASKED_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D024h

Figure 12-415 CPSW_CPTS_INTSTAT_MASKED_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED							TS_PEND
R-X							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-771 CPSW_CPTS_INTSTAT_MASKED_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X
0	TS_PEND	R	0h	TS_PEND masked interrupt read (after enable).

1.6.3.11 CPSW_CPTS_INT_ENABLE_REG Register (Offset = 0003D028h) [reset = X]

CPSW_CPTS_INT_ENABLE_REG is shown in Figure 12-416 and described in Table 12-773.

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Interrupt Enable Register.

Table 12-772 CPSW_CPTS_INT_ENABLE_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D028h

Figure 12-416 CPSW_CPTS_INT_ENABLE_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							TS_PEND_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-773 CPSW_CPTS_INT_ENABLE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	TS_PEND_EN	R/W	0h	TS_PEND masked interrupt enable.

1.6.3.12 CPSW_CPTS_TS_COMP_NUDGE_REG Register (Offset = 0003D02Ch) [reset = X]

CPSW_CPTS_TS_COMP_NUDGE_REG is shown in Figure 12-417 and described in Table 12-775.

Return to Summary Table.

Time Stamp Comparison Nudge Value Register.

Table 12-774 CPSW_CPTS_TS_COMP_NUDGE_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D02Ch

Figure 12-417 CPSW_CPTS_TS_COMP_NUDGE_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								NUDGE
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-775 CPSW_CPTS_TS_COMP_NUDGE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	NUDGE	R/W	0h	Time stamp Comparison Nudge Value. This two’s complement number is added to the CPSW_CPTS_TS_COMP_LEN_REG[31-0] TS_COMP_LENGTH value to increase or decrease the TS_COMP length by the CPSW_CPTS_TS_COMP_NUDGE_REG[7-0] NUDGE amount. Only a single high or low time is adjusted and the CPSW_CPTS_TS_COMP_NUDGE_REG value is cleared to zero when the nudge has occurred.

1.6.3.13 CPSW_CPTS_EVENT_POP_REG Register (Offset = 0003D030h) [reset = X]

CPSW_CPTS_EVENT_POP_REG is shown in Figure 12-418 and described in Table 12-777.

Return to Summary Table.

Event Interrupt Pop Register.

Table 12-776 CPSW_CPTS_EVENT_POP_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D030h

Figure 12-418 CPSW_CPTS_EVENT_POP_REG Register

31	30	29	28	27	26	25	24
RESERVED
W-X

23	22	21	20	19	18	17	16
RESERVED
W-X

15	14	13	12	11	10	9	8
RESERVED
W-X

7	6	5	4	3	2	1	0
RESERVED							EVENT_POP
W-X							W-0h

LEGEND: W = Write Only; -n = value after reset

Table 12-777 CPSW_CPTS_EVENT_POP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	W	X
0	EVENT_POP	W	0h	Event Pop. When a logic high is written to this bit an event is popped off the event FIFO. The event FIFO pop occurs as part of the interrupt process after the event has been read from the CPSW_CPTS_EVENT_0_REG to CPSW_CPTS_EVENT_3_REG registers. Popping an event discards the event and causes the next event, if any, to be moved to the top of the FIFO ready to be read by software on interrupt.

1.6.3.14 CPSW_CPTS_EVENT_0_REG Register (Offset = 0003D034h) [reset = 0h]

CPSW_CPTS_EVENT_0_REG is shown in Figure 12-419 and described in Table 12-779.

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Lower 32-bits of the Event Value Register.

Table 12-778 CPSW_CPTS_EVENT_0_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D034h

Figure 12-419 CPSW_CPTS_EVENT_0_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIME_STAMP
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-779 CPSW_CPTS_EVENT_0_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TIME_STAMP	R	0h	Time Stamp. The time stamp is valid for transmit, receive, and time stamp push event types. The time stamp value is not valid for counter roll event types.

1.6.3.15 CPSW_CPTS_EVENT_1_REG Register (Offset = 0003D038h) [reset = X]

CPSW_CPTS_EVENT_1_REG is shown in Figure 12-420 and described in Table 12-781.

Return to Summary Table.

Lower Middle 32-bits of the Event Value Register.

Table 12-780 CPSW_CPTS_EVENT_1_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D038h

Figure 12-420 CPSW_CPTS_EVENT_1_REG Register

31	30	29	28	27	26	25	24
RESERVED		PREMPT_QUEUE	PORT_NUMBER
R-X		R-0h	R-0h

23	22	21	20	19	18	17	16
EVENT_TYPE				MESSAGE_TYPE
R-0h				R-0h

15	14	13	12	11	10	9	8
SEQUENCE_ID
R-0h

7	6	5	4	3	2	1	0
SEQUENCE_ID
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-781 CPSW_CPTS_EVENT_1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	X
29	PREMPT_QUEUE	R	0h	Prempt QUEUE
28-24	PORT_NUMBER	R	0h	Port Number. Indicates the port number (encoded) of an Ethernet event or the encoded hardware time stamp number.
23-20	EVENT_TYPE	R	0h	Time Sync Event Type 0h = Time Stamp Push Event 1h = Time Stamp Rollover Event 2h = Time Stamp Half Rollover Event 3h = Hardware Time Stamp Push Event 4h = Ethernet Receive Event 5h = Ethernet Transmit Event 6h = Time Stamp Compare Event 7h = Host Transmit Event 8H to Fh = Reserved
19-16	MESSAGE_TYPE	R	0h	Message type. The message type value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events.
15-0	SEQUENCE_ID	R	0h	Sequence ID. The 16-bit sequence id is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events.

1.6.3.16 CPSW_CPTS_EVENT_2_REG Register (Offset = 0003D03Ch) [reset = X]

CPSW_CPTS_EVENT_2_REG is shown in Figure 12-421 and described in Table 12-783.

Return to Summary Table.

Upper Middle 32-bits of the Event Value Register.

Table 12-782 CPSW_CPTS_EVENT_2_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D03Ch

Figure 12-421 CPSW_CPTS_EVENT_2_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DOMAIN
R-X																								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-783 CPSW_CPTS_EVENT_2_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	X
7-0	DOMAIN	R	0h	Domain. The 8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events.

1.6.3.17 CPSW_CPTS_EVENT_3_REG Register (Offset = 0003D040h) [reset = 0h]

CPSW_CPTS_EVENT_3_REG is shown in Figure 12-422 and described in Table 12-785.

Return to Summary Table.

Upper 32-bits of the Event Value Register.

Table 12-784 CPSW_CPTS_EVENT_3_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D040h

Figure 12-422 CPSW_CPTS_EVENT_3_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIME_STAMP
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-785 CPSW_CPTS_EVENT_3_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TIME_STAMP	R	0h	Time Stamp. The time stamp upper 32-bits are valid for transmit, receive, and time stamp push event types. This value is zero in 32-bit mode.

1.6.3.18 CPSW_CPTS_TS_LOAD_HIGH_VAL_REG Register (Offset = 0003D044h) [reset = 0h]

CPSW_CPTS_TS_LOAD_HIGH_VAL_REG is shown in Figure 12-423 and described in Table 12-787.

Return to Summary Table.

Time Stamp Load High Value (upper 32-bits) Register

Table 12-786 CPSW_CPTS_TS_LOAD_HIGH_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D044h

Figure 12-423 CPSW_CPTS_TS_LOAD_HIGH_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_LOAD_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-787 CPSW_CPTS_TS_LOAD_HIGH_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TS_LOAD_VAL	R/W	0h	Time Stamp Load high Value. Writing the CPSW_CPTS_TS_LOAD_EN_REG[0] TS_LOAD_EN bit causes the value contained in this register to be written into the time stamp. The time stamp value is read by initiating a time stamp push event, not by reading this register. When reading this register, the value read is not the time stamp, but is the value that was last written to this register. This value is unused in 32-bit mode

1.6.3.19 CPSW_CPTS_TS_COMP_HIGH_VAL_REG Register (Offset = 0003D048h) [reset = 0h]

CPSW_CPTS_TS_COMP_HIGH_VAL_REG is shown in Figure 12-424 and described in Table 12-789.

Return to Summary Table.

Time Stamp Comparison High Value (upper 32-bits) Register.

Table 12-788 CPSW_CPTS_TS_COMP_HIGH_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D048h

Figure 12-424 CPSW_CPTS_TS_COMP_HIGH_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_COMP_HIGH_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-789 CPSW_CPTS_TS_COMP_HIGH_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TS_COMP_HIGH_VAL	R/W	0h	Time Stamp Comparison High Value. Writing a non-zero value to the CPSW_CPTS_TS_COMP_LEN_REG[31-0] TS_COMP_LENGTH register causes a pulse of TS_COMP_LENGTH RCLK periods on the TS_COMP output and a comparison event when the [31-0]TIME_STAMP counter value is equivalent to CPSW_CPTS_TS_COMP_VAL_REG[31-0] TS_COMP_VAL and CPSW_CPTS_TS_COMP_HIGH_VAL_REG[31-0] TS_COMP_HIGH_VAL. This value is unused in 32-bit mode. The upper 32-bits in CPSW_CPTS_TS_COMP_HIGH_VAL_REG register should be written before the lower 32-bits in the CPSW_CPTS_TS_COMP_VAL_REG register.

1.6.3.20 CPSW_CPTS_TS_ADD_VAL_REG Register (Offset = 0003D04Ch) [reset = X]

CPSW_CPTS_TS_ADD_VAL_REG is shown in Figure 12-425 and described in Table 12-791.

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TS Add Value Register.

Table 12-790 CPSW_CPTS_TS_ADD_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D04Ch

Figure 12-425 CPSW_CPTS_TS_ADD_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ADD_VAL
R/W-X													R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-791 CPSW_CPTS_TS_ADD_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2-0	ADD_VAL	R/W	0h	The ts_add_value[2:0] is added to 1 to comprise the time stamp increment value. The time stamp increment value is added to the current time stamp (time_stamp[63:0]) on each RCLK. The time stamp increment value can be adjusted by nudge and ppm also. The CPSW_CPTS_TS_ADD_VAL_REG[2-0] ADD_VAL value may be non-zero in 64-bit mode only.

1.6.3.21 CPSW_CPTS_TS_PPM_LOW_VAL_REG Register (Offset = 0003D050h) [reset = 0h]

CPSW_CPTS_TS_PPM_LOW_VAL_REG is shown in Figure 12-426 and described in Table 12-793.

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Time Stamp PPM Load Low Value (lower 32-bits) Register.

Table 12-792 CPSW_CPTS_TS_PPM_LOW_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D050h

Figure 12-426 CPSW_CPTS_TS_PPM_LOW_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_PPM_LOW_VAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-793 CPSW_CPTS_TS_PPM_LOW_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TS_PPM_LOW_VAL	R/W	0h	Time Stamp PPM Low Value. The 64-bit PPM value takes effect when this low value is written. The high value should be written first. Note: There should be at least 10 clocks in between writes to the low register to ensure that the previous operation has been seen.

1.6.3.22 CPSW_CPTS_TS_PPM_HIGH_VAL_REG Register (Offset = 0003D054h) [reset = X]

CPSW_CPTS_TS_PPM_HIGH_VAL_REG is shown in Figure 12-427 and described in Table 12-795.

Return to Summary Table.

Time Stamp PPM Load High Value (upper 32-bits) Register.

Table 12-794 CPSW_CPTS_TS_PPM_HIGH_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D054h

Figure 12-427 CPSW_CPTS_TS_PPM_HIGH_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TS_PPM_HIGH_VAL
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-795 CPSW_CPTS_TS_PPM_HIGH_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	TS_PPM_HIGH_VAL	R/W	0h	Time Stamp PPM High Value. This value should be written first (before the low value is written). The minimum value of the Time Stamp PPM is 0x400 (all 42 bits: CPSW_CPTS_TS_PPM_LOW_VAL_REG[31-0] TS_PPM_LOW_VAL and CPSW_CPTS_TS_PPM_HIGH_VAL_REG[9-0] TS_PPM_HIGH_VAL).

1.6.3.23 CPSW_CPTS_TS_NUDGE_VAL_REG Register (Offset = 0003D058h) [reset = X]

CPSW_CPTS_TS_NUDGE_VAL_REG is shown in Figure 12-428 and described in Table 12-797.

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Time Stamp Nudge Value Register.

Table 12-796 CPSW_CPTS_TS_NUDGE_VAL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D058h

Figure 12-428 CPSW_CPTS_TS_NUDGE_VAL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TS_NUDGE_VAL
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-797 CPSW_CPTS_TS_NUDGE_VAL_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

31-8

RESERVED

R/W

7-0

TS_NUDGE_VAL

R/W

Time stamp Nudge Value.
This two’s complement number is added to the CPSW_CPTS_EVENT_0_REG[31-0] TIME_STAMP and CPSW_CPTS_EVENT_3_REG[[31-0] TIME_STAMP value to increase or decrease the time stamp value by the CPSW_CPTS_TS_NUDGE_VAL_REG[7-0] TS_NUDGE_VAL amount. The TS_NUDGE_VAL value is cleared to zero when the nudge has occurred.

The minimum value of the Time Stamp PPM is 0x400 (all 42 bits: CPSW_CPTS_TS_PPM_LOW_VAL_REG[31-0] TS_PPM_LOW_VAL and CPSW_CPTS_TS_PPM_HIGH_VAL_REG[9-0] TS_PPM_HIGH_VAL).

1.6.3.24 CPSW_CPTS_TS_CONFIG Registers (Offset = 0003D0D0h)

Short Description: ts_config

Long Description: Time Stamp Configuration Read

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Table 12-798 Instance Table

Instance Name	Physical Address
CPSW0	0803 D0D0h

Figure 12-429 TS_CONFIG Name Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
NONE
0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVNT_FIFO_DEPTH								NUM_GENF
R								R
100000								10

Table 12-799 TS_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
	RESERVED	NONE		Reserved
15 - 8	EVNT_FIFO_DEPTH	R	20h	The Event FIFO Depth
7 - 0	NUM_GENF	R	2h	The number of CPTS GENF outputs

1.6.3.25 CPSW_GENF0_COMP_LOW_REG Register (Offset = 0003D0E0h) [reset = 0h]

CPSW_GENF0_COMP_LOW_REG is shown in Figure 12-430 and described in Table 12-801.

Return to Summary Table.

Time Stamp Generate Function (GENF0) Comparison Low Value (lower 32-bits).

Table 12-800 CPSW_GENF0_COMP_LOW_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0E0h

Figure 12-430 CPSW_GENF0_COMP_LOW_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP_LOW
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-801 CPSW_GENF0_COMP_LOW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	COMP_LOW	R/W	0h	Time Stamp Generate Function Comparison Low Value (lower 32-bits). This value should be written after the upper 32-bits. The CPSW_GENF0_COMP_HIGH_REG and CPSW_GENF0_COMP_LOW_REG should only be written when the CPSW_GENF0_LENGTH_REG[31-0] LENGTH value is zero.

1.6.3.26 CPSW_GENF0_COMP_HIGH_REG Register (Offset = 0003D0E4h) [reset = 0h]

CPSW_GENF0_COMP_HIGH_REG is shown in Figure 12-431 and described in Table 12-803.

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Time Stamp Generate Function (GENF0) Comparison high Value (upper 32-bits).

Table 12-802 CPSW_GENF0_COMP_HIGH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0E4h

Figure 12-431 CPSW_GENF0_COMP_HIGH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP_HIGH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-803 CPSW_GENF0_COMP_HIGH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	COMP_HIGH	R/W	0h	Time Stamp Generate Function Comparison High Value (upper 32-bits). This value should be written before the lower 32-bits. The CPSW_GENF0_COMP_HIGH_REG and CPSW_GENF0_COMP_LOW_REG should only be written when the CPSW_GENF0_LENGTH_REG[31-0] LENGTH value is zero.

1.6.3.27 CPSW_GENF0_CONTROL_REG Register (Offset = 0003D0E8h) [reset = X]

CPSW_GENF0_CONTROL_REG is shown in Figure 12-432 and described in Table 12-805.

Return to Summary Table.

Time Stamp Generate Function (GENF0) Control Registers.

Table 12-804 CPSW_GENF0_CONTROL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0E8h

Figure 12-432 CPSW_GENF0_CONTROL_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						PPM_DIR	POLARITY_INV
R/W-X						R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-805 CPSW_GENF0_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1	PPM_DIR	R/W	0h	Time Stamp Generate Function PPM Direction. 0h = A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1h = A single RCLK is subtracted from the generate function counter at the PPM rate which has the effect of increasing the generate function frequency by the PPM amount.
0	POLARITY_INV	R/W	0h	Time Stamp Generate Function Polarity Invert 0h = The output TS_GENFn signal asserts low 1h = The output TS_GENFn signal asserts high

1.6.3.28 CPSW_GENF0_LENGTH_REG Register (Offset = 0003D0ECh) [reset = 0h]

CPSW_GENF0_LENGTH_REG is shown in Figure 12-433 and described in Table 12-807.

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Time Stamp Generate Function (GENF0) Length Value.

Table 12-806 CPSW_GENF0_LENGTH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0ECh

Figure 12-433 CPSW_GENF0_LENGTH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LENGTH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-807 CPSW_GENF0_LENGTH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LENGTH	R/W	0h	Time Stamp Generate Function Length Value.

1.6.3.29 CPSW_GENF0_PPM_LOW_REG Register (Offset = 0003D0F0h) [reset = 0h]

CPSW_GENF0_PPM_LOW_REG is shown in Figure 12-434 and described in Table 12-809.

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Time Stamp Generate Function (GENF0) PPM Low Value (lower 32-bits).

Table 12-808 CPSW_GENF0_PPM_LOW_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0F0h

Figure 12-434 CPSW_GENF0_PPM_LOW_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PPM_LOW
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-809 CPSW_GENF0_PPM_LOW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PPM_LOW	R/W	0h	Time Stamp Generate Function PPM Low Value. The 64-bit PPM value takes effect when this low value is written. The high value should be written first.

1.6.3.30 CPSW_GENF0_PPM_HIGH_REG Register (Offset = 0003D0F4h) [reset = X]

CPSW_GENF0_PPM_HIGH_REG is shown in Figure 12-435 and described in Table 12-811.

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Time Stamp Generate Function (GENF0) PPM High Value (upper 32-bits).

Table 12-810 CPSW_GENF0_PPM_HIGH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0F4h

Figure 12-435 CPSW_GENF0_PPM_HIGH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						PPM_HIGH
R/W-X																						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-811 CPSW_GENF0_PPM_HIGH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	PPM_HIGH	R/W	0h	Time Stamp Generate Function PPM High Value. This value should be written first (before the low value is written).

1.6.3.31 CPSW_GENF0_NUDGE_REG Register (Offset = 0003D0F8h) [reset = X]

CPSW_GENF0_NUDGE_REG is shown in Figure 12-436 and described in Table 12-813.

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Time Stamp Generate Function (GENF0) Nudge Value Registers.

Table 12-812 CPSW_GENF0_NUDGE_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D0F8h

Figure 12-436 CPSW_GENF0_NUDGE_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								NUDGE
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-813 CPSW_GENF0_NUDGE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	NUDGE	R/W	0h	Time Stamp Generate Function Nudge Value. This two’s complement number is added to the generate counter value to increase or decrease the length by the CPSW_GENF0_NUDGE_REG[7-0] NUDGE amount. Only a single high or low time is adjusted and the CPSW_GENF0_NUDGE_REG value is cleared to zero when the nudge has occurred.

1.6.3.32 CPSW_GENF1_COMP_LOW_REG Register (Offset = 0003D100h) [reset = 0h]

CPSW_GENF1_COMP_LOW_REG is shown in Figure 12-437 and described in Table 12-815.

Return to Summary Table.

Time Stamp Generate Function (GENF1) Comparison Low Value.

Table 12-814 CPSW_GENF1_COMP_LOW_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D100h

Figure 12-437 CPSW_GENF1_COMP_LOW_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP_LOW
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-815 CPSW_GENF1_COMP_LOW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	COMP_LOW	R/W	0h	Time Stamp Generate Function (GENF1) Comparison Low Value (lower 32-bits). This value should be written after the upper 32-bits. The CPSW_GENF1_COMP_HIGH_REG and CPSW_GENF1_COMP_LOW_REG should only be written when the CPSW_GENF1_LENGTH_REG[31-0] LENGTH value is zero.

1.6.3.33 CPSW_GENF1_COMP_HIGH_REG Register (Offset = 0003D104h) [reset = 0h]

CPSW_GENF1_COMP_HIGH_REG is shown in Figure 12-438 and described in Table 12-817.

Return to Summary Table.

Time Stamp Generate Function (GENF1) Comparison high Value (upper 32-bits).

Table 12-816 CPSW_GENF1_COMP_HIGH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D104h

Figure 12-438 CPSW_GENF1_COMP_HIGH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP_HIGH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-817 CPSW_GENF1_COMP_HIGH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	COMP_HIGH	R/W	0h	Time Stamp Generate Function (GENF1) Comparison High Value (upper 32-bits). This value should be written before the lower 32-bits are written. The CPSW_GENF1_COMP_HIGH_REG and CPSW_GENF1_COMP_LOW_REG should only be written when the CPSW_GENF0_LENGTH_REG[31-0] LENGTH value is zero.

1.6.3.34 CPSW_GENF1_CONTROL_REG Register (Offset = 0003D108h) [reset = X]

CPSW_GENF1_CONTROL_REG is shown in Figure 12-439 and described in Table 12-819.

Return to Summary Table.

Time Stamp Generate Function (GENF1) Control Register.

Table 12-818 CPSW_GENF1_CONTROL_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D108h

Figure 12-439 CPSW_GENF1_CONTROL_REG Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						PPM_DIR	POLARITY_INV
R/W-X						R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-819 CPSW_GENF1_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1	PPM_DIR	R/W	0h	Time Stamp Generate Function (GENF1) PPM Direction. 0h = A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1h = A single RCLK is subtracted from the generate function counter at the PPM rate which has the effect of increasing the generate function frequency by the PPM amount.
0	POLARITY_INV	R/W	0h	Time Stamp Generate Function (GENF1) Polarity Invert. 0h = The output TS_GENFn signal asserts low 1h = The output TS_GENFn signal asserts high

1.6.3.35 CPSW_GENF1_LENGTH_REG Register (Offset = 0003D10Ch) [reset = 0h]

CPSW_GENF1_LENGTH_REG is shown in Figure 12-440 and described in Table 12-821.

Return to Summary Table.

Time Stamp Generate Function (GENF1) Length Value.

Table 12-820 CPSW_GENF1_LENGTH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D10Ch

Figure 12-440 CPSW_GENF1_LENGTH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LENGTH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-821 CPSW_GENF1_LENGTH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LENGTH	R/W	0h	Time Stamp Generate Function (GENF1) Length Value.

1.6.3.36 CPSW_GENF1_PPM_LOW_REG Register (Offset = 0003D110h) [reset = 0h]

CPSW_GENF1_PPM_LOW_REG is shown in Figure 12-441 and described in Table 12-823.

Return to Summary Table.

Time Stamp Generate Function (GENF1) PPM Low Value (lower 32-bits).

Table 12-822 CPSW_GENF1_PPM_LOW_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D110h

Figure 12-441 CPSW_GENF1_PPM_LOW_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PPM_LOW
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-823 CPSW_GENF1_PPM_LOW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PPM_LOW	R/W	0h	Time Stamp Generate Function (GENF1) PPM Low Value The 64-bit PPM value takes effect when this low value is written. The high value should be written first.

1.6.3.37 CPSW_GENF1_PPM_HIGH_REG Register (Offset = 0003D114h) [reset = X]

CPSW_GENF1_PPM_HIGH_REG is shown in Figure 12-442 and described in Table 12-825.

Return to Summary Table.

Time Stamp Generate Function (GENF1) PPM High Value (upper 32-bits).

Table 12-824 CPSW_GENF1_PPM_HIGH_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D114h

Figure 12-442 CPSW_GENF1_PPM_HIGH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						PPM_HIGH
R/W-X																						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-825 CPSW_GENF1_PPM_HIGH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	PPM_HIGH	R/W	0h	Time Stamp Generate Function (GENF1) PPM High Value. This value should be written first (before the low value is written).

1.6.3.38 CPSW_GENF1_NUDGE_REG Register (Offset = 0003D118h) [reset = X]

CPSW_GENF1_NUDGE_REG is shown in Figure 12-443 and described in Table 12-827.

Return to Summary Table.

Time Stamp Generate Function (GENF1) Nudge Value.

Table 12-826 CPSW_GENF1_NUDGE_REG Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D118h

Figure 12-443 CPSW_GENF1_NUDGE_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								NUDGE
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-827 CPSW_GENF1_NUDGE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	NUDGE	R/W	0h	Time Stamp Generate Function (GENF1) Nudge Value . This two’s complement number is added to the generate counter value to increase or decrease the length by the CPSW_GENF1_NUDGE_REG[7-0] NUDGE amount. Only a single high or low time is adjusted and the CPSW_GENF1_NUDGE_REG value is cleared to zero when the nudge has occurred.

1.6.3.39 CPSW_ESTF_COMP_LOW_REG_l Register (Offset = 0003D200h + formula) [reset = 0h]

CPSW_ESTF_COMP_LOW_REG_l is shown in Figure 12-444 and described in Table 12-829.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) Comparison Low Value.

Offset = 0003D200h + (l * 20h); where l = 0h to 1h.

Table 12-828 CPSW_ESTF_COMP_LOW_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D200h + formula

Figure 12-444 CPSW_ESTF_COMP_LOW_REG_l Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP_LOW
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-829 CPSW_ESTF_COMP_LOW_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	COMP_LOW	R/W	0h	Time Stamp Generate Function (ESTFn, where n = 1 to 2) Comparison Low Value (lower 32-bits). This value should be written after the upper 32-bits. The CPSW_ESTF_COMP_HIGH_REG_l and CPSW_ESTF_COMP_LOW_REG_l should only be written when the CPSW_ESTF_LENGTH_REG_l[31-0] LENGTH value is zero.

1.6.3.40 CPSW_ESTF_COMP_HIGH_REG_l Register (Offset = 0003D204h + formula) [reset = 0h]

CPSW_ESTF_COMP_HIGH_REG_l is shown in Figure 12-445 and described in Table 12-831.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) Comparison high Value (upper 32-bits).

Offset = 0003D204h + (l * 20h); where l = 0h to 1h.

Table 12-830 CPSW_ESTF_COMP_HIGH_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D204h + formula

Figure 12-445 CPSW_ESTF_COMP_HIGH_REG_l Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP_HIGH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-831 CPSW_ESTF_COMP_HIGH_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	COMP_HIGH	R/W	0h	Time Stamp Generate Function (ESTFn, where n = 1 to 2) Comparison High Value (upper 32-bits). This value should be written before the lower 32-bits are written. The CPSW_ESTF_COMP_HIGH_REG_l and CPSW_ESTF_COMP_LOW_REG_l should only be written when the CPSW_ESTF_LENGTH_REG_l[31-0] LENGTH value is zero.

1.6.3.41 CPSW_ESTF_CONTROL_REG_l Register (Offset = 0003D208h + formula) [reset = X]

CPSW_ESTF_CONTROL_REG_l is shown in Figure 12-446 and described in Table 12-833.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) Control Register.

Offset = 0003D208h + (l * 20h); where l = 0h to 1h.

Table 12-832 CPSW_ESTF_CONTROL_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D208h + formula

Figure 12-446 CPSW_ESTF_CONTROL_REG_l Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						POLARITY_INV	PPM_DIR
R/W-X						R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-833 CPSW_ESTF_CONTROL_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R/W	X
1	POLARITY_INV	R/W	0h	Time Stamp Generate Function (ESTFn, where n = 1 to 2) Polarity Invert. 0h = The output TS_ESTFn signal asserts low 1h = The output TS_ESTFn signal asserts high
0	PPM_DIR	R/W	0h	Time Stamp Generate Function (ESTFn, where n = 1 to 2) PPM Direction. 0h = A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1h = A single RCLK is subtracted from the generate function counter at the PPM rate which has the effect of increasing the generate function frequency by the PPM amount.

1.6.3.42 CPSW_ESTF_LENGTH_REG_l Register (Offset = 0003D20Ch + formula) [reset = 0h]

CPSW_ESTF_LENGTH_REG_l is shown in Figure 12-447 and described in Table 12-835.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) Length Value.

Offset = 0003D20Ch + (l * 20h); where l = 0h to 1h.

Table 12-834 CPSW_ESTF_LENGTH_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D20Ch + formula

Figure 12-447 CPSW_ESTF_LENGTH_REG_l Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LENGTH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-835 CPSW_ESTF_LENGTH_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LENGTH	R/W	0h	Time Stamp ESTFn (n = 1 to 2) Generate Function Length Value.

1.6.3.43 CPSW_ESTF_PPM_LOW_REG_l Register (Offset = 0003D210h + formula) [reset = 0h]

CPSW_ESTF_PPM_LOW_REG_l is shown in Figure 12-448 and described in Table 12-837.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) PPM Low Value (lower 32-bits).

Offset = 0003D210h + (l * 20h); where l = 0h to 1h.

Table 12-836 CPSW_ESTF_PPM_LOW_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D210h + formula

Figure 12-448 CPSW_ESTF_PPM_LOW_REG_l Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PPM_LOW
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-837 CPSW_ESTF_PPM_LOW_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PPM_LOW	R/W	0h	Time Stamp ESTFn (n = 1 to 2) Generate Function PPM Low Value. The 64-bit PPM value takes effect when this low value is written. The high value should be written first.

1.6.3.44 CPSW_ESTF_PPM_HIGH_REG_l Register (Offset = 0003D214h + formula) [reset = X]

CPSW_ESTF_PPM_HIGH_REG_l is shown in Figure 12-449 and described in Table 12-839.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) PPM High Value (upper 32-bits).

Offset = 0003D214h + (l * 20h); where l = 0h to 1h.

Table 12-838 CPSW_ESTF_PPM_HIGH_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D214h + formula

Figure 12-449 CPSW_ESTF_PPM_HIGH_REG_l Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						PPM_HIGH
R/W-X																						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-839 CPSW_ESTF_PPM_HIGH_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	PPM_HIGH	R/W	0h	Time Stamp ESTFn (n = 1 to 2) Generate Function PPM High Value. This value should be written first (before the low value is written).

1.6.3.45 CPSW_ESTF_NUDGE_REG_l Register (Offset = 0003D218h + formula) [reset = X]

CPSW_ESTF_NUDGE_REG_l is shown in Figure 12-450 and described in Table 12-841.

Return to Summary Table.

Time Stamp Generate Function (ESTFn, where n = 1 to 2) Nudge Value.

Offset = 0003D218h + (l * 20h); where l = 0h to 1h.

Table 12-840 CPSW_ESTF_NUDGE_REG_l Instances

Instance	Physical Address
CPSW0_NUSS_CPTS	0803 D218h + formula

Figure 12-450 CPSW_ESTF_NUDGE_REG_l Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								NUDGE
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-841 CPSW_ESTF_NUDGE_REG_l Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	NUDGE	R/W	0h	Time Stamp ESTFn (n = 1 to 2) Generate Function Nudge Value. This two’s complement number is added to the generate counter value to increase or decrease the length by the CPSW_ESTF_NUDGE_REG_l[7-0] NUDGE amount. Only a single high or low time is adjusted and the CPSW_ESTF_NUDGE_REG_l value is cleared to zero when the nudge has occurred.