SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 3-7 through Table 3-9 summarize the integration of CBASS0 in device MAIN/MCU domain.
Module Instance | Attributes | |||
---|---|---|---|---|
Power Sleep Controller | Power Domain | Module Domain | ||
CBASS0 CBASS_INFRA1 |
PSC0 | PD0 | LPSC0 | |
MCU_CBASS0 | MCU_PSC0 | PD0 | LPSC0 |
Clocks | |||
---|---|---|---|
Module Instance | Source Clock Signal | Source | Description |
CBASS0 CBASS_INFRA1 |
MAIN_SYSCLK0/2 | PLLCTRL0 | CBASS0 and CBASS_INFRA1 clocks |
MAIN_SYSCLK0/4 | PLLCTRL0 | ||
MCU_CBASS0 | MCU_SYSCLK0/2 | MCU_PLLCTRL0 | MCU_CBASS0 clocks |
MCU_SYSCLK0/4 | MCU_PLLCTRL0 | ||
Resets | |||
Module Instance | Source Reset Signal | Source | Description |
CBASS0 | MOD_G_RST | LPSC0 | CBASS0 reset |
CBASS_INFRA1 | MOD_G_RST | LPSC2 | CBASS_INFRA1 reset |
MCU_CBASS0 | ROD_G_RST | LPSC0 | MCU_CBASS0 reset |
Interrupt Requests | |||||
---|---|---|---|---|---|
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
CBASS0 | CBASS0_default_exp_0 | DMSC0_CORTEX_M3_0_sec_in_IN_0 | DMSC0_CORTEX_M3_0 | CBASS0 interrupt request | level |
CBASS_FW0 | CBASS_FW0_default_err_intr_0 | DMSC0_CORTEX_M3_0_nvic_IN_202 | DMSC0_CORTEX_M3_0 | CBASS_FW0 interrupt request | level |
CBASS_INFRA1 | CBASS_INFRA1_default_exp_0 | DMSC0_CORTEX_M3_0_sec_in_IN_1 | DMSC0_CORTEX_M3_0 | CBASS_INFRA1 interrupt request | level |
MCU_CBASS0 | MCU_CBASS0_default_err_intr_0 | MCU_M4FSS0_CORE0_nvic_IN_31 | MCU_M4FSS0_CORE0 | MCU_CBASS0 interrupt request | level |
CBASS0CBASS_DBG0CBASS_INFRA1MCU_CBASS0 | CBASS0_default_err_intr_0(1)CBASS_DBG0_default_err_intr_0(1)CBASS_INFRA1_default_err_intr_0(1)MCU_CBASS0_default_err_intr_0(1) | GICSS0_spi_IN_133 | GICSS0 | CBASS0 interrupt request | level |
R5FSS0_CORE0_intr_IN_133 | R5FSS0_CORE0 | CBASS0 interrupt request | level | ||
R5FSS0_CORE1_intr_IN_133 | R5FSS0_CORE1 | CBASS0 interrupt request | level | ||
R5FSS1_CORE0_intr_IN_133 | R5FSS1_CORE0 | CBASS0 interrupt request | level | ||
R5FSS1_CORE1_intr_IN_133 | R5FSS1_CORE1 | CBASS0 interrupt request | level |
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.