If the associated CPU has the vector (VIC) interface enabled, then the following method is used for servicing IRQs:
- Hardware handshake
- CPU asserts coreN_IRQACK high
- VIM asserts coreN_IRQADDRV to indicate that the coreN_IRQADDR bus is stable with the correct vector address
- CPU reads coreN_IRQADDR, jumps to that address, and de-asserts coreN_IRQACK low
- VIM de-asserts coreN_IRQn and coreN_IRQADDRV, VIM masks (discards) all IRQs with the same or lower priority
- VIM loads the value from the R5FSS_VIM_PRIIRQ[9:0] NUM bit field (which corresponds to the vector address) into the R5FSS_VIM_ACTIRQ[9:0] NUM bit field, which causes the R5FSS_VIM_ACTIRQ[31] VALID bit to be set
- Service the interrupt
- Depending on whether the original source of the interrupt was a pulse or a level (determined by reading the R5FSS_VIM_ACTIRQ[9:0] NUM bit field to determine number, and reading the appropriate bit in the R5FSS_VIM_INTTYPE_j register to determine type)
- Pulse
- Clear the status by writing a '1' to the appropriate bit in the R5FSS_VIM_IRQSTS_j register, or R5FSS_VIM_STS_j register
- Clear the interrupt at the source. This way, the source can generate another pulse, if it needs to, and the VIM will process this as a new interrupt
- Level
- Clear the interrupt at the source
- Clear the status by writing a '1' to the appropriate bit in the R5FSS_VIM_IRQSTS_j register, or R5FSS_VIM_STS_j register. This way, the level should be gone at the input to the VIM, it will avoid falsely re-calling the interrupt. If the source maintains the level, then it means there is another interrupt
- Write any value to the R5FSS_VIM_IRQVEC register
- This will clear the priority mask and will cause all interrupts to be re-evaluated for the new highest priority interrupt
- This will also clear the R5FSS_VIM_ACTIRQ[31] VALID bit