SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

6.4.12.3 PRU_ICSSG MII MDIO Receive/Transmit Frame Host Software Interface

To facilitate transmission and reception of serial management frames, the host has to perform the following operations:

Configure the [20] PREAMBLE and [15-0] CLKDIV fields in the MDIO MDIO_CONTROL_REG register.
Enable the MDIO module by setting the [30] ENABLE bit in the MDIO MDIO_CONTROL_REG register. If Byte access is being used, the [30] ENABLE bit should be written last.
The MDIO MDIO_ALIVE_REG register can be read after a delay to determine which Ethernet PHYs responded.
Set up the appropriate PHY addresses in the MDIO MDIO_USER_PHY_SEL_REG_j[4-0] PHYADR_MON bits.
Set up the appropriate [6] LINKINT_ENABLE bit in the MDIO MDIO_USER_PHY_SEL_REG_j registers.
Set up the appropriate [7] LINKSEL bits in the MDIO MDIO_USER_PHY_SEL_REG_j registers.
Set up the appropriate [1-0] USERINTMASKEDSET field in the MDIO MDIO_USER_INT_MASK_SET_REG register.
To write to an Ethernet PHY register the host should first check to ensure that the [31] GO bit in a MDIO MDIO_USER_ACCESS_REG_j registers is cleared. The [31] GO, [30] WRITE, [25-21] REGADR, [20-16] PHYADR and data fields in that MDIO MDIO_USER_ACCESS_REG_j registers can then be updated to the appropriate value. If byte access is being used, the [31] GO bit should be written last. The write operation to the PHY will be scheduled and completed by the module. Completion of the write operation can be determined by examining the [31] GO bit in the MDIO MDIO_USER_ACCESS_REG_j registers. It also results in a transition on the appropriate MDIO_INT signal and the corresponding bit in the MDIO MDIO_USER_INT_MASKED_REG register based on the setting of the MDIO MDIO_USER_INT_MASK_SET_REG register.
To read from an Ethernet PHY register the host should first check to ensure that the [31] GO bit in a MDIO MDIO_USER_ACCESS_REG_j registers is cleared. The [31] GO, [25-21] REGADR, and [20-16] PHYADR fields in that MDIO MDIO_USER_ACCESS_REG_j registers can then be updated to the appropriate value. The read data value will be available in the [15-0] DATA field of the MDIO MDIO_USER_ACCESS_REG_j registers after the module completes the read operation on the serial bus. The completion of the read operation can be determined by examining the [31] GO and [29] ACK bits in the MDIO MDIO_USER_ACCESS_REG_j registers. It also results in a transition on the appropriate MDIO_INT signal and the corresponding bit in the MDIO MDIO_USER_INT_MASKED_REG register based on the setting of the MDIO MDIO_USER_INT_MASK_SET_REG register.
The module de-asserts the MDIO_USERINT signal when the host writes to the appropriate [1-0] USERINTMASKED bit field in the MDIO MDIO_USER_INT_MASKED_REG register or the [1-0] USERINTRAW bit field in the MDIO MDIO_USER_INT_RAW_REG register.
The host can poll the MDIO MDIO_LINK_REG register periodically or use the MDIO_LINKINT signals to determine the state of the serial interface to a particular Ethernet PHY.
The module de-asserts the MDIO_LINKINT when the host writes to the appropriate [1-0] LINKINTRAW bit field in the MDIO_MDIO LINK_INT_RAW_REG register or the [1-0] LINKINTMASKED bit field in the MDIO_MDIO LINK_INT_MASKED_REG register.

Table 6-496 Summary of the PRU_ICSSG MII MDIO Functional Registers

Address Offset	Register Mnemonic	Register Name	Register Purpose
00h	MDIOVer	MDIO_MDIO_VERSION_REG	Module version register
04h	MDIOControl	MDIO_CONTROL_REG	Module control register
08h	MDIOAlive	MDIO_ALIVE_REG	Ethernet PHY acknowledge status register
0Ch	MDIOLink	MDIO_LINK_REG	Ethernet PHY link status register
10h	MDIOLinkIntRaw	MDIO_LINK_INT_RAW_REG	Link status change interrupt register (raw value)
14h	MDIOLinkIntMasked	MDIO_LINK_INT_MASKED_REG	Link status change interrupt register (masked value)
18h	MDIOLinkIntMaskSet	MDIO_LINK_INT_MASK_SET_REG	Link status change interrupt mask set register
1Ch	MDIOLinkIntMaskClr	MDIO_LINK_INT_MASK_CLEAR_REG	Link status change interrupt mask clear register
20h	MDIOUserIntRaw	MDIO_USER_INT_RAW_REG	User command complete interrupt register (raw value)
24h	MDIOUserIntMasked	MDIO_USER_INT_MASKED_REG	User command complete interrupt register (masked value)
28h	MDIOUserIntMaskSet	MDIO_USER_INT_MASK_SET_REG	User interrupt mask set register
2Ch	MDIOUserIntMaskClr	MDIO_USER_INT_MASK_CLEAR_REG	User interrupt mask clear register
30h	MDIOManual_IF	MDIO_MANUAL_IF_REG	Manual interface register
34h	MDIOPoll_IPG	MDIO_POLL_REG	Poll and IPG register
38h	MDIOPoll_En	MDIO_POLL_EN_REG	Poll Enable register
3Ch	MDIOClause	MDIO_CLAUS45_REG	Clause 22 or 45 enable register
40h	MDIOUser_Addr0	MDIO_USER_ADDR0_REG	User Address register 0
44h	MDIOUser_Addr1	MDIO_USER_ADDR1_REG	User Address register 1
48h – 7Ch	Reserved	-	Reserved
80h	MDIOUserAccess0	MDIO_USER_ACCESS_REG_0	User access register 0
84h	MDIOUserPhySel0	MDIO_USER_PHY_SEL_REG_0	User PHY select register 0
88h	MDIOUserAccess1	MDIO_USER_ACCESS_REG_1	User access register 1
8Ch	MDIOUserPhySel1	MDIO_USER_PHY_SEL_REG_1	User PHY select register 1
90h – FFh	Reserved	-	Reserved