SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

4.5.2.2.3.6.4.3 TX - Continuous FIFO Loading

Follow these steps to configure the Peripheral I/F channel(s) for a continuous loading transmission:

(Optional) Configure TX FIFO for MSB (default) or LSB:
1. ICSSG_PRU0_ED_CHm_CFG0_REG[31] PRU0_ED_TX_FIFO_SWAP_BITSm
Pre-load TX FIFO:
1. Select TX channel by writing the desired channel number to r30[17-16] (tx_ch_sel)
2. Write 1-4 bytes of data to r30[7-0] (tx_data). At each r30[7-0] write, data will be pushed into the FIFO.
3. Repeat Steps 2a and 2b for all desired channels.
Configure TX frame size to continuously transmit the TX FIFO until empty:
1. Set ICSSG_PRU0_ED_CHm_CFG0_REG[15-11] PRU0_ED_TX_FRAME_SIZEm = 0h
Push TX FIFO data to PERIF<m>_OUT (see Section 4.5.2.2.3.6.3.2 for the PERIF<m>_CLK and PERIF<m>_OUT start time relationship):
1. To start TX on all channels, set r31[20] = 1 (tx_global_go).
2. To start TX on individual channel:
  1. Select TX channel by writing the desired channel number to r30[17-16] (tx_ch_sel)
  2. Set r31[18] = 1 (tx_channel_go)
Monitor line rate and reload FIFO:
1. Polling r31[20-18, 12-10, 4-2] (tx_fifo_sts<m>)
2. When FIFO level is at 2 bytes, load next 2 bytes of data (see Step 2). Do not let the FIFO get close to 0. Once the FIFO runs empty, the hardware will assume the PRU has reached end of the last transmit. Any new writes to the FIFO will NOT be sent until the software sends another tx_channel_go bit. Note: There are also underrun and overrun error flags that can be monitored.
To end TX operation, do not send any new data to FIFO.
1. If ICSSG_PRU0_ED_CHm_CFG1_REG[31-16] PRU0_ED_RX_EN_COUNTERm > 0 (where n = 0 or 1 and m = 0 to 2), then the channel will automatically switch into RX mode. See Section 4.5.2.2.3.6.4.4 for an example of how to program and configure RX content.
2. If ICSSG_PRU0_ED_CHm_CFG1_REG[31-16] PRU0_ED_RX_EN_COUNTERm = 0, poll either r31[21, 13, or 5] (tx_global_reinit_active/busy[2,1,0]) or ICSSG_PRU0_ED_TX_CFG_REG[7, 6, or 5] PRU0_ED_BUSY_m (where m = 0 to 2, indicates channel number) for when TX is complete

Note:

The PERIF<m>_CLK Peripheral I/F requires that PERIF<m>_CLK be in a high state at the beginning of a new transaction. If the clock ended the continuous loading transmission in low state, then the clock needs to be reset before sending more data. The steps to reset PERIF<m>_CLK are:

Set R31[19] = 1 (tx_global_reinit) to reset clock high
Wait until PRU0_ED_BUSY_m is cleared
Re-configure R30[20-19] (clk_mode), since reinit will reset the clk_mode to "Free-running/stop-high" mode