This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.
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Below are some direct links to additional documentation:
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This chapter introduces the features, subsystems, and architecture of the AM64x/AM243xSitara Processor Platform high-performance System-on-Chip (SoC).
This document describes the Superset architecture, processors and peripherals of the AM64x and AM243x Family of SoCs, which are part of the Sitara Processors Multicore SoC architecture platform. Not all features are available on each family of devices. The superset AM6442x and AM2434x devices are available for preproduction software development. Software should constrain the features used to match the intended production device. For more information on the specific features, processors and peripherals available on a particular device, refer to the Device Comparison table in the corresponding device-specific Data sheet.
The AM64x and AM2434x Sitara Processor Platforms are hereinafter commonly referred to as AM64x, AM243x, platform, device, or SoC.
This section gives overview
Below are some direct links to additional documentation:
Figure 1-1 is functional block diagram for the device.
Module Full Name | Module Abbreviation | Device Domain | |
---|---|---|---|
MCU | MAIN | ||
Dual-Core Arm Cortex A53 Subsystem | A53SS | - | 1 |
Dual-Core Arm Cortex-R5F Subsystem | R5FSS | - | 2 |
Arm Cortex-M4F Subsystem | M4FSS | 1 | - |
Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit | PRU_ICSSG | - | 2 |
Device Management and Security Controller | DMSC-L | - | 1 |
Interprocessor Communication - Mailbox | Mailbox | - | 1 |
Interprocessor Communication - Spinlock | Spinlock | - | 1 |
Dual Data Rate Random Access Memory (16-Bit) Subsystem | DDRSS | - | 1 |
Region-based Address Translation | RAT | - | 1 |
Data Movement Subsystem | DMSS | - | 1 |
Peripheral DMA | PDMA | - | 2 |
Common Platform Time Sync Module | CPTS | - | 1 |
Timer Manager Module | TIMERMANAGER | - | 1 |
Analog to Digital Converter | ADC | - | 1 |
General Purpose Input/Output | GPIO | 1 | 2 |
Inter-Integrated Circuit | I2C | 2 | 4 |
Multi-channel Serial Peripheral Interface | MCSPI | 2 | 5 |
Universal Asynchronous Receiver/Transmitter | UART | 2 | 7 |
2 Port Gigabit Ethernet Switch | CPSW3G | - | 1 |
Peripheral Component Interconnect Express | PCIE | - | 1 |
Serializer/Deserializer (1-Lane) | SERDES | - | 1 |
Universal Serial Bus Subsystem | USB | - | 1 |
Enhanced Pulse Width Modulation Module | EPWM | - | 9 |
Enhanced Quadrature Encoder Pulse Module | EQEP | - | 3 |
Enhanced Capture Module | ECAP | - | 3 |
Fast Serial Interface Transmitter | FSI_TX | - | 2 |
Fast Serial Interface Reciever | FSI_RX | - | 6 |
Controller Area Network Interface | MCAN | - | 2 |
Flast Memory Subsystem | FSS | - | 1 |
Octal Serial Peripheral Interface | OSPI | - | 1 |
General Purpose Memory Controller | GPMC | - | 1 |
Error Location Module | ELM | - | 1 |
Multi-Media Card/Secure Digital Interface | MMCSD | - | 2 |
Global Time Counter | GTC | - | 1 |
Real Time Interrupt/Windowed WatchDog Timer | RTI/WWDT | 1 | 6 |
Dual-Mode Timer | TIMER | 4 | 12 |
Dual Clock Comparator | DCC | 1 | 6 |
Error Signaling Module | ESM | 1 | 1 |
Memory Cyclic Redundancy Check Controller | MCRC | 1 | - |
This section describes the modules integrated in the device MAIN domain.
The integrated 64-bit Arm Cortex-A53 subsystem (A53SS) supports the following main features: