SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

5.4.6.1 PLLCTRL0 Registers

Table 5-996 lists the PLLCTRL0 registers. All register offset addresses not listed in Table 5-996 should be considered as reserved locations and the register contents should not be modified.

Table 5-995 PLLCTRL0 Instances

Instance	Base Address
PLLCTRL0	0041 0000h
MCU_PLLCTRL0	4020 0000h

Table 5-996 PLLCTRL0 Registers

Offset	Acronym	Register Name	PLLCTRL0 Physical Address	MCU_PLLCTRL0 Physical Address
0h	PID	Peripheral identification register	0041 0000h	4020 0000h
100h	PLLCTL	PLL control register	0041 0100h	4020 0100h
118h	PLLDIV1	PLL controller divider1 control register	0041 0118h	4020 0118h
11Ch	PLLDIV2	PLL controller divider2 control register	0041 011Ch	4020 011Ch
138h	PLLCMD	PLL Controller command register	0041 0138h	4020 0138h
13Ch	PLLSTAT	PLL Controller status register	0041 013Ch	4020 013Ch
140h	ALNCTL	PLL Controller clock align control register	0041 0140h	4020 0140h
144h	DCHANGE	PLLDIV ratio change register	0041 0144h	4020 0144h

4.6.1.1 PID Register (Offset = 0h) [reset = 44815C00h]

PID is shown in Figure 5-499 and described in Table 5-998.

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Peripheral identification register

Table 5-997 PID Instances

Instance	Physical Address
PLLCTRL0	0041 0000h
MCU_PLLCTRL0	4020 0000h

Figure 5-499 PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SCHEME		BU		FUNC
R-1h		R-0h		R-481h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTL					MAJOR			CUSTOM		MINOR
R-Bh					R-4h			R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-998 PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	Peripheral identification register scheme
29-28	BU	R	0h	Business Unit
27-16	FUNC	R	481h	Module ID
15-11	RTL	R	Bh	RTL revision. Will vary depending on release
10-8	MAJOR	R	4h	Major revision
7-6	CUSTOM	R	0h	Custom
5-0	MINOR	R	0h	Minor revision

4.6.1.2 PLLCTL Register (Offset = 100h) [reset = X]

PLLCTL is shown in Figure 5-500 and described in Table 5-1000.

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PLL control register

Table 5-999 PLLCTL Instances

Instance	Physical Address
PLLCTRL0	0041 0100h
MCU_PLLCTRL0	4020 0100h

Figure 5-500 PLLCTL Register

31	30	29	28	27	26	25	24
RSVD2
R/W-0h

23	22	21	20	19	18	17	16
RSVD2
R/W-0h

15	14	13	12	11	10	9	8
RSVD2						EXCLKSRC	CLKMODE
R/W-0h						R/W-0h	R/W-X

7	6	5	4	3	2	1	0
PLLSELB	RSVD1	PLLENSRC	PLLDIS	PLLRST	RSVD	PLLPWRDN	PLLEN
R/W-0h	R/W-0h	R/W-1h	R/W-X	R/W-X	R/W-0h	R/W-1h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1000 PLLCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RSVD2	R/W	0h	Reserved
9	EXCLKSRC	R/W	0h	Selects between using bypass clock or an external clock source. 0 = bypass clock 1 = external clock source
8	CLKMODE	R/W	X	Reference Clock Selection. 1 = clkin_pi is the reference clock 0 = oscin_pi is the reference clock This bit is only applicable when d_clkmodesrc_pi = 1. It is otherwise don't care.
7	PLLSELB	R/W	0h	Selects PLL A versus PLL B. 1 = PLL B is selected. PLL A is put in power down (pll_a_pwrdn_po = 1) 0 = PLL A is selected. PLL B is put in power down. (pll_b_pwrdn_po = 1)
6	RSVD1	R/W	0h	Reserved
5	PLLENSRC	R/W	1h	PLLEN Mux Control Source 1 = PLLEN Mux is controlled by input pllen_pi. PLLCTL.PLLEN is don't care 0 = PLLEN Mux is controlled by PLLCTL.PLLEN. pllen_pi is don't care
4	PLLDIS	R/W	X	Asserts DISABLE to PLL if Supported 1 = PLL Controller output pll_disable_po = 1. 0 = PLL Controller output pll_disable_po = 0. Chip team must pay attention to the disable signal polarity of the PLL they use. Some PLLs may require PLLDIS = 1 to disable PLL, some PLLs require PLLDIS = 0 to disable PLL. Note that PLL Controller only supports one pll_disable_po output for both PLLA and PLLB. This is possible because the non-selected PLL is already placed in power down mode.
3	PLLRST	R/W	X	Asserts RESET to PLL if Supported. Controls output pll_reset_po. 1 = PLL Controller output pll_reset_po = 1. 0 = PLL Controller output pll_reset_po = 0. Chip team must pay attention to the reset signal polarity of the PLL they use. Some PLLs require PLLRST = 1 to reset the PLL. Some PLLs require PLLRST = 0 to reset the PLL. Note that PLL Controller only supports one pll_reset_po output for both PLLA and PLLB. This is possible because the non-selected PLL is already placed in power down mode.
2	RSVD	R/W	0h	Reserved
1	PLLPWRDN	R/W	1h	Selects PLL Power Down for the PLL selected by PLLSELB. The PLL not selected by PLLSELB is NOT controlled by PLLPWRDN bit. The not-selected PLL will stay in power down regardless of PLLPWRDN value. 0 = Selected PLL Operational. If PLLSELB = 0 (PLLA selected), PLL controller output pll_a_pwrdn_po is deasserted low. If PLLSELB = 1 (PLLB selected), PLL controller output pll_b_pwrdn_po is deasserted low. 1 = Selected PLL Placed In Power Down State. If PLLSELB = 0 (PLLA selected), PLL controller outputs pll_a_pwrdn_po is asserted high. If PLLSELB = 1 (PLLB selected), pll_b_pwrdn_po is asserted
0	PLLEN	R/W	0h	PLL Mode Enable This bit controls the multiplexer before the SYSCLK dividers D1 to Dn. 0 = Bypass Mode PreDiv, PLL, and PostDiv are bypassed. SYSCLK divided down directly from input reference clock refclk. 1 = PLL Mode PLL is used. SYSCLK divided down from PostDiv output

4.6.1.3 PLLDIV1 Register (Offset = 118h) [reset = X]

PLLDIV1 is shown in Figure 5-501 and described in Table 5-1002.

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PLL controller divider1 control register

Table 5-1001 PLLDIV1 Instances

Instance	Physical Address
PLLCTRL0	0041 0118h
MCU_PLLCTRL0	4020 0118h

Figure 5-501 PLLDIV1 Register

31	30	29	28	27	26	25	24
RSVD1
R/W-0h

23	22	21	20	19	18	17	16
RSVD1
R/W-0h

15	14	13	12	11	10	9	8
DN_EN	HALF_RATIO	RSVD
R/W-X	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RATIO
R/W-X

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1002 PLLDIV1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RSVD1	R/W	0h	Reserved
15	DN_EN	R/W	X	Divider Dn Enable 0 = Divider n Disabled. SYSCLKn is also gated before and after divider Dn. 1 = Divider n Enabled
14	HALF_RATIO	R/W	0h	Ratio is in half steps. Example 1: if RATIO = 00000 and HALFRATIO = 1 the divider will be /1.5. Example 2: RATIO = 10111 and HALFRATIO = 1 divider will be /24.5. Example 3: if RATIO = 00011 and HALFRATIO = 0 divider will be /4. THE HALF RATIO DIVIDER IS NOT A 50% DUTY CYCLE. It is a single 1x high clock pulse followed by low time until ratio is met. Note: To enable half step ratio dividers user must also set the associated bit in the PLLHDIVEN register PRIOR to writing the PLLDIVn register. If PLLHDIVEN register is not enabled then HALF_RATIO will not be writable. Changing the PLLHDIVEN register, set or clear, will not set or clear the HALF_RATIO bit in PLLDIVn register. This is to protect and enable backward compatible software in the chance it accidentally wrote this bit field.
13-8	RSVD	R/W	0h	Reserved
7-0	RATIO	R/W	X	Divider Dn Ratio (SYSCLKn divider) 00000 = /1 00001 = /2 00010 = /3 00011 = /4 00100 = /5 00101 = /6 00110 = /7 00111 = /8 01000 = /9 01001 = /10 01010 = /11 01011 = /12 01100 = /13 01101 = /14 01110 = /15 01111 = /16 10000 = /17 10001 = /18 10010 = /19 10011 = /20 10100 = /21 10101 = /22 10110 = /23 10111 = /24 11000 = /25 11001 = /26 11010 = /27 11011 = /28 11100 = /29 11101 = /30 11110 = /31 11111 = /32 Note that the actual PLLDIVx divide ratio will not be modified when this field is written to. User must also set the GOSET bit so that the SYSCLKs selected in ALNCTL can change their RATIOs to the new values and remain phase-aligned. Note: see HALF_RATIO bit.

4.6.1.4 PLLDIV2 Register (Offset = 11Ch) [reset = X]

PLLDIV2 is shown in Figure 5-502 and described in Table 5-1004.

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PLL controller divider2 control register

Table 5-1003 PLLDIV2 Instances

Instance	Physical Address
PLLCTRL0	0041 011Ch
MCU_PLLCTRL0	4020 011Ch

Figure 5-502 PLLDIV2 Register

31	30	29	28	27	26	25	24
RSVD1
R/W-0h

23	22	21	20	19	18	17	16
RSVD1
R/W-0h

15	14	13	12	11	10	9	8
DN_EN	HALF_RATIO	RSVD
R/W-X	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RATIO
R/W-X

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1004 PLLDIV2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RSVD1	R/W	0h	Reserved
15	DN_EN	R/W	X	Divider Dn Enable 0 = Divider n Disabled. SYSCLKn is also gated before and after divider Dn. 1 = Divider n Enabled
14	HALF_RATIO	R/W	0h	Ratio is in half steps. Example 1: if RATIO = 00000 and HALFRATIO = 1 the divider will be /1.5. Example 2: RATIO = 10111 and HALFRATIO = 1 divider will be /24.5. Example 3: if RATIO = 00011 and HALFRATIO = 0 divider will be /4. THE HALF RATIO DIVIDER IS NOT A 50% DUTY CYCLE. It is a single 1x high clock pulse followed by low time until ratio is met. Note: To enable half step ratio dividers user must also set the associated bit in the PLLHDIVEN register PRIOR to writing the PLLDIVn register. If PLLHDIVEN register is not enabled then HALF_RATIO will not be writable. Changing the PLLHDIVEN register, set or clear, will not set or clear the HALF_RATIO bit in PLLDIVn register. This is to protect and enable backward compatible software in the chance it accidentally wrote this bit field.
13-8	RSVD	R/W	0h	Reserved
7-0	RATIO	R/W	X	Divider Dn Ratio (SYSCLKn divider) 00000 = /1 00001 = /2 00010 = /3 00011 = /4 00100 = /5 00101 = 6 00110 = /7 00111 = /8 01000 = /9 01001 = /10 01010 = /11 01011 = /12 01100 = 13 01101 = /14 01110 = /15 01111 = /16 10000 = /17 10001 = /18 10010 = /19 10011 = /20 10100 = /21 10101 = /22 10110 = /23 10111 = /24 11000 = /25 11001 = /26 11010 = /27 11011 = /28 11100 = /29 11101 = /30 11110 = /31 11111 = /32 Note that the actual PLLDIVx divide ratio will not be modified when this field is written to. User must also set the GOSET bit so that the SYSCLKs selected in ALNCTL can change their RATIOs to the new values and remain phase-aligned. Note: see HALF_RATIO bit.

4.6.1.5 PLLCMD Register (Offset = 138h) [reset = 0h]

PLLCMD is shown in Figure 5-503 and described in Table 5-1006.

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PLL Controller command register

Table 5-1005 PLLCMD Instances

Instance	Physical Address
PLLCTRL0	0041 0138h
MCU_PLLCTRL0	4020 0138h

Figure 5-503 PLLCMD Register

31	30	29	28	27	26	25	24
RSVD
R/W-0h

23	22	21	20	19	18	17	16
RSVD
R/W-0h

15	14	13	12	11	10	9	8
RSVD
R/W-0h

7	6	5	4	3	2	1	0
RSVD						OSCPWRDN	GOSET
R/W-0h						R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1006 PLLCMD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RSVD	R/W	0h	Reserved
1	OSCPWRDN	R/W	0h	Oscillator Power Down Command 1: A write of 1 (doesn't need to be a transition from 0 to 1) to this bit initiates oscillator power down command. 0: A write of 0 to this bit clears the bit to zero but causes no effect. Read from this field returns the value previously written. Once written a 1, the bit remains a 1 unless if user writes a 0 to it. Do not read this bit for status of oscillator power down. In the case when CLKMODE = 1 (CLKIN mode), write to OSCPWRDN bit still occurs, but no oscillator power down command is actually sent because osc is already in power down. Read from this bit returns the value written.
0	GOSET	R/W	0h	GO bit for SYSCLKx phase alignment. GOSET = 1: A write of 1 to this bit signifies that the new divide ratios in PLLDIV [1:n] are taken into account at the nearest possible rising edge to phase align the clocks. The actual SYSCLKx to be aligned are selected in register ALNCTL. When divide-ratio change and clock alignment are completed, GOSET remains 1. Subsequent write of 1 to this register (even though the field was already a 1) causes the command for divide-ratio change and clock alignment. GOSET = 0: A write of 0 to this bit clears the bit to zero but causes no effect. Read from this field returns the value previously written. When writing consecutively to this field, the user must poll the GOSTAT between accesses to see if previous command for clock alignment and divide-ratio change has completed. Otherwise operation is undefined. Do not read GOSET in this command register for status.

4.6.1.6 PLLSTAT Register (Offset = 13Ch) [reset = X]

PLLSTAT is shown in Figure 5-504 and described in Table 5-1008.

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PLL Controller status register

Table 5-1007 PLLSTAT Instances

Instance	Physical Address
PLLCTRL0	0041 013Ch
MCU_PLLCTRL0	4020 013Ch

Figure 5-504 PLLSTAT Register

31	30	29	28	27	26	25	24
RSVD
R/W-0h

23	22	21	20	19	18	17	16
RSVD
R/W-0h

15	14	13	12	11	10	9	8
RSVD
R/W-0h

7	6	5	4	3	2	1	0
RSVD					STABLE	LOCK	GOSET
R/W-0h					R-X	R-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1008 PLLSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RSVD	R/W	0h	Reserved
2	STABLE	R	X	OSCIN Stable This bit shows the status of the rstclk_cnt_done_po signal. It indicates if the rstclk counter has finished counting, implying that the OSCIN/CLKIN is stable. The d_rstclk_cnt_pi must be set properly to allow rstclk counter to count sufficient amount of time for clock sources to become stable. 0 = rstclk counter not done counting, implying OSCIN/CLKIN input may not yet be stable. 1 = OSCIN/CLKIN is assumed to be stable. This bit is set to 1 if any one of the three cases is true: - rstclk counter has finished counting d_rstclk_cnt_pi number of rstclk cycles. - rstclk counter is parametrized out and does not exist, in which case OSCIN/CLKIN is assumed to be stable when por_pi_n is de-asserted.
1	LOCK	R	0h	PLL Core STATUS This bit returns the lock status of the selected PLL core (if supported by PLL core). For example, if PLLSELB = 0 (PLLA selected), it reflects the status of pll_a_lock_i. If PLLSELB-1 (PLLB selected), it reflects the status of pll_b_lock_i. 0 = PLL core not locked. The corresponding PLL Controller output pll_[x]_lock_out = 0. (where [x] is a or b depending on PLLSELB). 1 = PLL core locked. The corresponding PLL Controller output pll_[x]_lock_out = 1. (where [x] is a or b depending on PLLSELB). Note that not all PLL Core supports the lock signal. Check the PLL used to see if it has a functional lock output. Therefore this bit may not need to be documented to users.
0	GOSET	R	0h	Reflects the status of GO transition. Read from this register returns the status of the GO operation. Writes to the register are ignored. GOSTAT = 1: This bit goes to 1 as soon as GOSET in PLLCMD is written to. It remains a 1 when GO operation (divide-ratio change and clock alignment) is in progress. This bit automatically clears to 0 when GO operation is completed. GOSTAT = 0: No GO operation in progress. Software note: Users must not initiate another GOSET operation in PLLCMD until GOSTAT is cleared to 0.

4.6.1.7 ALNCTL Register (Offset = 140h) [reset = 3h]

ALNCTL is shown in Figure 5-505 and described in Table 5-1010.

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PLL Controller clock align control register

Table 5-1009 ALNCTL Instances

Instance	Physical Address
PLLCTRL0	0041 0140h
MCU_PLLCTRL0	4020 0140h

Figure 5-505 ALNCTL Register

31	30	29	28	27	26	25	24
RSVD
R/W-0h

23	22	21	20	19	18	17	16
RSVD
R/W-0h

15	14	13	12	11	10	9	8
ALN
R/W-1h

7	6	5	4	3	2	1	0
ALN							ALN1
R/W-1h							R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-1010 ALNCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RSVD	R/W	0h	Reserved
15-1	ALN	R/W	1h	SYSCLKx needs to be aligned with other clocks selected in this register. ALNx = 0: Do not need to align SYSCLKx to other clocks. SYSCLKx is left free-running. ALNx = 1: Align SYSCLKx to other clocks selected in this register Software note: This bit should only be modified when GOSTAT is 0. Software note: In the case when a divider is disabled (DxEN = 0) but the respective ALNx = 1, GO operation should ignore ALNx = 1. DxEN takes priority. Existence of ALN [8:3] are determined by RTL parameter SYSCLK. If the corresponding SYSCLK does not exist, the ALNx bit will be read-only and default to 0.
0	ALN1	R/W	1h	SYSCLK1 needs to be aligned with other clocks selected in this register. ALN1 = 0: Do not need to align SYSCLK1 to other clocks. SYSCLK1 is left free-running. ALN1 = 1: Align SYSCLK1 to other clocks selected in this register Software note: This bit should only be modified when GOSTAT is 0. Software note: in the case when a divider is disabled (D1EN = 0) but ALN1 = 1, GO operation should ignore ALN1 = 1. D1EN takes priority.

4.6.1.8 DCHANGE Register (Offset = 144h) [reset = 0h]

DCHANGE is shown in Figure 5-506 and described in Table 5-1012.

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PLLDIV ratio change register

Table 5-1011 DCHANGE Instances

Instance	Physical Address
PLLCTRL0	0041 0144h
MCU_PLLCTRL0	4020 0144h

Figure 5-506 DCHANGE Register

31	30	29	28	27	26	25	24
RSVD
R/W-0h

23	22	21	20	19	18	17	16
RSVD
R/W-0h

15	14	13	12	11	10	9	8
SYS
R-0h

7	6	5	4	3	2	1	0
SYS							SYS1
R-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-1012 DCHANGE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RSVD	R/W	0h	Reserved
15-1	SYS	R	0h	SYSCLKx divide ratio has been modified. SYSCLKx ratio will be changed during GO operation. SYSx = 0: SYSCLKx ratio has not been modified. When GOSET is set, SYSCLKx will not be affected. SYSx = 1: SYSCLKx ratio has been modified. When GOSET is set, SYSCLKx will change to the new ratio.
0	SYS1	R	0h	SYSCLK1 divide ratio has been modified. SYSCLK1 ratio will be changed during GO operation. SYS1 = 0: SYSCLK1 ratio has not been modified. When GOSET is set, SYSCLK1 will not be affected. SYS1 = 1: SYSCLK1 ratio has been modified. When GOSET is set, SYSCLK1 will change to the new ratio.