SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There are some limitations that must be adhered to while issuing transactions to PCIe subsystem internal bus interface.
The PCIe subsystem operation is completely dependent upon the availability of the clock from the PLL that is inside the SERDES. All registers in the PCIe controller located in the core clock domain need the PLL to be in lock and properly configured. Register access transactions that are initiated before ensuring that the PLL is locked will result in a status error.
Since the remote configuration and I/O transaction windows are directly mapped to internal bus space, the software must care to not access these spaces when there is no operational PCIe link. No response may be generated for such transactions. It is recommended that checks be built into software to avoid remote accesses in the absence of an operational link.
For any type of write transactions, the byte enables can only have a single unbroken string of 1s. In other words, in a transaction, if a byte’s write strobe is set, then all following bytes must have write strobe set until the last byte with write enabled. "Holes" or "Zeros" in between the byte enables are not allowed.
Since the internal bus width is greater that 32-bit, the TLP (Transaction Layer Packets) size will not be 1 (PCIe counts in 32-bit units) and therefore, it is through the FBE/LBE (First/Last Byte Enable) that the actual data transfer size is controlled.
The PCIe core and respectively the PCIe subsystem does not support ‘fixed’ or ‘wrap’ burst types on its Target or Controller port. Transactions that require any burst type other than incremental burst type will result in unspecified behavior, possibly bus lock up.
The PCIe subsystem imposes a limitation of a maximum of 128-byte outbound read/write command. However, if the starting address is not aligned to an 8-byte boundary, then the maximum transaction size is reduced to 120 bytes. This limitation is placed to avoid arithmetic overflow in computing transaction length from CBA to AXI. Unspecified behavior will occur, if misaligned transactions in outbound direction are not limited to a maximum of 120 bytes.
Read interleaving refers to the process of returning split read responses from multiple transactions. This implies that read data is not guaranteed to be sent in sequential order (data for one transaction to be sent completely before the next). The PCIe core will not interleave read responses, if the outbound read command/transaction size does not exceed the maximum transaction size configured in the PCIe core.