Note: When using the OSPI Controller, the opcodes in
OSPI_DEV_INSTR_RD_CONFIG_REG[7-0] RD_OPCODE_NON_XIP_FLD,
OSPI_DEV_INSTR_WR_CONFIG_REG[7-0] WR_OPCODE_FLD and
OSPI_WRITE_COMPLETION_CTRL_REG[7-0] OPCODE_FLD bit fields shall not match the
opcode in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD bit field.
For high speed transfers PHY mode can be enabled and for optimal configuration PHY Pipeline mode is recommended. For more information, see Section 12.3.2.4.16.1, PHY Pipeline Mode.
To access the flash optimally, software must configure the controller accurately:
- Wait until any pending STIG or INDAC operation
has completed or poll OSPI_CONFIG_REG[31] IDLE_FLD bit.
- Disable the DAC through OSPI_CONFIG_REG[7]
ENB_DIR_ACC_CTLR_FLD bit. It is permitted, but not necessary to also disable
the OSPI controller completely via OSPI_CONFIG_REG[0] ENB_SPI_FLD bit.
- Update the OSPI_DEV_INSTR_RD_CONFIG_REG and
OSPI_DEV_INSTR_WR_CONFIG_REG registers for the instruction type you wish to
use for indirect and direct writes and reads.
- Update the OSPI_MODE_BIT_CONFIG_REG[7-0] MODE_FLD
bit field if mode bits have been enabled in the
OSPI_DEV_INSTR_RD_CONFIG_REG[20] MODE_BIT_ENABLE_FLD bit.
- Update the OSPI_DEV_SIZE_CONFIG_REG if the
contents are incorrect. Note parts or all of this register may have been
updated after initialization. The number of address bytes is a key
configuration setting required for performing reads and writes. The number
of bytes per page is required for performing any write. The number of bytes
per device block is only required if the write protect feature is used. If
the default values are correct for the target device, or if some of the
values (not including the number address bytes) were incorrect but device
writes were not permitted.
- Update the OSPI_DEV_DELAY_REG. This register
allows the user to tweak how the chip select is driven after each FLASH
access. This is required as each device may have different timing
requirements. As the serial clock frequency is increased, these timing
requirements become more important. Note the numbers programmed in this
register are based on the period of reference clock. Example: A device needs
50ns minimum time before CS can be re-asserted after it has been
de-asserted. By default, the controller will only provide a minimum of 1
SCLK period. When the device is operating at 100 MHz, the SCLK period is
only 10ns, so 40ns extra is required. Since the register defines the number
of reference clock cycles to add, and reference clock is running at 400 MHz
(2.5ns period), then the user should program a value of at least 16 to the
OSPI_DEV_DELAY_REG[31-24] D_NSS_FLD. This delay can be extended during
auto-polling phase. There is possibility to define the polling repetition
delay in the OSPI_WRITE_COMPLETION_CTRL_REG[31-24] POLL_REP_DELAY_FLD bit
field.
- Update the OSPI_REMAP_ADDR_REG register, if
required. Affects DAC path only.
- Setup and enable write protection registers
(OSPI_LOWER_WR_PROT_REG, OSPI_UPPER_WR_PROT_REG and OSPI_WR_PROT_CTRL_REG)
if they are required and if they have not already been setup from post
initialization.
- Enable required interrupts via the
OSPI_IRQ_MASK_REG register.
- Setup the baud rate divisor in the
OSPI_CONFIG_REG[22-19] MSTR_BAUD_DIV_FLD to define the required clock
frequency of the target device.
- Update the OSPI_RD_DATA_CAPTURE_REG register.
This register will delay when the read data is captured and can help when
the read data path from the device to the controller is long and the device
clock frequency is high. An update to this register may not be
necessary.
- Enable the OSPI controller and the DAC via the
OSPI_CONFIG_REG.