In the FIFO mode, the PRU_ICSSG UART0 generates the following two DMA events:
- Receive event (URXEVT): The trigger level
for the receiver FIFO (1, 4, 8, or 14 characters) is set with the FIFO control
UART_INT_FIFO[7-6] IIR_FIFOEN bitfield. Every time the trigger level
is reached or a receiver time-out occurs, the PRU_ICSSG UART0 sends a receive
event to the DMA controller. In response, the DMA controller reads the data from
the receiver FIFO by way of the receiver buffer register UART_RBR_TBR[7-0] RBR_DATA. Note that the receive event is not
asserted if the data at the top of the receiver FIFO is erroneous even if the
trigger level has been reached.
- Transmit event (UTXEVT): When the
transmitter FIFO is empty (when the last byte in the transmitter FIFO has been
copied to the transmitter shift register), the PRU_ICSSG UART0 sends an UTXEVT
signal to the DMA controller. In response, the DMA controller refills the
transmitter FIFO by way of the transmitter holding register (THR) - UART_RBR_TBR[7-0] RBR_DATA. The UTXEVT signal is also sent to the
DMA controller when the PRU_ICSSG UART0 is taken out of reset using the
[14]UTRST bit in the power and emulation management register (UART_PWR).
Activity in DMA channels can be synchronized to these events. In the non-FIFO mode, the PRU_ICSSG UART0 generates no DMA events. Any DMA channel synchronized to either of these events must be enabled at the time the PRU_ICSSG UART0 event is generated. Otherwise, the DMA channel will miss the event and, unless the PRU_ICSSG UART0 generates a new event, no data transfer will occur.